1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <dt-bindings/clock/imx8mq-clock.h>
8#include <dt-bindings/power/imx8mq-power.h>
9#include <dt-bindings/reset/imx8mq-reset.h>
10#include <dt-bindings/gpio/gpio.h>
11#include "dt-bindings/input/input.h"
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/thermal/thermal.h>
14#include <dt-bindings/interconnect/imx8mq.h>
15#include "imx8mq-pinfunc.h"
16
17/ {
18	interrupt-parent = <&gpc>;
19
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	aliases {
24		ethernet0 = &fec1;
25		gpio0 = &gpio1;
26		gpio1 = &gpio2;
27		gpio2 = &gpio3;
28		gpio3 = &gpio4;
29		gpio4 = &gpio5;
30		i2c0 = &i2c1;
31		i2c1 = &i2c2;
32		i2c2 = &i2c3;
33		i2c3 = &i2c4;
34		mmc0 = &usdhc1;
35		mmc1 = &usdhc2;
36		serial0 = &uart1;
37		serial1 = &uart2;
38		serial2 = &uart3;
39		serial3 = &uart4;
40		spi0 = &ecspi1;
41		spi1 = &ecspi2;
42		spi2 = &ecspi3;
43	};
44
45	ckil: clock-ckil {
46		compatible = "fixed-clock";
47		#clock-cells = <0>;
48		clock-frequency = <32768>;
49		clock-output-names = "ckil";
50	};
51
52	osc_25m: clock-osc-25m {
53		compatible = "fixed-clock";
54		#clock-cells = <0>;
55		clock-frequency = <25000000>;
56		clock-output-names = "osc_25m";
57	};
58
59	osc_27m: clock-osc-27m {
60		compatible = "fixed-clock";
61		#clock-cells = <0>;
62		clock-frequency = <27000000>;
63		clock-output-names = "osc_27m";
64	};
65
66	clk_ext1: clock-ext1 {
67		compatible = "fixed-clock";
68		#clock-cells = <0>;
69		clock-frequency = <133000000>;
70		clock-output-names = "clk_ext1";
71	};
72
73	clk_ext2: clock-ext2 {
74		compatible = "fixed-clock";
75		#clock-cells = <0>;
76		clock-frequency = <133000000>;
77		clock-output-names = "clk_ext2";
78	};
79
80	clk_ext3: clock-ext3 {
81		compatible = "fixed-clock";
82		#clock-cells = <0>;
83		clock-frequency = <133000000>;
84		clock-output-names = "clk_ext3";
85	};
86
87	clk_ext4: clock-ext4 {
88		compatible = "fixed-clock";
89		#clock-cells = <0>;
90		clock-frequency= <133000000>;
91		clock-output-names = "clk_ext4";
92	};
93
94	cpus {
95		#address-cells = <1>;
96		#size-cells = <0>;
97
98		A53_0: cpu@0 {
99			device_type = "cpu";
100			compatible = "arm,cortex-a53";
101			reg = <0x0>;
102			clock-latency = <61036>; /* two CLK32 periods */
103			clocks = <&clk IMX8MQ_CLK_ARM>;
104			enable-method = "psci";
105			next-level-cache = <&A53_L2>;
106			operating-points-v2 = <&a53_opp_table>;
107			#cooling-cells = <2>;
108			nvmem-cells = <&cpu_speed_grade>;
109			nvmem-cell-names = "speed_grade";
110		};
111
112		A53_1: cpu@1 {
113			device_type = "cpu";
114			compatible = "arm,cortex-a53";
115			reg = <0x1>;
116			clock-latency = <61036>; /* two CLK32 periods */
117			clocks = <&clk IMX8MQ_CLK_ARM>;
118			enable-method = "psci";
119			next-level-cache = <&A53_L2>;
120			operating-points-v2 = <&a53_opp_table>;
121			#cooling-cells = <2>;
122		};
123
124		A53_2: cpu@2 {
125			device_type = "cpu";
126			compatible = "arm,cortex-a53";
127			reg = <0x2>;
128			clock-latency = <61036>; /* two CLK32 periods */
129			clocks = <&clk IMX8MQ_CLK_ARM>;
130			enable-method = "psci";
131			next-level-cache = <&A53_L2>;
132			operating-points-v2 = <&a53_opp_table>;
133			#cooling-cells = <2>;
134		};
135
136		A53_3: cpu@3 {
137			device_type = "cpu";
138			compatible = "arm,cortex-a53";
139			reg = <0x3>;
140			clock-latency = <61036>; /* two CLK32 periods */
141			clocks = <&clk IMX8MQ_CLK_ARM>;
142			enable-method = "psci";
143			next-level-cache = <&A53_L2>;
144			operating-points-v2 = <&a53_opp_table>;
145			#cooling-cells = <2>;
146		};
147
148		A53_L2: l2-cache0 {
149			compatible = "cache";
150		};
151	};
152
153	a53_opp_table: opp-table {
154		compatible = "operating-points-v2";
155		opp-shared;
156
157		opp-800000000 {
158			opp-hz = /bits/ 64 <800000000>;
159			opp-microvolt = <900000>;
160			/* Industrial only */
161			opp-supported-hw = <0xf>, <0x4>;
162			clock-latency-ns = <150000>;
163			opp-suspend;
164		};
165
166		opp-1000000000 {
167			opp-hz = /bits/ 64 <1000000000>;
168			opp-microvolt = <900000>;
169			/* Consumer only */
170			opp-supported-hw = <0xe>, <0x3>;
171			clock-latency-ns = <150000>;
172			opp-suspend;
173		};
174
175		opp-1300000000 {
176			opp-hz = /bits/ 64 <1300000000>;
177			opp-microvolt = <1000000>;
178			opp-supported-hw = <0xc>, <0x4>;
179			clock-latency-ns = <150000>;
180			opp-suspend;
181		};
182
183		opp-1500000000 {
184			opp-hz = /bits/ 64 <1500000000>;
185			opp-microvolt = <1000000>;
186			opp-supported-hw = <0x8>, <0x3>;
187			clock-latency-ns = <150000>;
188			opp-suspend;
189		};
190	};
191
192	pmu {
193		compatible = "arm,cortex-a53-pmu";
194		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
195		interrupt-parent = <&gic>;
196	};
197
198	psci {
199		compatible = "arm,psci-1.0";
200		method = "smc";
201	};
202
203	thermal-zones {
204		cpu_thermal: cpu-thermal {
205			polling-delay-passive = <250>;
206			polling-delay = <2000>;
207			thermal-sensors = <&tmu 0>;
208
209			trips {
210				cpu_alert: cpu-alert {
211					temperature = <80000>;
212					hysteresis = <2000>;
213					type = "passive";
214				};
215
216				cpu-crit {
217					temperature = <90000>;
218					hysteresis = <2000>;
219					type = "critical";
220				};
221			};
222
223			cooling-maps {
224				map0 {
225					trip = <&cpu_alert>;
226					cooling-device =
227						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
228						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
229						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
230						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
231				};
232			};
233		};
234
235		gpu-thermal {
236			polling-delay-passive = <250>;
237			polling-delay = <2000>;
238			thermal-sensors = <&tmu 1>;
239
240			trips {
241				gpu_alert: gpu-alert {
242					temperature = <80000>;
243					hysteresis = <2000>;
244					type = "passive";
245				};
246
247				gpu-crit {
248					temperature = <90000>;
249					hysteresis = <2000>;
250					type = "critical";
251				};
252			};
253
254			cooling-maps {
255				map0 {
256					trip = <&gpu_alert>;
257					cooling-device =
258						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
259				};
260			};
261		};
262
263		vpu-thermal {
264			polling-delay-passive = <250>;
265			polling-delay = <2000>;
266			thermal-sensors = <&tmu 2>;
267
268			trips {
269				vpu-crit {
270					temperature = <90000>;
271					hysteresis = <2000>;
272					type = "critical";
273				};
274			};
275		};
276	};
277
278	timer {
279		compatible = "arm,armv8-timer";
280		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
281		             <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
282		             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
283		             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
284		interrupt-parent = <&gic>;
285		arm,no-tick-in-suspend;
286	};
287
288	soc@0 {
289		compatible = "fsl,imx8mq-soc", "simple-bus";
290		#address-cells = <1>;
291		#size-cells = <1>;
292		ranges = <0x0 0x0 0x0 0x3e000000>;
293		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
294		nvmem-cells = <&imx8mq_uid>;
295		nvmem-cell-names = "soc_unique_id";
296
297		bus@30000000 { /* AIPS1 */
298			compatible = "fsl,aips-bus", "simple-bus";
299			reg = <0x30000000 0x400000>;
300			#address-cells = <1>;
301			#size-cells = <1>;
302			ranges = <0x30000000 0x30000000 0x400000>;
303
304			sai1: sai@30010000 {
305				#sound-dai-cells = <0>;
306				compatible = "fsl,imx8mq-sai";
307				reg = <0x30010000 0x10000>;
308				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
309				clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
310				         <&clk IMX8MQ_CLK_SAI1_ROOT>,
311				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
312				clock-names = "bus", "mclk1", "mclk2", "mclk3";
313				dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
314				dma-names = "rx", "tx";
315				status = "disabled";
316			};
317
318			sai6: sai@30030000 {
319				#sound-dai-cells = <0>;
320				compatible = "fsl,imx8mq-sai";
321				reg = <0x30030000 0x10000>;
322				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
323				clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
324				         <&clk IMX8MQ_CLK_SAI6_ROOT>,
325				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
326				clock-names = "bus", "mclk1", "mclk2", "mclk3";
327				dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
328				dma-names = "rx", "tx";
329				status = "disabled";
330			};
331
332			sai5: sai@30040000 {
333				#sound-dai-cells = <0>;
334				compatible = "fsl,imx8mq-sai";
335				reg = <0x30040000 0x10000>;
336				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
337				clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
338				         <&clk IMX8MQ_CLK_SAI5_ROOT>,
339				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
340				clock-names = "bus", "mclk1", "mclk2", "mclk3";
341				dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
342				dma-names = "rx", "tx";
343				status = "disabled";
344			};
345
346			sai4: sai@30050000 {
347				#sound-dai-cells = <0>;
348				compatible = "fsl,imx8mq-sai";
349				reg = <0x30050000 0x10000>;
350				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
351				clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
352				         <&clk IMX8MQ_CLK_SAI4_ROOT>,
353				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
354				clock-names = "bus", "mclk1", "mclk2", "mclk3";
355				dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
356				dma-names = "rx", "tx";
357				status = "disabled";
358			};
359
360			gpio1: gpio@30200000 {
361				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
362				reg = <0x30200000 0x10000>;
363				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
364				             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
365				clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
366				gpio-controller;
367				#gpio-cells = <2>;
368				interrupt-controller;
369				#interrupt-cells = <2>;
370				gpio-ranges = <&iomuxc 0 10 30>;
371			};
372
373			gpio2: gpio@30210000 {
374				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
375				reg = <0x30210000 0x10000>;
376				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
377				             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
378				clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
379				gpio-controller;
380				#gpio-cells = <2>;
381				interrupt-controller;
382				#interrupt-cells = <2>;
383				gpio-ranges = <&iomuxc 0 40 21>;
384			};
385
386			gpio3: gpio@30220000 {
387				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
388				reg = <0x30220000 0x10000>;
389				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
390				             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
391				clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
392				gpio-controller;
393				#gpio-cells = <2>;
394				interrupt-controller;
395				#interrupt-cells = <2>;
396				gpio-ranges = <&iomuxc 0 61 26>;
397			};
398
399			gpio4: gpio@30230000 {
400				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
401				reg = <0x30230000 0x10000>;
402				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
403				             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
404				clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
405				gpio-controller;
406				#gpio-cells = <2>;
407				interrupt-controller;
408				#interrupt-cells = <2>;
409				gpio-ranges = <&iomuxc 0 87 32>;
410			};
411
412			gpio5: gpio@30240000 {
413				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
414				reg = <0x30240000 0x10000>;
415				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
416				             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
417				clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
418				gpio-controller;
419				#gpio-cells = <2>;
420				interrupt-controller;
421				#interrupt-cells = <2>;
422				gpio-ranges = <&iomuxc 0 119 30>;
423			};
424
425			tmu: tmu@30260000 {
426				compatible = "fsl,imx8mq-tmu";
427				reg = <0x30260000 0x10000>;
428				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
429				clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
430				little-endian;
431				fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
432				fsl,tmu-calibration = <0x00000000 0x00000023
433						       0x00000001 0x00000029
434						       0x00000002 0x0000002f
435						       0x00000003 0x00000035
436						       0x00000004 0x0000003d
437						       0x00000005 0x00000043
438						       0x00000006 0x0000004b
439						       0x00000007 0x00000051
440						       0x00000008 0x00000057
441						       0x00000009 0x0000005f
442						       0x0000000a 0x00000067
443						       0x0000000b 0x0000006f
444
445						       0x00010000 0x0000001b
446						       0x00010001 0x00000023
447						       0x00010002 0x0000002b
448						       0x00010003 0x00000033
449						       0x00010004 0x0000003b
450						       0x00010005 0x00000043
451						       0x00010006 0x0000004b
452						       0x00010007 0x00000055
453						       0x00010008 0x0000005d
454						       0x00010009 0x00000067
455						       0x0001000a 0x00000070
456
457						       0x00020000 0x00000017
458						       0x00020001 0x00000023
459						       0x00020002 0x0000002d
460						       0x00020003 0x00000037
461						       0x00020004 0x00000041
462						       0x00020005 0x0000004b
463						       0x00020006 0x00000057
464						       0x00020007 0x00000063
465						       0x00020008 0x0000006f
466
467						       0x00030000 0x00000015
468						       0x00030001 0x00000021
469						       0x00030002 0x0000002d
470						       0x00030003 0x00000039
471						       0x00030004 0x00000045
472						       0x00030005 0x00000053
473						       0x00030006 0x0000005f
474						       0x00030007 0x00000071>;
475				#thermal-sensor-cells =  <1>;
476			};
477
478			wdog1: watchdog@30280000 {
479				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
480				reg = <0x30280000 0x10000>;
481				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
482				clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
483				status = "disabled";
484			};
485
486			wdog2: watchdog@30290000 {
487				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
488				reg = <0x30290000 0x10000>;
489				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
490				clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
491				status = "disabled";
492			};
493
494			wdog3: watchdog@302a0000 {
495				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
496				reg = <0x302a0000 0x10000>;
497				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
498				clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
499				status = "disabled";
500			};
501
502			sdma2: sdma@302c0000 {
503				compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
504				reg = <0x302c0000 0x10000>;
505				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
506				clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
507					 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
508				clock-names = "ipg", "ahb";
509				#dma-cells = <3>;
510				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
511			};
512
513			lcdif: lcd-controller@30320000 {
514				compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
515				reg = <0x30320000 0x10000>;
516				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
517				clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
518				clock-names = "pix";
519				assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
520						  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
521						  <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
522						  <&clk IMX8MQ_VIDEO_PLL1>;
523				assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
524						  <&clk IMX8MQ_VIDEO_PLL1>,
525						  <&clk IMX8MQ_VIDEO_PLL1_OUT>;
526				assigned-clock-rates = <0>, <0>, <0>, <594000000>;
527				interconnects = <&noc IMX8MQ_ICM_LCDIF &noc IMX8MQ_ICS_DRAM>;
528				interconnect-names = "dram";
529				status = "disabled";
530
531				port@0 {
532					lcdif_mipi_dsi: endpoint {
533						remote-endpoint = <&mipi_dsi_lcdif_in>;
534					};
535				};
536			};
537
538			iomuxc: pinctrl@30330000 {
539				compatible = "fsl,imx8mq-iomuxc";
540				reg = <0x30330000 0x10000>;
541			};
542
543			iomuxc_gpr: syscon@30340000 {
544				compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
545					     "syscon", "simple-mfd";
546				reg = <0x30340000 0x10000>;
547
548				mux: mux-controller {
549					compatible = "mmio-mux";
550					#mux-control-cells = <1>;
551					mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
552				};
553			};
554
555			ocotp: efuse@30350000 {
556				compatible = "fsl,imx8mq-ocotp", "syscon";
557				reg = <0x30350000 0x10000>;
558				clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
559				#address-cells = <1>;
560				#size-cells = <1>;
561
562				imx8mq_uid: soc-uid@410 {
563					reg = <0x4 0x8>;
564				};
565
566				cpu_speed_grade: speed-grade@10 {
567					reg = <0x10 4>;
568				};
569
570				fec_mac_address: mac-address@90 {
571					reg = <0x90 6>;
572				};
573			};
574
575			anatop: syscon@30360000 {
576				compatible = "fsl,imx8mq-anatop", "syscon";
577				reg = <0x30360000 0x10000>;
578				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
579			};
580
581			snvs: snvs@30370000 {
582				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
583				reg = <0x30370000 0x10000>;
584
585				snvs_rtc: snvs-rtc-lp{
586					compatible = "fsl,sec-v4.0-mon-rtc-lp";
587					regmap =<&snvs>;
588					offset = <0x34>;
589					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
590						<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
591					clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
592					clock-names = "snvs-rtc";
593				};
594
595				snvs_pwrkey: snvs-powerkey {
596					compatible = "fsl,sec-v4.0-pwrkey";
597					regmap = <&snvs>;
598					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
599					clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
600					clock-names = "snvs-pwrkey";
601					linux,keycode = <KEY_POWER>;
602					wakeup-source;
603					status = "disabled";
604				};
605			};
606
607			clk: clock-controller@30380000 {
608				compatible = "fsl,imx8mq-ccm";
609				reg = <0x30380000 0x10000>;
610				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
611				             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
612				#clock-cells = <1>;
613				clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
614				         <&clk_ext1>, <&clk_ext2>,
615				         <&clk_ext3>, <&clk_ext4>;
616				clock-names = "ckil", "osc_25m", "osc_27m",
617				              "clk_ext1", "clk_ext2",
618				              "clk_ext3", "clk_ext4";
619				assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
620						  <&clk IMX8MQ_CLK_A53_CORE>,
621						  <&clk IMX8MQ_CLK_NOC>,
622						  <&clk IMX8MQ_CLK_AUDIO_AHB>,
623						  <&clk IMX8MQ_AUDIO_PLL1_BYPASS>,
624						  <&clk IMX8MQ_AUDIO_PLL2_BYPASS>,
625						  <&clk IMX8MQ_AUDIO_PLL1>,
626						  <&clk IMX8MQ_AUDIO_PLL2>;
627				assigned-clock-rates = <0>, <0>,
628						       <800000000>,
629						       <0>,
630						       <0>,
631						       <0>,
632						       <786432000>,
633						       <722534400>;
634				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
635							 <&clk IMX8MQ_ARM_PLL_OUT>,
636							 <0>,
637							 <&clk IMX8MQ_SYS2_PLL_500M>,
638							 <&clk IMX8MQ_AUDIO_PLL1>,
639							 <&clk IMX8MQ_AUDIO_PLL2>;
640			};
641
642			src: reset-controller@30390000 {
643				compatible = "fsl,imx8mq-src", "syscon";
644				reg = <0x30390000 0x10000>;
645				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
646				#reset-cells = <1>;
647			};
648
649			gpc: gpc@303a0000 {
650				compatible = "fsl,imx8mq-gpc";
651				reg = <0x303a0000 0x10000>;
652				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
653				interrupt-parent = <&gic>;
654				interrupt-controller;
655				#interrupt-cells = <3>;
656
657				pgc {
658					#address-cells = <1>;
659					#size-cells = <0>;
660
661					pgc_mipi: power-domain@0 {
662						#power-domain-cells = <0>;
663						reg = <IMX8M_POWER_DOMAIN_MIPI>;
664					};
665
666					/*
667					 * As per comment in ATF source code:
668					 *
669					 * PCIE1 and PCIE2 share the
670					 * same reset signal, if we
671					 * power down PCIE2, PCIE1
672					 * will be held in reset too.
673					 *
674					 * So instead of creating two
675					 * separate power domains for
676					 * PCIE1 and PCIE2 we create a
677					 * link between both and use
678					 * it as a shared PCIE power
679					 * domain.
680					 */
681					pgc_pcie: power-domain@1 {
682						#power-domain-cells = <0>;
683						reg = <IMX8M_POWER_DOMAIN_PCIE1>;
684						power-domains = <&pgc_pcie2>;
685					};
686
687					pgc_otg1: power-domain@2 {
688						#power-domain-cells = <0>;
689						reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
690					};
691
692					pgc_otg2: power-domain@3 {
693						#power-domain-cells = <0>;
694						reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
695					};
696
697					pgc_ddr1: power-domain@4 {
698						#power-domain-cells = <0>;
699						reg = <IMX8M_POWER_DOMAIN_DDR1>;
700					};
701
702					pgc_gpu: power-domain@5 {
703						#power-domain-cells = <0>;
704						reg = <IMX8M_POWER_DOMAIN_GPU>;
705						clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
706						         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
707							 <&clk IMX8MQ_CLK_GPU_AXI>,
708						         <&clk IMX8MQ_CLK_GPU_AHB>;
709					};
710
711					pgc_vpu: power-domain@6 {
712						#power-domain-cells = <0>;
713						reg = <IMX8M_POWER_DOMAIN_VPU>;
714						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
715					};
716
717					pgc_disp: power-domain@7 {
718						#power-domain-cells = <0>;
719						reg = <IMX8M_POWER_DOMAIN_DISP>;
720					};
721
722					pgc_mipi_csi1: power-domain@8 {
723						#power-domain-cells = <0>;
724						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
725					};
726
727					pgc_mipi_csi2: power-domain@9 {
728						#power-domain-cells = <0>;
729						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
730					};
731
732					pgc_pcie2: power-domain@a {
733						#power-domain-cells = <0>;
734						reg = <IMX8M_POWER_DOMAIN_PCIE2>;
735					};
736				};
737			};
738		};
739
740		bus@30400000 { /* AIPS2 */
741			compatible = "fsl,aips-bus", "simple-bus";
742			reg = <0x30400000 0x400000>;
743			#address-cells = <1>;
744			#size-cells = <1>;
745			ranges = <0x30400000 0x30400000 0x400000>;
746
747			pwm1: pwm@30660000 {
748				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
749				reg = <0x30660000 0x10000>;
750				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
751				clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
752				         <&clk IMX8MQ_CLK_PWM1_ROOT>;
753				clock-names = "ipg", "per";
754				#pwm-cells = <2>;
755				status = "disabled";
756			};
757
758			pwm2: pwm@30670000 {
759				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
760				reg = <0x30670000 0x10000>;
761				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
762				clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
763				         <&clk IMX8MQ_CLK_PWM2_ROOT>;
764				clock-names = "ipg", "per";
765				#pwm-cells = <2>;
766				status = "disabled";
767			};
768
769			pwm3: pwm@30680000 {
770				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
771				reg = <0x30680000 0x10000>;
772				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
773				clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
774				         <&clk IMX8MQ_CLK_PWM3_ROOT>;
775				clock-names = "ipg", "per";
776				#pwm-cells = <2>;
777				status = "disabled";
778			};
779
780			pwm4: pwm@30690000 {
781				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
782				reg = <0x30690000 0x10000>;
783				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
784				clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
785				         <&clk IMX8MQ_CLK_PWM4_ROOT>;
786				clock-names = "ipg", "per";
787				#pwm-cells = <2>;
788				status = "disabled";
789			};
790
791			system_counter: timer@306a0000 {
792				compatible = "nxp,sysctr-timer";
793				reg = <0x306a0000 0x20000>;
794				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
795				clocks = <&osc_25m>;
796				clock-names = "per";
797			};
798		};
799
800		bus@30800000 { /* AIPS3 */
801			compatible = "fsl,aips-bus", "simple-bus";
802			reg = <0x30800000 0x400000>;
803			#address-cells = <1>;
804			#size-cells = <1>;
805			ranges = <0x30800000 0x30800000 0x400000>,
806				 <0x08000000 0x08000000 0x10000000>;
807
808			spdif1: spdif@30810000 {
809				compatible = "fsl,imx35-spdif";
810				reg = <0x30810000 0x10000>;
811				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
812				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
813					<&clk IMX8MQ_CLK_25M>, /* rxtx0 */
814					<&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
815					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
816					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
817					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
818					<&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
819					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
820					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
821					<&clk IMX8MQ_CLK_DUMMY>; /* spba */
822				clock-names = "core", "rxtx0",
823					      "rxtx1", "rxtx2",
824					      "rxtx3", "rxtx4",
825					      "rxtx5", "rxtx6",
826					      "rxtx7", "spba";
827				dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
828				dma-names = "rx", "tx";
829				status = "disabled";
830			};
831
832			ecspi1: spi@30820000 {
833				#address-cells = <1>;
834				#size-cells = <0>;
835				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
836				reg = <0x30820000 0x10000>;
837				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
838				clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
839					 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
840				clock-names = "ipg", "per";
841				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
842				dma-names = "rx", "tx";
843				status = "disabled";
844			};
845
846			ecspi2: spi@30830000 {
847				#address-cells = <1>;
848				#size-cells = <0>;
849				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
850				reg = <0x30830000 0x10000>;
851				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
852				clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
853					 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
854				clock-names = "ipg", "per";
855				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
856				dma-names = "rx", "tx";
857				status = "disabled";
858			};
859
860			ecspi3: spi@30840000 {
861				#address-cells = <1>;
862				#size-cells = <0>;
863				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
864				reg = <0x30840000 0x10000>;
865				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
866				clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
867					 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
868				clock-names = "ipg", "per";
869				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
870				dma-names = "rx", "tx";
871				status = "disabled";
872			};
873
874			uart1: serial@30860000 {
875				compatible = "fsl,imx8mq-uart",
876				             "fsl,imx6q-uart";
877				reg = <0x30860000 0x10000>;
878				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
879				clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
880				         <&clk IMX8MQ_CLK_UART1_ROOT>;
881				clock-names = "ipg", "per";
882				status = "disabled";
883			};
884
885			uart3: serial@30880000 {
886				compatible = "fsl,imx8mq-uart",
887				             "fsl,imx6q-uart";
888				reg = <0x30880000 0x10000>;
889				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
890				clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
891				         <&clk IMX8MQ_CLK_UART3_ROOT>;
892				clock-names = "ipg", "per";
893				status = "disabled";
894			};
895
896			uart2: serial@30890000 {
897				compatible = "fsl,imx8mq-uart",
898				             "fsl,imx6q-uart";
899				reg = <0x30890000 0x10000>;
900				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
901				clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
902				         <&clk IMX8MQ_CLK_UART2_ROOT>;
903				clock-names = "ipg", "per";
904				status = "disabled";
905			};
906
907			spdif2: spdif@308a0000 {
908				compatible = "fsl,imx35-spdif";
909				reg = <0x308a0000 0x10000>;
910				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
911				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
912					<&clk IMX8MQ_CLK_25M>, /* rxtx0 */
913					<&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
914					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
915					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
916					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
917					<&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
918					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
919					<&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
920					<&clk IMX8MQ_CLK_DUMMY>; /* spba */
921				clock-names = "core", "rxtx0",
922					      "rxtx1", "rxtx2",
923					      "rxtx3", "rxtx4",
924					      "rxtx5", "rxtx6",
925					      "rxtx7", "spba";
926				dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
927				dma-names = "rx", "tx";
928				status = "disabled";
929			};
930
931			sai2: sai@308b0000 {
932				#sound-dai-cells = <0>;
933				compatible = "fsl,imx8mq-sai";
934				reg = <0x308b0000 0x10000>;
935				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
936				clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
937					 <&clk IMX8MQ_CLK_SAI2_ROOT>,
938					 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
939				clock-names = "bus", "mclk1", "mclk2", "mclk3";
940				dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
941				dma-names = "rx", "tx";
942				status = "disabled";
943			};
944
945			sai3: sai@308c0000 {
946				#sound-dai-cells = <0>;
947				compatible = "fsl,imx8mq-sai";
948				reg = <0x308c0000 0x10000>;
949				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
950				clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
951				         <&clk IMX8MQ_CLK_SAI3_ROOT>,
952				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
953				clock-names = "bus", "mclk1", "mclk2", "mclk3";
954				dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
955				dma-names = "rx", "tx";
956				status = "disabled";
957			};
958
959			crypto: crypto@30900000 {
960				compatible = "fsl,sec-v4.0";
961				#address-cells = <1>;
962				#size-cells = <1>;
963				reg = <0x30900000 0x40000>;
964				ranges = <0 0x30900000 0x40000>;
965				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
966				clocks = <&clk IMX8MQ_CLK_AHB>,
967					 <&clk IMX8MQ_CLK_IPG_ROOT>;
968				clock-names = "aclk", "ipg";
969
970				sec_jr0: jr@1000 {
971					compatible = "fsl,sec-v4.0-job-ring";
972					reg = <0x1000 0x1000>;
973					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
974				};
975
976				sec_jr1: jr@2000 {
977					compatible = "fsl,sec-v4.0-job-ring";
978					reg = <0x2000 0x1000>;
979					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
980				};
981
982				sec_jr2: jr@3000 {
983					compatible = "fsl,sec-v4.0-job-ring";
984					reg = <0x3000 0x1000>;
985					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
986				};
987			};
988
989			mipi_dsi: mipi-dsi@30a00000 {
990				compatible = "fsl,imx8mq-nwl-dsi";
991				reg = <0x30a00000 0x300>;
992				clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
993					 <&clk IMX8MQ_CLK_DSI_AHB>,
994					 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
995					 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
996					 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
997				clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
998				assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
999						  <&clk IMX8MQ_CLK_DSI_CORE>,
1000						  <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
1001				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1002							 <&clk IMX8MQ_SYS1_PLL_266M>;
1003				assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1004				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1005				mux-controls = <&mux 0>;
1006				power-domains = <&pgc_mipi>;
1007				phys = <&dphy>;
1008				phy-names = "dphy";
1009				resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
1010					 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
1011					 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
1012					 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
1013				reset-names = "byte", "dpi", "esc", "pclk";
1014				status = "disabled";
1015
1016				ports {
1017					#address-cells = <1>;
1018					#size-cells = <0>;
1019
1020					port@0 {
1021						reg = <0>;
1022						#address-cells = <1>;
1023						#size-cells = <0>;
1024						mipi_dsi_lcdif_in: endpoint@0 {
1025							reg = <0>;
1026							remote-endpoint = <&lcdif_mipi_dsi>;
1027						};
1028					};
1029				};
1030			};
1031
1032			dphy: dphy@30a00300 {
1033				compatible = "fsl,imx8mq-mipi-dphy";
1034				reg = <0x30a00300 0x100>;
1035				clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
1036				clock-names = "phy_ref";
1037				assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1038						  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
1039						  <&clk IMX8MQ_CLK_DSI_PHY_REF>,
1040						  <&clk IMX8MQ_VIDEO_PLL1>;
1041				assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
1042						  <&clk IMX8MQ_VIDEO_PLL1>,
1043						  <&clk IMX8MQ_VIDEO_PLL1_OUT>;
1044				assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1045				#phy-cells = <0>;
1046				power-domains = <&pgc_mipi>;
1047				status = "disabled";
1048			};
1049
1050			i2c1: i2c@30a20000 {
1051				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1052				reg = <0x30a20000 0x10000>;
1053				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1054				clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
1055				#address-cells = <1>;
1056				#size-cells = <0>;
1057				status = "disabled";
1058			};
1059
1060			i2c2: i2c@30a30000 {
1061				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1062				reg = <0x30a30000 0x10000>;
1063				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1064				clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
1065				#address-cells = <1>;
1066				#size-cells = <0>;
1067				status = "disabled";
1068			};
1069
1070			i2c3: i2c@30a40000 {
1071				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1072				reg = <0x30a40000 0x10000>;
1073				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1074				clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
1075				#address-cells = <1>;
1076				#size-cells = <0>;
1077				status = "disabled";
1078			};
1079
1080			i2c4: i2c@30a50000 {
1081				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1082				reg = <0x30a50000 0x10000>;
1083				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1084				clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
1085				#address-cells = <1>;
1086				#size-cells = <0>;
1087				status = "disabled";
1088			};
1089
1090			uart4: serial@30a60000 {
1091				compatible = "fsl,imx8mq-uart",
1092				             "fsl,imx6q-uart";
1093				reg = <0x30a60000 0x10000>;
1094				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1095				clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
1096				         <&clk IMX8MQ_CLK_UART4_ROOT>;
1097				clock-names = "ipg", "per";
1098				status = "disabled";
1099			};
1100
1101			mipi_csi1: csi@30a70000 {
1102				compatible = "fsl,imx8mq-mipi-csi2";
1103				reg = <0x30a70000 0x1000>;
1104				clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1105				   <&clk IMX8MQ_CLK_CSI1_ESC>,
1106				   <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
1107				clock-names = "core", "esc", "ui";
1108				assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1109				    <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
1110				    <&clk IMX8MQ_CLK_CSI1_ESC>;
1111				assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1112				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1113					<&clk IMX8MQ_SYS2_PLL_1000M>,
1114					<&clk IMX8MQ_SYS1_PLL_800M>;
1115				power-domains = <&pgc_mipi_csi1>;
1116				resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
1117					 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
1118					 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
1119				fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1120				interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
1121				interconnect-names = "dram";
1122				status = "disabled";
1123
1124				ports {
1125					#address-cells = <1>;
1126					#size-cells = <0>;
1127
1128					port@0 {
1129						reg = <0>;
1130
1131						csi1_mipi_ep: endpoint {
1132							remote-endpoint = <&csi1_ep>;
1133						};
1134					};
1135				};
1136			};
1137
1138			csi1: csi@30a90000 {
1139				compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
1140				reg = <0x30a90000 0x10000>;
1141				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1142				clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
1143				clock-names = "mclk";
1144				status = "disabled";
1145
1146				port {
1147					csi1_ep: endpoint {
1148						remote-endpoint = <&csi1_mipi_ep>;
1149					};
1150				};
1151			};
1152
1153			mipi_csi2: csi@30b60000 {
1154				compatible = "fsl,imx8mq-mipi-csi2";
1155				reg = <0x30b60000 0x1000>;
1156				clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1157				   <&clk IMX8MQ_CLK_CSI2_ESC>,
1158				   <&clk IMX8MQ_CLK_CSI2_PHY_REF>;
1159				clock-names = "core", "esc", "ui";
1160				assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1161				    <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
1162				    <&clk IMX8MQ_CLK_CSI2_ESC>;
1163				assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1164				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1165					<&clk IMX8MQ_SYS2_PLL_1000M>,
1166					<&clk IMX8MQ_SYS1_PLL_800M>;
1167				power-domains = <&pgc_mipi_csi2>;
1168				resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,
1169					 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,
1170					 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;
1171				fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1172				interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
1173				interconnect-names = "dram";
1174				status = "disabled";
1175
1176				ports {
1177					#address-cells = <1>;
1178					#size-cells = <0>;
1179
1180					port@0 {
1181						reg = <0>;
1182
1183						csi2_mipi_ep: endpoint {
1184							remote-endpoint = <&csi2_ep>;
1185						};
1186					};
1187				};
1188			};
1189
1190			csi2: csi@30b80000 {
1191				compatible = "fsl,imx8mq-csi", "fsl,imx7-csi";
1192				reg = <0x30b80000 0x10000>;
1193				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1194				clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
1195				clock-names = "mclk";
1196				status = "disabled";
1197
1198				port {
1199					csi2_ep: endpoint {
1200						remote-endpoint = <&csi2_mipi_ep>;
1201					};
1202				};
1203			};
1204
1205			mu: mailbox@30aa0000 {
1206				compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1207				reg = <0x30aa0000 0x10000>;
1208				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1209				clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
1210				#mbox-cells = <2>;
1211			};
1212
1213			usdhc1: mmc@30b40000 {
1214				compatible = "fsl,imx8mq-usdhc",
1215				             "fsl,imx7d-usdhc";
1216				reg = <0x30b40000 0x10000>;
1217				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1218				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1219				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1220				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
1221				clock-names = "ipg", "ahb", "per";
1222				fsl,tuning-start-tap = <20>;
1223				fsl,tuning-step = <2>;
1224				bus-width = <4>;
1225				status = "disabled";
1226			};
1227
1228			usdhc2: mmc@30b50000 {
1229				compatible = "fsl,imx8mq-usdhc",
1230				             "fsl,imx7d-usdhc";
1231				reg = <0x30b50000 0x10000>;
1232				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1233				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1234				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1235				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
1236				clock-names = "ipg", "ahb", "per";
1237				fsl,tuning-start-tap = <20>;
1238				fsl,tuning-step = <2>;
1239				bus-width = <4>;
1240				status = "disabled";
1241			};
1242
1243			qspi0: spi@30bb0000 {
1244				#address-cells = <1>;
1245				#size-cells = <0>;
1246				compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1247				reg = <0x30bb0000 0x10000>,
1248				      <0x08000000 0x10000000>;
1249				reg-names = "QuadSPI", "QuadSPI-memory";
1250				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1251				clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
1252					 <&clk IMX8MQ_CLK_QSPI_ROOT>;
1253				clock-names = "qspi_en", "qspi";
1254				status = "disabled";
1255			};
1256
1257			sdma1: sdma@30bd0000 {
1258				compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1259				reg = <0x30bd0000 0x10000>;
1260				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1261				clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
1262					 <&clk IMX8MQ_CLK_AHB>;
1263				clock-names = "ipg", "ahb";
1264				#dma-cells = <3>;
1265				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1266			};
1267
1268			fec1: ethernet@30be0000 {
1269				compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1270				reg = <0x30be0000 0x10000>;
1271				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1272				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1273					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1274					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1275				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1276				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
1277				         <&clk IMX8MQ_CLK_ENET_TIMER>,
1278				         <&clk IMX8MQ_CLK_ENET_REF>,
1279				         <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1280				clock-names = "ipg", "ahb", "ptp",
1281				              "enet_clk_ref", "enet_out";
1282				assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
1283						  <&clk IMX8MQ_CLK_ENET_TIMER>,
1284						  <&clk IMX8MQ_CLK_ENET_REF>,
1285						  <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1286				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1287							 <&clk IMX8MQ_SYS2_PLL_100M>,
1288							 <&clk IMX8MQ_SYS2_PLL_125M>,
1289							 <&clk IMX8MQ_SYS2_PLL_50M>;
1290				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1291				fsl,num-tx-queues = <3>;
1292				fsl,num-rx-queues = <3>;
1293				nvmem-cells = <&fec_mac_address>;
1294				nvmem-cell-names = "mac-address";
1295				nvmem_macaddr_swap;
1296				fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1297				status = "disabled";
1298			};
1299		};
1300
1301		noc: interconnect@32700000 {
1302			compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
1303			reg = <0x32700000 0x100000>;
1304			clocks = <&clk IMX8MQ_CLK_NOC>;
1305			fsl,ddrc = <&ddrc>;
1306			#interconnect-cells = <1>;
1307			operating-points-v2 = <&noc_opp_table>;
1308
1309			noc_opp_table: opp-table {
1310				compatible = "operating-points-v2";
1311
1312				opp-133M {
1313					opp-hz = /bits/ 64 <133333333>;
1314				};
1315
1316				opp-400M {
1317					opp-hz = /bits/ 64 <400000000>;
1318				};
1319
1320				opp-800M {
1321					opp-hz = /bits/ 64 <800000000>;
1322				};
1323			};
1324		};
1325
1326		bus@32c00000 { /* AIPS4 */
1327			compatible = "fsl,aips-bus", "simple-bus";
1328			reg = <0x32c00000 0x400000>;
1329			#address-cells = <1>;
1330			#size-cells = <1>;
1331			ranges = <0x32c00000 0x32c00000 0x400000>;
1332
1333			irqsteer: interrupt-controller@32e2d000 {
1334				compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1335				reg = <0x32e2d000 0x1000>;
1336				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1337				clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
1338				clock-names = "ipg";
1339				fsl,channel = <0>;
1340				fsl,num-irqs = <64>;
1341				interrupt-controller;
1342				#interrupt-cells = <1>;
1343			};
1344		};
1345
1346		gpu: gpu@38000000 {
1347			compatible = "vivante,gc";
1348			reg = <0x38000000 0x40000>;
1349			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1350			clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
1351			         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
1352			         <&clk IMX8MQ_CLK_GPU_AXI>,
1353			         <&clk IMX8MQ_CLK_GPU_AHB>;
1354			clock-names = "core", "shader", "bus", "reg";
1355			#cooling-cells = <2>;
1356			assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1357			                  <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
1358			                  <&clk IMX8MQ_CLK_GPU_AXI>,
1359			                  <&clk IMX8MQ_CLK_GPU_AHB>,
1360			                  <&clk IMX8MQ_GPU_PLL_BYPASS>;
1361			assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1362			                         <&clk IMX8MQ_GPU_PLL_OUT>,
1363			                         <&clk IMX8MQ_GPU_PLL_OUT>,
1364			                         <&clk IMX8MQ_GPU_PLL_OUT>,
1365			                         <&clk IMX8MQ_GPU_PLL>;
1366			assigned-clock-rates = <800000000>, <800000000>,
1367			                       <800000000>, <800000000>, <0>;
1368			power-domains = <&pgc_gpu>;
1369		};
1370
1371		usb_dwc3_0: usb@38100000 {
1372			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1373			reg = <0x38100000 0x10000>;
1374			clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
1375			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
1376				 <&clk IMX8MQ_CLK_32K>;
1377			clock-names = "bus_early", "ref", "suspend";
1378			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1379			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
1380			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1381			                         <&clk IMX8MQ_SYS1_PLL_100M>;
1382			assigned-clock-rates = <500000000>, <100000000>;
1383			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1384			phys = <&usb3_phy0>, <&usb3_phy0>;
1385			phy-names = "usb2-phy", "usb3-phy";
1386			power-domains = <&pgc_otg1>;
1387			usb3-resume-missing-cas;
1388			status = "disabled";
1389		};
1390
1391		usb3_phy0: usb-phy@381f0040 {
1392			compatible = "fsl,imx8mq-usb-phy";
1393			reg = <0x381f0040 0x40>;
1394			clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1395			clock-names = "phy";
1396			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1397			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1398			assigned-clock-rates = <100000000>;
1399			#phy-cells = <0>;
1400			status = "disabled";
1401		};
1402
1403		usb_dwc3_1: usb@38200000 {
1404			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1405			reg = <0x38200000 0x10000>;
1406			clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1407			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
1408				 <&clk IMX8MQ_CLK_32K>;
1409			clock-names = "bus_early", "ref", "suspend";
1410			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1411			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
1412			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1413			                         <&clk IMX8MQ_SYS1_PLL_100M>;
1414			assigned-clock-rates = <500000000>, <100000000>;
1415			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1416			phys = <&usb3_phy1>, <&usb3_phy1>;
1417			phy-names = "usb2-phy", "usb3-phy";
1418			power-domains = <&pgc_otg2>;
1419			usb3-resume-missing-cas;
1420			status = "disabled";
1421		};
1422
1423		usb3_phy1: usb-phy@382f0040 {
1424			compatible = "fsl,imx8mq-usb-phy";
1425			reg = <0x382f0040 0x40>;
1426			clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1427			clock-names = "phy";
1428			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1429			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1430			assigned-clock-rates = <100000000>;
1431			#phy-cells = <0>;
1432			status = "disabled";
1433		};
1434
1435		vpu: video-codec@38300000 {
1436			compatible = "nxp,imx8mq-vpu";
1437			reg = <0x38300000 0x10000>,
1438			      <0x38310000 0x10000>,
1439			      <0x38320000 0x10000>;
1440			reg-names = "g1", "g2", "ctrl";
1441			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1442				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1443			interrupt-names = "g1", "g2";
1444			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
1445				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
1446				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
1447			clock-names = "g1", "g2", "bus";
1448			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
1449					  <&clk IMX8MQ_CLK_VPU_G2>,
1450					  <&clk IMX8MQ_CLK_VPU_BUS>,
1451					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
1452			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
1453						 <&clk IMX8MQ_VPU_PLL_OUT>,
1454						 <&clk IMX8MQ_SYS1_PLL_800M>,
1455						 <&clk IMX8MQ_VPU_PLL>;
1456			assigned-clock-rates = <600000000>, <600000000>,
1457					       <800000000>, <0>;
1458			power-domains = <&pgc_vpu>;
1459		};
1460
1461		pcie0: pcie@33800000 {
1462			compatible = "fsl,imx8mq-pcie";
1463			reg = <0x33800000 0x400000>,
1464			      <0x1ff00000 0x80000>;
1465			reg-names = "dbi", "config";
1466			#address-cells = <3>;
1467			#size-cells = <2>;
1468			device_type = "pci";
1469			bus-range = <0x00 0xff>;
1470			ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1471			          0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1472			num-lanes = <1>;
1473			num-viewport = <4>;
1474			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1475			interrupt-names = "msi";
1476			#interrupt-cells = <1>;
1477			interrupt-map-mask = <0 0 0 0x7>;
1478			interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1479			                <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1480			                <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1481			                <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1482			fsl,max-link-speed = <2>;
1483			linux,pci-domain = <0>;
1484			power-domains = <&pgc_pcie>;
1485			resets = <&src IMX8MQ_RESET_PCIEPHY>,
1486			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1487			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1488			reset-names = "pciephy", "apps", "turnoff";
1489			assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1490			                  <&clk IMX8MQ_CLK_PCIE1_PHY>,
1491			                  <&clk IMX8MQ_CLK_PCIE1_AUX>;
1492			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1493			                         <&clk IMX8MQ_SYS2_PLL_100M>,
1494			                         <&clk IMX8MQ_SYS1_PLL_80M>;
1495			assigned-clock-rates = <250000000>, <100000000>,
1496			                       <10000000>;
1497			status = "disabled";
1498		};
1499
1500		pcie1: pcie@33c00000 {
1501			compatible = "fsl,imx8mq-pcie";
1502			reg = <0x33c00000 0x400000>,
1503			      <0x27f00000 0x80000>;
1504			reg-names = "dbi", "config";
1505			#address-cells = <3>;
1506			#size-cells = <2>;
1507			device_type = "pci";
1508			ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1509				   0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1510			num-lanes = <1>;
1511			num-viewport = <4>;
1512			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1513			interrupt-names = "msi";
1514			#interrupt-cells = <1>;
1515			interrupt-map-mask = <0 0 0 0x7>;
1516			interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1517					<0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1518					<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1519					<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1520			fsl,max-link-speed = <2>;
1521			linux,pci-domain = <1>;
1522			power-domains = <&pgc_pcie>;
1523			resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1524			         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1525			         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1526			reset-names = "pciephy", "apps", "turnoff";
1527			assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1528			                  <&clk IMX8MQ_CLK_PCIE2_PHY>,
1529			                  <&clk IMX8MQ_CLK_PCIE2_AUX>;
1530			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1531			                         <&clk IMX8MQ_SYS2_PLL_100M>,
1532			                         <&clk IMX8MQ_SYS1_PLL_80M>;
1533			assigned-clock-rates = <250000000>, <100000000>,
1534			                       <10000000>;
1535			status = "disabled";
1536		};
1537
1538		gic: interrupt-controller@38800000 {
1539			compatible = "arm,gic-v3";
1540			reg = <0x38800000 0x10000>,	/* GIC Dist */
1541			      <0x38880000 0xc0000>,	/* GICR */
1542			      <0x31000000 0x2000>,	/* GICC */
1543			      <0x31010000 0x2000>,	/* GICV */
1544			      <0x31020000 0x2000>;	/* GICH */
1545			#interrupt-cells = <3>;
1546			interrupt-controller;
1547			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1548			interrupt-parent = <&gic>;
1549		};
1550
1551		ddrc: memory-controller@3d400000 {
1552			compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1553			reg = <0x3d400000 0x400000>;
1554			clock-names = "core", "pll", "alt", "apb";
1555			clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1556				 <&clk IMX8MQ_DRAM_PLL_OUT>,
1557				 <&clk IMX8MQ_CLK_DRAM_ALT>,
1558				 <&clk IMX8MQ_CLK_DRAM_APB>;
1559		};
1560
1561		ddr-pmu@3d800000 {
1562			compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1563			reg = <0x3d800000 0x400000>;
1564			interrupt-parent = <&gic>;
1565			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1566		};
1567	};
1568};
1569