1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <dt-bindings/clock/imx8mq-clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include "imx8mq-pinfunc.h"
11
12/ {
13	/* This should really be the GPC, but we need a driver for this first */
14	interrupt-parent = <&gic>;
15
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	aliases {
20		i2c0 = &i2c1;
21		i2c1 = &i2c2;
22		i2c2 = &i2c3;
23		i2c3 = &i2c4;
24		serial0 = &uart1;
25		serial1 = &uart2;
26		serial2 = &uart3;
27		serial3 = &uart4;
28	};
29
30	ckil: clock-ckil {
31		compatible = "fixed-clock";
32		#clock-cells = <0>;
33		clock-frequency = <32768>;
34		clock-output-names = "ckil";
35	};
36
37	osc_25m: clock-osc-25m {
38		compatible = "fixed-clock";
39		#clock-cells = <0>;
40		clock-frequency = <25000000>;
41		clock-output-names = "osc_25m";
42	};
43
44	osc_27m: clock-osc-27m {
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		clock-frequency = <27000000>;
48		clock-output-names = "osc_27m";
49	};
50
51	clk_ext1: clock-ext1 {
52		compatible = "fixed-clock";
53		#clock-cells = <0>;
54		clock-frequency = <133000000>;
55		clock-output-names = "clk_ext1";
56	};
57
58	clk_ext2: clock-ext2 {
59		compatible = "fixed-clock";
60		#clock-cells = <0>;
61		clock-frequency = <133000000>;
62		clock-output-names = "clk_ext2";
63	};
64
65	clk_ext3: clock-ext3 {
66		compatible = "fixed-clock";
67		#clock-cells = <0>;
68		clock-frequency = <133000000>;
69		clock-output-names = "clk_ext3";
70	};
71
72	clk_ext4: clock-ext4 {
73		compatible = "fixed-clock";
74		#clock-cells = <0>;
75		clock-frequency= <133000000>;
76		clock-output-names = "clk_ext4";
77	};
78
79	cpus {
80		#address-cells = <1>;
81		#size-cells = <0>;
82
83		A53_0: cpu@0 {
84			device_type = "cpu";
85			compatible = "arm,cortex-a53";
86			reg = <0x0>;
87			enable-method = "psci";
88			next-level-cache = <&A53_L2>;
89		};
90
91		A53_1: cpu@1 {
92			device_type = "cpu";
93			compatible = "arm,cortex-a53";
94			reg = <0x1>;
95			enable-method = "psci";
96			next-level-cache = <&A53_L2>;
97		};
98
99		A53_2: cpu@2 {
100			device_type = "cpu";
101			compatible = "arm,cortex-a53";
102			reg = <0x2>;
103			enable-method = "psci";
104			next-level-cache = <&A53_L2>;
105		};
106
107		A53_3: cpu@3 {
108			device_type = "cpu";
109			compatible = "arm,cortex-a53";
110			reg = <0x3>;
111			enable-method = "psci";
112			next-level-cache = <&A53_L2>;
113		};
114
115		A53_L2: l2-cache0 {
116			compatible = "cache";
117		};
118	};
119
120	psci {
121		compatible = "arm,psci-1.0";
122		method = "smc";
123	};
124
125	timer {
126		compatible = "arm,armv8-timer";
127		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
128		             <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
129		             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
130		             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
131		interrupt-parent = <&gic>;
132		arm,no-tick-in-suspend;
133	};
134
135	soc@0 {
136		compatible = "simple-bus";
137		#address-cells = <1>;
138		#size-cells = <1>;
139		ranges = <0x0 0x0 0x0 0x3e000000>;
140
141		bus@30000000 { /* AIPS1 */
142			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
143			#address-cells = <1>;
144			#size-cells = <1>;
145			ranges = <0x30000000 0x30000000 0x400000>;
146
147			gpio1: gpio@30200000 {
148				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
149				reg = <0x30200000 0x10000>;
150				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
151				             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
152				gpio-controller;
153				#gpio-cells = <2>;
154				interrupt-controller;
155				#interrupt-cells = <2>;
156			};
157
158			gpio2: gpio@30210000 {
159				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
160				reg = <0x30210000 0x10000>;
161				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
162				             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
163				gpio-controller;
164				#gpio-cells = <2>;
165				interrupt-controller;
166				#interrupt-cells = <2>;
167			};
168
169			gpio3: gpio@30220000 {
170				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
171				reg = <0x30220000 0x10000>;
172				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
173				             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
174				gpio-controller;
175				#gpio-cells = <2>;
176				interrupt-controller;
177				#interrupt-cells = <2>;
178			};
179
180			gpio4: gpio@30230000 {
181				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
182				reg = <0x30230000 0x10000>;
183				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
184				             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
185				gpio-controller;
186				#gpio-cells = <2>;
187				interrupt-controller;
188				#interrupt-cells = <2>;
189			};
190
191			gpio5: gpio@30240000 {
192				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
193				reg = <0x30240000 0x10000>;
194				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
195				             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196				gpio-controller;
197				#gpio-cells = <2>;
198				interrupt-controller;
199				#interrupt-cells = <2>;
200			};
201
202			iomuxc: iomuxc@30330000 {
203				compatible = "fsl,imx8mq-iomuxc";
204				reg = <0x30330000 0x10000>;
205			};
206
207			iomuxc_gpr: syscon@30340000 {
208				compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
209				reg = <0x30340000 0x10000>;
210			};
211
212			anatop: syscon@30360000 {
213				compatible = "fsl,imx8mq-anatop", "syscon";
214				reg = <0x30360000 0x10000>;
215				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
216			};
217
218			clk: clock-controller@30380000 {
219				compatible = "fsl,imx8mq-ccm";
220				reg = <0x30380000 0x10000>;
221				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
222				             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
223				#clock-cells = <1>;
224				clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
225				         <&clk_ext1>, <&clk_ext2>,
226				         <&clk_ext3>, <&clk_ext4>;
227				clock-names = "ckil", "osc_25m", "osc_27m",
228				              "clk_ext1", "clk_ext2",
229				              "clk_ext3", "clk_ext4";
230			};
231
232			wdog1: watchdog@30280000 {
233				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
234				reg = <0x30280000 0x10000>;
235				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
236				clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
237				status = "disabled";
238			};
239
240			wdog2: watchdog@30290000 {
241				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
242				reg = <0x30290000 0x10000>;
243				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
244				clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
245				status = "disabled";
246			};
247
248			wdog3: watchdog@302a0000 {
249				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
250				reg = <0x302a0000 0x10000>;
251				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
252				clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
253				status = "disabled";
254			};
255		};
256
257		bus@30400000 { /* AIPS2 */
258			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
259			#address-cells = <1>;
260			#size-cells = <1>;
261			ranges = <0x30400000 0x30400000 0x400000>;
262		};
263
264		bus@30800000 { /* AIPS3 */
265			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
266			#address-cells = <1>;
267			#size-cells = <1>;
268			ranges = <0x30800000 0x30800000 0x400000>;
269
270			uart1: serial@30860000 {
271				compatible = "fsl,imx8mq-uart",
272				             "fsl,imx6q-uart";
273				reg = <0x30860000 0x10000>;
274				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
275				clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
276				         <&clk IMX8MQ_CLK_UART1_ROOT>;
277				clock-names = "ipg", "per";
278				status = "disabled";
279			};
280
281			uart3: serial@30880000 {
282				compatible = "fsl,imx8mq-uart",
283				             "fsl,imx6q-uart";
284				reg = <0x30880000 0x10000>;
285				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
286				clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
287				         <&clk IMX8MQ_CLK_UART3_ROOT>;
288				clock-names = "ipg", "per";
289				status = "disabled";
290			};
291
292			uart2: serial@30890000 {
293				compatible = "fsl,imx8mq-uart",
294				             "fsl,imx6q-uart";
295				reg = <0x30890000 0x10000>;
296				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
297				clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
298				         <&clk IMX8MQ_CLK_UART2_ROOT>;
299				clock-names = "ipg", "per";
300				status = "disabled";
301			};
302
303			i2c1: i2c@30a20000 {
304				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
305				reg = <0x30a20000 0x10000>;
306				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
307				clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
308				#address-cells = <1>;
309				#size-cells = <0>;
310				status = "disabled";
311			};
312
313			i2c2: i2c@30a30000 {
314				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
315				reg = <0x30a30000 0x10000>;
316				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
317				clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
318				#address-cells = <1>;
319				#size-cells = <0>;
320				status = "disabled";
321			};
322
323			i2c3: i2c@30a40000 {
324				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
325				reg = <0x30a40000 0x10000>;
326				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
327				clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
328				#address-cells = <1>;
329				#size-cells = <0>;
330				status = "disabled";
331			};
332
333			i2c4: i2c@30a50000 {
334				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
335				reg = <0x30a50000 0x10000>;
336				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
337				clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
338				#address-cells = <1>;
339				#size-cells = <0>;
340				status = "disabled";
341			};
342
343			uart4: serial@30a60000 {
344				compatible = "fsl,imx8mq-uart",
345				             "fsl,imx6q-uart";
346				reg = <0x30a60000 0x10000>;
347				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
348				clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
349				         <&clk IMX8MQ_CLK_UART4_ROOT>;
350				clock-names = "ipg", "per";
351				status = "disabled";
352			};
353
354			usdhc1: mmc@30b40000 {
355				compatible = "fsl,imx8mq-usdhc",
356				             "fsl,imx7d-usdhc";
357				reg = <0x30b40000 0x10000>;
358				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
359				clocks = <&clk IMX8MQ_CLK_DUMMY>,
360				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
361				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
362				clock-names = "ipg", "ahb", "per";
363				fsl,tuning-start-tap = <20>;
364				fsl,tuning-step = <2>;
365				bus-width = <4>;
366				status = "disabled";
367			};
368
369			usdhc2: mmc@30b50000 {
370				compatible = "fsl,imx8mq-usdhc",
371				             "fsl,imx7d-usdhc";
372				reg = <0x30b50000 0x10000>;
373				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
374				clocks = <&clk IMX8MQ_CLK_DUMMY>,
375				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
376				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
377				clock-names = "ipg", "ahb", "per";
378				fsl,tuning-start-tap = <20>;
379				fsl,tuning-step = <2>;
380				bus-width = <4>;
381				status = "disabled";
382			};
383
384			fec1: ethernet@30be0000 {
385				compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
386				reg = <0x30be0000 0x10000>;
387				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
388				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
389				             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
390				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
391				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
392				         <&clk IMX8MQ_CLK_ENET_TIMER>,
393				         <&clk IMX8MQ_CLK_ENET_REF>,
394				         <&clk IMX8MQ_CLK_ENET_PHY_REF>;
395				clock-names = "ipg", "ahb", "ptp",
396				              "enet_clk_ref", "enet_out";
397				fsl,num-tx-queues = <3>;
398				fsl,num-rx-queues = <3>;
399				status = "disabled";
400			};
401		};
402
403		gic: interrupt-controller@38800000 {
404			compatible = "arm,gic-v3";
405			reg = <0x38800000 0x10000>,	/* GIC Dist */
406			      <0x38880000 0xc0000>,	/* GICR */
407			      <0x31000000 0x2000>,	/* GICC */
408			      <0x31010000 0x2000>,	/* GICV */
409			      <0x31020000 0x2000>;	/* GICH */
410			#interrupt-cells = <3>;
411			interrupt-controller;
412			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
413			interrupt-parent = <&gic>;
414		};
415	};
416};
417