1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7#include <dt-bindings/clock/imx8mq-clock.h> 8#include <dt-bindings/power/imx8mq-power.h> 9#include <dt-bindings/reset/imx8mq-reset.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "dt-bindings/input/input.h" 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include "imx8mq-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gpc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 serial0 = &uart1; 33 serial1 = &uart2; 34 serial2 = &uart3; 35 serial3 = &uart4; 36 spi0 = &ecspi1; 37 spi1 = &ecspi2; 38 spi2 = &ecspi3; 39 }; 40 41 ckil: clock-ckil { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <32768>; 45 clock-output-names = "ckil"; 46 }; 47 48 osc_25m: clock-osc-25m { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <25000000>; 52 clock-output-names = "osc_25m"; 53 }; 54 55 osc_27m: clock-osc-27m { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <27000000>; 59 clock-output-names = "osc_27m"; 60 }; 61 62 clk_ext1: clock-ext1 { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <133000000>; 66 clock-output-names = "clk_ext1"; 67 }; 68 69 clk_ext2: clock-ext2 { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <133000000>; 73 clock-output-names = "clk_ext2"; 74 }; 75 76 clk_ext3: clock-ext3 { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <133000000>; 80 clock-output-names = "clk_ext3"; 81 }; 82 83 clk_ext4: clock-ext4 { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency= <133000000>; 87 clock-output-names = "clk_ext4"; 88 }; 89 90 cpus { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 94 A53_0: cpu@0 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x0>; 98 clock-latency = <61036>; /* two CLK32 periods */ 99 clocks = <&clk IMX8MQ_CLK_ARM>; 100 enable-method = "psci"; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 nvmem-cells = <&cpu_speed_grade>; 105 nvmem-cell-names = "speed_grade"; 106 }; 107 108 A53_1: cpu@1 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x1>; 112 clock-latency = <61036>; /* two CLK32 periods */ 113 clocks = <&clk IMX8MQ_CLK_ARM>; 114 enable-method = "psci"; 115 next-level-cache = <&A53_L2>; 116 operating-points-v2 = <&a53_opp_table>; 117 #cooling-cells = <2>; 118 }; 119 120 A53_2: cpu@2 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x2>; 124 clock-latency = <61036>; /* two CLK32 periods */ 125 clocks = <&clk IMX8MQ_CLK_ARM>; 126 enable-method = "psci"; 127 next-level-cache = <&A53_L2>; 128 operating-points-v2 = <&a53_opp_table>; 129 #cooling-cells = <2>; 130 }; 131 132 A53_3: cpu@3 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a53"; 135 reg = <0x3>; 136 clock-latency = <61036>; /* two CLK32 periods */ 137 clocks = <&clk IMX8MQ_CLK_ARM>; 138 enable-method = "psci"; 139 next-level-cache = <&A53_L2>; 140 operating-points-v2 = <&a53_opp_table>; 141 #cooling-cells = <2>; 142 }; 143 144 A53_L2: l2-cache0 { 145 compatible = "cache"; 146 }; 147 }; 148 149 a53_opp_table: opp-table { 150 compatible = "operating-points-v2"; 151 opp-shared; 152 153 opp-800000000 { 154 opp-hz = /bits/ 64 <800000000>; 155 opp-microvolt = <900000>; 156 /* Industrial only */ 157 opp-supported-hw = <0xf>, <0x4>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 162 opp-1000000000 { 163 opp-hz = /bits/ 64 <1000000000>; 164 opp-microvolt = <900000>; 165 /* Consumer only */ 166 opp-supported-hw = <0xe>, <0x3>; 167 clock-latency-ns = <150000>; 168 opp-suspend; 169 }; 170 171 opp-1300000000 { 172 opp-hz = /bits/ 64 <1300000000>; 173 opp-microvolt = <1000000>; 174 opp-supported-hw = <0xc>, <0x4>; 175 clock-latency-ns = <150000>; 176 opp-suspend; 177 }; 178 179 opp-1500000000 { 180 opp-hz = /bits/ 64 <1500000000>; 181 opp-microvolt = <1000000>; 182 opp-supported-hw = <0x8>, <0x3>; 183 clock-latency-ns = <150000>; 184 opp-suspend; 185 }; 186 }; 187 188 pmu { 189 compatible = "arm,cortex-a53-pmu"; 190 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 191 interrupt-parent = <&gic>; 192 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; 193 }; 194 195 psci { 196 compatible = "arm,psci-1.0"; 197 method = "smc"; 198 }; 199 200 thermal-zones { 201 cpu-thermal { 202 polling-delay-passive = <250>; 203 polling-delay = <2000>; 204 thermal-sensors = <&tmu 0>; 205 206 trips { 207 cpu_alert: cpu-alert { 208 temperature = <80000>; 209 hysteresis = <2000>; 210 type = "passive"; 211 }; 212 213 cpu-crit { 214 temperature = <90000>; 215 hysteresis = <2000>; 216 type = "critical"; 217 }; 218 }; 219 220 cooling-maps { 221 map0 { 222 trip = <&cpu_alert>; 223 cooling-device = 224 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 225 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 226 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 227 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 228 }; 229 }; 230 }; 231 232 gpu-thermal { 233 polling-delay-passive = <250>; 234 polling-delay = <2000>; 235 thermal-sensors = <&tmu 1>; 236 237 trips { 238 gpu_alert: gpu-alert { 239 temperature = <80000>; 240 hysteresis = <2000>; 241 type = "passive"; 242 }; 243 244 gpu-crit { 245 temperature = <90000>; 246 hysteresis = <2000>; 247 type = "critical"; 248 }; 249 }; 250 251 cooling-maps { 252 map0 { 253 trip = <&gpu_alert>; 254 cooling-device = 255 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 256 }; 257 }; 258 }; 259 260 vpu-thermal { 261 polling-delay-passive = <250>; 262 polling-delay = <2000>; 263 thermal-sensors = <&tmu 2>; 264 265 trips { 266 vpu-crit { 267 temperature = <90000>; 268 hysteresis = <2000>; 269 type = "critical"; 270 }; 271 }; 272 }; 273 }; 274 275 timer { 276 compatible = "arm,armv8-timer"; 277 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 278 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 279 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 280 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 281 interrupt-parent = <&gic>; 282 arm,no-tick-in-suspend; 283 }; 284 285 soc@0 { 286 compatible = "simple-bus"; 287 #address-cells = <1>; 288 #size-cells = <1>; 289 ranges = <0x0 0x0 0x0 0x3e000000>; 290 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 291 292 bus@30000000 { /* AIPS1 */ 293 compatible = "simple-bus"; 294 #address-cells = <1>; 295 #size-cells = <1>; 296 ranges = <0x30000000 0x30000000 0x400000>; 297 298 sai1: sai@30010000 { 299 #sound-dai-cells = <0>; 300 compatible = "fsl,imx8mq-sai"; 301 reg = <0x30010000 0x10000>; 302 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, 304 <&clk IMX8MQ_CLK_SAI1_ROOT>, 305 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 306 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 307 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; 308 dma-names = "rx", "tx"; 309 status = "disabled"; 310 }; 311 312 sai6: sai@30030000 { 313 #sound-dai-cells = <0>; 314 compatible = "fsl,imx8mq-sai"; 315 reg = <0x30030000 0x10000>; 316 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, 318 <&clk IMX8MQ_CLK_SAI6_ROOT>, 319 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 320 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 321 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; 322 dma-names = "rx", "tx"; 323 status = "disabled"; 324 }; 325 326 sai5: sai@30040000 { 327 #sound-dai-cells = <0>; 328 compatible = "fsl,imx8mq-sai"; 329 reg = <0x30040000 0x10000>; 330 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, 332 <&clk IMX8MQ_CLK_SAI5_ROOT>, 333 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 334 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 335 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; 336 dma-names = "rx", "tx"; 337 status = "disabled"; 338 }; 339 340 sai4: sai@30050000 { 341 #sound-dai-cells = <0>; 342 compatible = "fsl,imx8mq-sai"; 343 reg = <0x30050000 0x10000>; 344 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, 346 <&clk IMX8MQ_CLK_SAI4_ROOT>, 347 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 348 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 349 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 }; 353 354 gpio1: gpio@30200000 { 355 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 356 reg = <0x30200000 0x10000>; 357 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; 360 gpio-controller; 361 #gpio-cells = <2>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 gpio-ranges = <&iomuxc 0 10 30>; 365 }; 366 367 gpio2: gpio@30210000 { 368 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 369 reg = <0x30210000 0x10000>; 370 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 gpio-ranges = <&iomuxc 0 40 21>; 378 }; 379 380 gpio3: gpio@30220000 { 381 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 382 reg = <0x30220000 0x10000>; 383 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; 386 gpio-controller; 387 #gpio-cells = <2>; 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 gpio-ranges = <&iomuxc 0 61 26>; 391 }; 392 393 gpio4: gpio@30230000 { 394 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 395 reg = <0x30230000 0x10000>; 396 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; 399 gpio-controller; 400 #gpio-cells = <2>; 401 interrupt-controller; 402 #interrupt-cells = <2>; 403 gpio-ranges = <&iomuxc 0 87 32>; 404 }; 405 406 gpio5: gpio@30240000 { 407 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 408 reg = <0x30240000 0x10000>; 409 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; 412 gpio-controller; 413 #gpio-cells = <2>; 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 gpio-ranges = <&iomuxc 0 119 30>; 417 }; 418 419 tmu: tmu@30260000 { 420 compatible = "fsl,imx8mq-tmu"; 421 reg = <0x30260000 0x10000>; 422 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; 424 little-endian; 425 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 426 fsl,tmu-calibration = <0x00000000 0x00000023 427 0x00000001 0x00000029 428 0x00000002 0x0000002f 429 0x00000003 0x00000035 430 0x00000004 0x0000003d 431 0x00000005 0x00000043 432 0x00000006 0x0000004b 433 0x00000007 0x00000051 434 0x00000008 0x00000057 435 0x00000009 0x0000005f 436 0x0000000a 0x00000067 437 0x0000000b 0x0000006f 438 439 0x00010000 0x0000001b 440 0x00010001 0x00000023 441 0x00010002 0x0000002b 442 0x00010003 0x00000033 443 0x00010004 0x0000003b 444 0x00010005 0x00000043 445 0x00010006 0x0000004b 446 0x00010007 0x00000055 447 0x00010008 0x0000005d 448 0x00010009 0x00000067 449 0x0001000a 0x00000070 450 451 0x00020000 0x00000017 452 0x00020001 0x00000023 453 0x00020002 0x0000002d 454 0x00020003 0x00000037 455 0x00020004 0x00000041 456 0x00020005 0x0000004b 457 0x00020006 0x00000057 458 0x00020007 0x00000063 459 0x00020008 0x0000006f 460 461 0x00030000 0x00000015 462 0x00030001 0x00000021 463 0x00030002 0x0000002d 464 0x00030003 0x00000039 465 0x00030004 0x00000045 466 0x00030005 0x00000053 467 0x00030006 0x0000005f 468 0x00030007 0x00000071>; 469 #thermal-sensor-cells = <1>; 470 }; 471 472 wdog1: watchdog@30280000 { 473 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 474 reg = <0x30280000 0x10000>; 475 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; 477 status = "disabled"; 478 }; 479 480 wdog2: watchdog@30290000 { 481 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 482 reg = <0x30290000 0x10000>; 483 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; 485 status = "disabled"; 486 }; 487 488 wdog3: watchdog@302a0000 { 489 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 490 reg = <0x302a0000 0x10000>; 491 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; 493 status = "disabled"; 494 }; 495 496 sdma2: sdma@302c0000 { 497 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 498 reg = <0x302c0000 0x10000>; 499 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, 501 <&clk IMX8MQ_CLK_SDMA2_ROOT>; 502 clock-names = "ipg", "ahb"; 503 #dma-cells = <3>; 504 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 505 }; 506 507 lcdif: lcd-controller@30320000 { 508 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; 509 reg = <0x30320000 0x10000>; 510 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 512 clock-names = "pix"; 513 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 514 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 515 <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 516 <&clk IMX8MQ_VIDEO_PLL1>; 517 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 518 <&clk IMX8MQ_VIDEO_PLL1>, 519 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 520 assigned-clock-rates = <0>, <0>, <0>, <594000000>; 521 status = "disabled"; 522 }; 523 524 iomuxc: iomuxc@30330000 { 525 compatible = "fsl,imx8mq-iomuxc"; 526 reg = <0x30330000 0x10000>; 527 }; 528 529 iomuxc_gpr: syscon@30340000 { 530 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", 531 "syscon", "simple-mfd"; 532 reg = <0x30340000 0x10000>; 533 534 mux: mux-controller { 535 compatible = "mmio-mux"; 536 #mux-control-cells = <1>; 537 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ 538 }; 539 }; 540 541 ocotp: ocotp-ctrl@30350000 { 542 compatible = "fsl,imx8mq-ocotp", "syscon"; 543 reg = <0x30350000 0x10000>; 544 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 545 #address-cells = <1>; 546 #size-cells = <1>; 547 548 cpu_speed_grade: speed-grade@10 { 549 reg = <0x10 4>; 550 }; 551 }; 552 553 anatop: syscon@30360000 { 554 compatible = "fsl,imx8mq-anatop", "syscon"; 555 reg = <0x30360000 0x10000>; 556 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 557 }; 558 559 snvs: snvs@30370000 { 560 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 561 reg = <0x30370000 0x10000>; 562 563 snvs_rtc: snvs-rtc-lp{ 564 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 565 regmap =<&snvs>; 566 offset = <0x34>; 567 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 570 clock-names = "snvs-rtc"; 571 }; 572 573 snvs_pwrkey: snvs-powerkey { 574 compatible = "fsl,sec-v4.0-pwrkey"; 575 regmap = <&snvs>; 576 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 577 linux,keycode = <KEY_POWER>; 578 wakeup-source; 579 status = "disabled"; 580 }; 581 }; 582 583 clk: clock-controller@30380000 { 584 compatible = "fsl,imx8mq-ccm"; 585 reg = <0x30380000 0x10000>; 586 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 588 #clock-cells = <1>; 589 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, 590 <&clk_ext1>, <&clk_ext2>, 591 <&clk_ext3>, <&clk_ext4>; 592 clock-names = "ckil", "osc_25m", "osc_27m", 593 "clk_ext1", "clk_ext2", 594 "clk_ext3", "clk_ext4"; 595 assigned-clocks = <&clk IMX8MQ_CLK_NOC>; 596 assigned-clock-rates = <800000000>; 597 }; 598 599 src: reset-controller@30390000 { 600 compatible = "fsl,imx8mq-src", "syscon"; 601 reg = <0x30390000 0x10000>; 602 #reset-cells = <1>; 603 }; 604 605 gpc: gpc@303a0000 { 606 compatible = "fsl,imx8mq-gpc"; 607 reg = <0x303a0000 0x10000>; 608 interrupt-parent = <&gic>; 609 interrupt-controller; 610 #interrupt-cells = <3>; 611 612 pgc { 613 #address-cells = <1>; 614 #size-cells = <0>; 615 616 pgc_mipi: power-domain@0 { 617 #power-domain-cells = <0>; 618 reg = <IMX8M_POWER_DOMAIN_MIPI>; 619 }; 620 621 /* 622 * As per comment in ATF source code: 623 * 624 * PCIE1 and PCIE2 share the 625 * same reset signal, if we 626 * power down PCIE2, PCIE1 627 * will be held in reset too. 628 * 629 * So instead of creating two 630 * separate power domains for 631 * PCIE1 and PCIE2 we create a 632 * link between both and use 633 * it as a shared PCIE power 634 * domain. 635 */ 636 pgc_pcie: power-domain@1 { 637 #power-domain-cells = <0>; 638 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 639 power-domains = <&pgc_pcie2>; 640 }; 641 642 pgc_otg1: power-domain@2 { 643 #power-domain-cells = <0>; 644 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; 645 }; 646 647 pgc_otg2: power-domain@3 { 648 #power-domain-cells = <0>; 649 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; 650 }; 651 652 pgc_ddr1: power-domain@4 { 653 #power-domain-cells = <0>; 654 reg = <IMX8M_POWER_DOMAIN_DDR1>; 655 }; 656 657 pgc_gpu: power-domain@5 { 658 #power-domain-cells = <0>; 659 reg = <IMX8M_POWER_DOMAIN_GPU>; 660 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 661 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 662 <&clk IMX8MQ_CLK_GPU_AXI>, 663 <&clk IMX8MQ_CLK_GPU_AHB>; 664 }; 665 666 pgc_vpu: power-domain@6 { 667 #power-domain-cells = <0>; 668 reg = <IMX8M_POWER_DOMAIN_VPU>; 669 }; 670 671 pgc_disp: power-domain@7 { 672 #power-domain-cells = <0>; 673 reg = <IMX8M_POWER_DOMAIN_DISP>; 674 }; 675 676 pgc_mipi_csi1: power-domain@8 { 677 #power-domain-cells = <0>; 678 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; 679 }; 680 681 pgc_mipi_csi2: power-domain@9 { 682 #power-domain-cells = <0>; 683 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; 684 }; 685 686 pgc_pcie2: power-domain@a { 687 #power-domain-cells = <0>; 688 reg = <IMX8M_POWER_DOMAIN_PCIE2>; 689 }; 690 }; 691 }; 692 }; 693 694 bus@30400000 { /* AIPS2 */ 695 compatible = "simple-bus"; 696 #address-cells = <1>; 697 #size-cells = <1>; 698 ranges = <0x30400000 0x30400000 0x400000>; 699 700 pwm1: pwm@30660000 { 701 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 702 reg = <0x30660000 0x10000>; 703 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, 705 <&clk IMX8MQ_CLK_PWM1_ROOT>; 706 clock-names = "ipg", "per"; 707 #pwm-cells = <2>; 708 status = "disabled"; 709 }; 710 711 pwm2: pwm@30670000 { 712 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 713 reg = <0x30670000 0x10000>; 714 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, 716 <&clk IMX8MQ_CLK_PWM2_ROOT>; 717 clock-names = "ipg", "per"; 718 #pwm-cells = <2>; 719 status = "disabled"; 720 }; 721 722 pwm3: pwm@30680000 { 723 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 724 reg = <0x30680000 0x10000>; 725 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, 727 <&clk IMX8MQ_CLK_PWM3_ROOT>; 728 clock-names = "ipg", "per"; 729 #pwm-cells = <2>; 730 status = "disabled"; 731 }; 732 733 pwm4: pwm@30690000 { 734 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 735 reg = <0x30690000 0x10000>; 736 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, 738 <&clk IMX8MQ_CLK_PWM4_ROOT>; 739 clock-names = "ipg", "per"; 740 #pwm-cells = <2>; 741 status = "disabled"; 742 }; 743 744 system_counter: timer@306a0000 { 745 compatible = "nxp,sysctr-timer"; 746 reg = <0x306a0000 0x20000>; 747 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&osc_25m>; 749 clock-names = "per"; 750 }; 751 }; 752 753 bus@30800000 { /* AIPS3 */ 754 compatible = "simple-bus"; 755 #address-cells = <1>; 756 #size-cells = <1>; 757 ranges = <0x30800000 0x30800000 0x400000>, 758 <0x08000000 0x08000000 0x10000000>; 759 760 ecspi1: spi@30820000 { 761 #address-cells = <1>; 762 #size-cells = <0>; 763 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 764 reg = <0x30820000 0x10000>; 765 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, 767 <&clk IMX8MQ_CLK_ECSPI1_ROOT>; 768 clock-names = "ipg", "per"; 769 status = "disabled"; 770 }; 771 772 ecspi2: spi@30830000 { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 776 reg = <0x30830000 0x10000>; 777 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, 779 <&clk IMX8MQ_CLK_ECSPI2_ROOT>; 780 clock-names = "ipg", "per"; 781 status = "disabled"; 782 }; 783 784 ecspi3: spi@30840000 { 785 #address-cells = <1>; 786 #size-cells = <0>; 787 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 788 reg = <0x30840000 0x10000>; 789 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, 791 <&clk IMX8MQ_CLK_ECSPI3_ROOT>; 792 clock-names = "ipg", "per"; 793 status = "disabled"; 794 }; 795 796 uart1: serial@30860000 { 797 compatible = "fsl,imx8mq-uart", 798 "fsl,imx6q-uart"; 799 reg = <0x30860000 0x10000>; 800 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, 802 <&clk IMX8MQ_CLK_UART1_ROOT>; 803 clock-names = "ipg", "per"; 804 status = "disabled"; 805 }; 806 807 uart3: serial@30880000 { 808 compatible = "fsl,imx8mq-uart", 809 "fsl,imx6q-uart"; 810 reg = <0x30880000 0x10000>; 811 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, 813 <&clk IMX8MQ_CLK_UART3_ROOT>; 814 clock-names = "ipg", "per"; 815 status = "disabled"; 816 }; 817 818 uart2: serial@30890000 { 819 compatible = "fsl,imx8mq-uart", 820 "fsl,imx6q-uart"; 821 reg = <0x30890000 0x10000>; 822 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, 824 <&clk IMX8MQ_CLK_UART2_ROOT>; 825 clock-names = "ipg", "per"; 826 status = "disabled"; 827 }; 828 829 sai2: sai@308b0000 { 830 #sound-dai-cells = <0>; 831 compatible = "fsl,imx8mq-sai"; 832 reg = <0x308b0000 0x10000>; 833 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, 835 <&clk IMX8MQ_CLK_SAI2_ROOT>, 836 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 837 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 838 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; 839 dma-names = "rx", "tx"; 840 status = "disabled"; 841 }; 842 843 sai3: sai@308c0000 { 844 #sound-dai-cells = <0>; 845 compatible = "fsl,imx8mq-sai"; 846 reg = <0x308c0000 0x10000>; 847 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, 849 <&clk IMX8MQ_CLK_SAI3_ROOT>, 850 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 851 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 852 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; 853 dma-names = "rx", "tx"; 854 status = "disabled"; 855 }; 856 857 crypto: crypto@30900000 { 858 compatible = "fsl,sec-v4.0"; 859 #address-cells = <1>; 860 #size-cells = <1>; 861 reg = <0x30900000 0x40000>; 862 ranges = <0 0x30900000 0x40000>; 863 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&clk IMX8MQ_CLK_AHB>, 865 <&clk IMX8MQ_CLK_IPG_ROOT>; 866 clock-names = "aclk", "ipg"; 867 868 sec_jr0: jr@1000 { 869 compatible = "fsl,sec-v4.0-job-ring"; 870 reg = <0x1000 0x1000>; 871 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 872 }; 873 874 sec_jr1: jr@2000 { 875 compatible = "fsl,sec-v4.0-job-ring"; 876 reg = <0x2000 0x1000>; 877 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 878 }; 879 880 sec_jr2: jr@3000 { 881 compatible = "fsl,sec-v4.0-job-ring"; 882 reg = <0x3000 0x1000>; 883 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 884 }; 885 }; 886 887 dphy: dphy@30a00300 { 888 compatible = "fsl,imx8mq-mipi-dphy"; 889 reg = <0x30a00300 0x100>; 890 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 891 clock-names = "phy_ref"; 892 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 893 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>; 894 assigned-clock-rates = <24000000>; 895 #phy-cells = <0>; 896 power-domains = <&pgc_mipi>; 897 status = "disabled"; 898 }; 899 900 i2c1: i2c@30a20000 { 901 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 902 reg = <0x30a20000 0x10000>; 903 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 status = "disabled"; 908 }; 909 910 i2c2: i2c@30a30000 { 911 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 912 reg = <0x30a30000 0x10000>; 913 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 status = "disabled"; 918 }; 919 920 i2c3: i2c@30a40000 { 921 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 922 reg = <0x30a40000 0x10000>; 923 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; 925 #address-cells = <1>; 926 #size-cells = <0>; 927 status = "disabled"; 928 }; 929 930 i2c4: i2c@30a50000 { 931 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 932 reg = <0x30a50000 0x10000>; 933 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 status = "disabled"; 938 }; 939 940 uart4: serial@30a60000 { 941 compatible = "fsl,imx8mq-uart", 942 "fsl,imx6q-uart"; 943 reg = <0x30a60000 0x10000>; 944 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, 946 <&clk IMX8MQ_CLK_UART4_ROOT>; 947 clock-names = "ipg", "per"; 948 status = "disabled"; 949 }; 950 951 usdhc1: mmc@30b40000 { 952 compatible = "fsl,imx8mq-usdhc", 953 "fsl,imx7d-usdhc"; 954 reg = <0x30b40000 0x10000>; 955 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 957 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 958 <&clk IMX8MQ_CLK_USDHC1_ROOT>; 959 clock-names = "ipg", "ahb", "per"; 960 fsl,tuning-start-tap = <20>; 961 fsl,tuning-step = <2>; 962 bus-width = <4>; 963 status = "disabled"; 964 }; 965 966 usdhc2: mmc@30b50000 { 967 compatible = "fsl,imx8mq-usdhc", 968 "fsl,imx7d-usdhc"; 969 reg = <0x30b50000 0x10000>; 970 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 972 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 973 <&clk IMX8MQ_CLK_USDHC2_ROOT>; 974 clock-names = "ipg", "ahb", "per"; 975 fsl,tuning-start-tap = <20>; 976 fsl,tuning-step = <2>; 977 bus-width = <4>; 978 status = "disabled"; 979 }; 980 981 qspi0: spi@30bb0000 { 982 #address-cells = <1>; 983 #size-cells = <0>; 984 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; 985 reg = <0x30bb0000 0x10000>, 986 <0x08000000 0x10000000>; 987 reg-names = "QuadSPI", "QuadSPI-memory"; 988 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, 990 <&clk IMX8MQ_CLK_QSPI_ROOT>; 991 clock-names = "qspi_en", "qspi"; 992 status = "disabled"; 993 }; 994 995 sdma1: sdma@30bd0000 { 996 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 997 reg = <0x30bd0000 0x10000>; 998 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, 1000 <&clk IMX8MQ_CLK_AHB>; 1001 clock-names = "ipg", "ahb"; 1002 #dma-cells = <3>; 1003 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1004 }; 1005 1006 fec1: ethernet@30be0000 { 1007 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1008 reg = <0x30be0000 0x10000>; 1009 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, 1013 <&clk IMX8MQ_CLK_ENET1_ROOT>, 1014 <&clk IMX8MQ_CLK_ENET_TIMER>, 1015 <&clk IMX8MQ_CLK_ENET_REF>, 1016 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1017 clock-names = "ipg", "ahb", "ptp", 1018 "enet_clk_ref", "enet_out"; 1019 fsl,num-tx-queues = <3>; 1020 fsl,num-rx-queues = <3>; 1021 status = "disabled"; 1022 }; 1023 }; 1024 1025 bus@32c00000 { /* AIPS4 */ 1026 compatible = "simple-bus"; 1027 #address-cells = <1>; 1028 #size-cells = <1>; 1029 ranges = <0x32c00000 0x32c00000 0x400000>; 1030 1031 irqsteer: interrupt-controller@32e2d000 { 1032 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; 1033 reg = <0x32e2d000 0x1000>; 1034 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 1036 clock-names = "ipg"; 1037 fsl,channel = <0>; 1038 fsl,num-irqs = <64>; 1039 interrupt-controller; 1040 #interrupt-cells = <1>; 1041 }; 1042 }; 1043 1044 gpu: gpu@38000000 { 1045 compatible = "vivante,gc"; 1046 reg = <0x38000000 0x40000>; 1047 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 1049 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 1050 <&clk IMX8MQ_CLK_GPU_AXI>, 1051 <&clk IMX8MQ_CLK_GPU_AHB>; 1052 clock-names = "core", "shader", "bus", "reg"; 1053 #cooling-cells = <2>; 1054 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, 1055 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, 1056 <&clk IMX8MQ_CLK_GPU_AXI>, 1057 <&clk IMX8MQ_CLK_GPU_AHB>, 1058 <&clk IMX8MQ_GPU_PLL_BYPASS>; 1059 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, 1060 <&clk IMX8MQ_GPU_PLL_OUT>, 1061 <&clk IMX8MQ_GPU_PLL_OUT>, 1062 <&clk IMX8MQ_GPU_PLL_OUT>, 1063 <&clk IMX8MQ_GPU_PLL>; 1064 assigned-clock-rates = <800000000>, <800000000>, 1065 <800000000>, <800000000>, <0>; 1066 power-domains = <&pgc_gpu>; 1067 }; 1068 1069 usb_dwc3_0: usb@38100000 { 1070 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1071 reg = <0x38100000 0x10000>; 1072 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, 1073 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1074 <&clk IMX8MQ_CLK_32K>; 1075 clock-names = "bus_early", "ref", "suspend"; 1076 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1077 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1078 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1079 <&clk IMX8MQ_SYS1_PLL_100M>; 1080 assigned-clock-rates = <500000000>, <100000000>; 1081 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1082 phys = <&usb3_phy0>, <&usb3_phy0>; 1083 phy-names = "usb2-phy", "usb3-phy"; 1084 power-domains = <&pgc_otg1>; 1085 usb3-resume-missing-cas; 1086 status = "disabled"; 1087 }; 1088 1089 usb3_phy0: usb-phy@381f0040 { 1090 compatible = "fsl,imx8mq-usb-phy"; 1091 reg = <0x381f0040 0x40>; 1092 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 1093 clock-names = "phy"; 1094 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1095 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1096 assigned-clock-rates = <100000000>; 1097 #phy-cells = <0>; 1098 status = "disabled"; 1099 }; 1100 1101 usb_dwc3_1: usb@38200000 { 1102 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1103 reg = <0x38200000 0x10000>; 1104 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, 1105 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1106 <&clk IMX8MQ_CLK_32K>; 1107 clock-names = "bus_early", "ref", "suspend"; 1108 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1109 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1110 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1111 <&clk IMX8MQ_SYS1_PLL_100M>; 1112 assigned-clock-rates = <500000000>, <100000000>; 1113 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1114 phys = <&usb3_phy1>, <&usb3_phy1>; 1115 phy-names = "usb2-phy", "usb3-phy"; 1116 power-domains = <&pgc_otg2>; 1117 usb3-resume-missing-cas; 1118 status = "disabled"; 1119 }; 1120 1121 usb3_phy1: usb-phy@382f0040 { 1122 compatible = "fsl,imx8mq-usb-phy"; 1123 reg = <0x382f0040 0x40>; 1124 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; 1125 clock-names = "phy"; 1126 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1127 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1128 assigned-clock-rates = <100000000>; 1129 #phy-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 pcie0: pcie@33800000 { 1134 compatible = "fsl,imx8mq-pcie"; 1135 reg = <0x33800000 0x400000>, 1136 <0x1ff00000 0x80000>; 1137 reg-names = "dbi", "config"; 1138 #address-cells = <3>; 1139 #size-cells = <2>; 1140 device_type = "pci"; 1141 bus-range = <0x00 0xff>; 1142 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ 1143 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1144 num-lanes = <1>; 1145 num-viewport = <4>; 1146 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1147 interrupt-names = "msi"; 1148 #interrupt-cells = <1>; 1149 interrupt-map-mask = <0 0 0 0x7>; 1150 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1151 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1152 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1153 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1154 fsl,max-link-speed = <2>; 1155 power-domains = <&pgc_pcie>; 1156 resets = <&src IMX8MQ_RESET_PCIEPHY>, 1157 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1158 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1159 reset-names = "pciephy", "apps", "turnoff"; 1160 status = "disabled"; 1161 }; 1162 1163 pcie1: pcie@33c00000 { 1164 compatible = "fsl,imx8mq-pcie"; 1165 reg = <0x33c00000 0x400000>, 1166 <0x27f00000 0x80000>; 1167 reg-names = "dbi", "config"; 1168 #address-cells = <3>; 1169 #size-cells = <2>; 1170 device_type = "pci"; 1171 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ 1172 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1173 num-lanes = <1>; 1174 num-viewport = <4>; 1175 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1176 interrupt-names = "msi"; 1177 #interrupt-cells = <1>; 1178 interrupt-map-mask = <0 0 0 0x7>; 1179 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1180 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1181 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1182 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1183 fsl,max-link-speed = <2>; 1184 power-domains = <&pgc_pcie>; 1185 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1186 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1187 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1188 reset-names = "pciephy", "apps", "turnoff"; 1189 status = "disabled"; 1190 }; 1191 1192 gic: interrupt-controller@38800000 { 1193 compatible = "arm,gic-v3"; 1194 reg = <0x38800000 0x10000>, /* GIC Dist */ 1195 <0x38880000 0xc0000>, /* GICR */ 1196 <0x31000000 0x2000>, /* GICC */ 1197 <0x31010000 0x2000>, /* GICV */ 1198 <0x31020000 0x2000>; /* GICH */ 1199 #interrupt-cells = <3>; 1200 interrupt-controller; 1201 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1202 interrupt-parent = <&gic>; 1203 }; 1204 1205 ddrc: memory-controller@3d400000 { 1206 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; 1207 reg = <0x3d400000 0x400000>; 1208 clock-names = "core", "pll", "alt", "apb"; 1209 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, 1210 <&clk IMX8MQ_DRAM_PLL_OUT>, 1211 <&clk IMX8MQ_CLK_DRAM_ALT>, 1212 <&clk IMX8MQ_CLK_DRAM_APB>; 1213 }; 1214 1215 ddr-pmu@3d800000 { 1216 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1217 reg = <0x3d800000 0x400000>; 1218 interrupt-parent = <&gic>; 1219 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1220 }; 1221 }; 1222}; 1223