1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <dt-bindings/clock/imx8mq-clock.h>
8#include <dt-bindings/power/imx8mq-power.h>
9#include <dt-bindings/reset/imx8mq-reset.h>
10#include <dt-bindings/gpio/gpio.h>
11#include "dt-bindings/input/input.h"
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/thermal/thermal.h>
14#include "imx8mq-pinfunc.h"
15
16/ {
17	interrupt-parent = <&gpc>;
18
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		ethernet0 = &fec1;
24		gpio0 = &gpio1;
25		gpio1 = &gpio2;
26		gpio2 = &gpio3;
27		gpio3 = &gpio4;
28		gpio4 = &gpio5;
29		i2c0 = &i2c1;
30		i2c1 = &i2c2;
31		i2c2 = &i2c3;
32		i2c3 = &i2c4;
33		mmc0 = &usdhc1;
34		mmc1 = &usdhc2;
35		serial0 = &uart1;
36		serial1 = &uart2;
37		serial2 = &uart3;
38		serial3 = &uart4;
39		spi0 = &ecspi1;
40		spi1 = &ecspi2;
41		spi2 = &ecspi3;
42	};
43
44	ckil: clock-ckil {
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		clock-frequency = <32768>;
48		clock-output-names = "ckil";
49	};
50
51	osc_25m: clock-osc-25m {
52		compatible = "fixed-clock";
53		#clock-cells = <0>;
54		clock-frequency = <25000000>;
55		clock-output-names = "osc_25m";
56	};
57
58	osc_27m: clock-osc-27m {
59		compatible = "fixed-clock";
60		#clock-cells = <0>;
61		clock-frequency = <27000000>;
62		clock-output-names = "osc_27m";
63	};
64
65	clk_ext1: clock-ext1 {
66		compatible = "fixed-clock";
67		#clock-cells = <0>;
68		clock-frequency = <133000000>;
69		clock-output-names = "clk_ext1";
70	};
71
72	clk_ext2: clock-ext2 {
73		compatible = "fixed-clock";
74		#clock-cells = <0>;
75		clock-frequency = <133000000>;
76		clock-output-names = "clk_ext2";
77	};
78
79	clk_ext3: clock-ext3 {
80		compatible = "fixed-clock";
81		#clock-cells = <0>;
82		clock-frequency = <133000000>;
83		clock-output-names = "clk_ext3";
84	};
85
86	clk_ext4: clock-ext4 {
87		compatible = "fixed-clock";
88		#clock-cells = <0>;
89		clock-frequency= <133000000>;
90		clock-output-names = "clk_ext4";
91	};
92
93	cpus {
94		#address-cells = <1>;
95		#size-cells = <0>;
96
97		A53_0: cpu@0 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a53";
100			reg = <0x0>;
101			clock-latency = <61036>; /* two CLK32 periods */
102			clocks = <&clk IMX8MQ_CLK_ARM>;
103			enable-method = "psci";
104			next-level-cache = <&A53_L2>;
105			operating-points-v2 = <&a53_opp_table>;
106			#cooling-cells = <2>;
107			nvmem-cells = <&cpu_speed_grade>;
108			nvmem-cell-names = "speed_grade";
109		};
110
111		A53_1: cpu@1 {
112			device_type = "cpu";
113			compatible = "arm,cortex-a53";
114			reg = <0x1>;
115			clock-latency = <61036>; /* two CLK32 periods */
116			clocks = <&clk IMX8MQ_CLK_ARM>;
117			enable-method = "psci";
118			next-level-cache = <&A53_L2>;
119			operating-points-v2 = <&a53_opp_table>;
120			#cooling-cells = <2>;
121		};
122
123		A53_2: cpu@2 {
124			device_type = "cpu";
125			compatible = "arm,cortex-a53";
126			reg = <0x2>;
127			clock-latency = <61036>; /* two CLK32 periods */
128			clocks = <&clk IMX8MQ_CLK_ARM>;
129			enable-method = "psci";
130			next-level-cache = <&A53_L2>;
131			operating-points-v2 = <&a53_opp_table>;
132			#cooling-cells = <2>;
133		};
134
135		A53_3: cpu@3 {
136			device_type = "cpu";
137			compatible = "arm,cortex-a53";
138			reg = <0x3>;
139			clock-latency = <61036>; /* two CLK32 periods */
140			clocks = <&clk IMX8MQ_CLK_ARM>;
141			enable-method = "psci";
142			next-level-cache = <&A53_L2>;
143			operating-points-v2 = <&a53_opp_table>;
144			#cooling-cells = <2>;
145		};
146
147		A53_L2: l2-cache0 {
148			compatible = "cache";
149		};
150	};
151
152	a53_opp_table: opp-table {
153		compatible = "operating-points-v2";
154		opp-shared;
155
156		opp-800000000 {
157			opp-hz = /bits/ 64 <800000000>;
158			opp-microvolt = <900000>;
159			/* Industrial only */
160			opp-supported-hw = <0xf>, <0x4>;
161			clock-latency-ns = <150000>;
162			opp-suspend;
163		};
164
165		opp-1000000000 {
166			opp-hz = /bits/ 64 <1000000000>;
167			opp-microvolt = <900000>;
168			/* Consumer only */
169			opp-supported-hw = <0xe>, <0x3>;
170			clock-latency-ns = <150000>;
171			opp-suspend;
172		};
173
174		opp-1300000000 {
175			opp-hz = /bits/ 64 <1300000000>;
176			opp-microvolt = <1000000>;
177			opp-supported-hw = <0xc>, <0x4>;
178			clock-latency-ns = <150000>;
179			opp-suspend;
180		};
181
182		opp-1500000000 {
183			opp-hz = /bits/ 64 <1500000000>;
184			opp-microvolt = <1000000>;
185			opp-supported-hw = <0x8>, <0x3>;
186			clock-latency-ns = <150000>;
187			opp-suspend;
188		};
189	};
190
191	pmu {
192		compatible = "arm,cortex-a53-pmu";
193		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
194		interrupt-parent = <&gic>;
195		interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
196	};
197
198	psci {
199		compatible = "arm,psci-1.0";
200		method = "smc";
201	};
202
203	thermal-zones {
204		cpu_thermal: cpu-thermal {
205			polling-delay-passive = <250>;
206			polling-delay = <2000>;
207			thermal-sensors = <&tmu 0>;
208
209			trips {
210				cpu_alert: cpu-alert {
211					temperature = <80000>;
212					hysteresis = <2000>;
213					type = "passive";
214				};
215
216				cpu-crit {
217					temperature = <90000>;
218					hysteresis = <2000>;
219					type = "critical";
220				};
221			};
222
223			cooling-maps {
224				map0 {
225					trip = <&cpu_alert>;
226					cooling-device =
227						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
228						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
229						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
230						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
231				};
232			};
233		};
234
235		gpu-thermal {
236			polling-delay-passive = <250>;
237			polling-delay = <2000>;
238			thermal-sensors = <&tmu 1>;
239
240			trips {
241				gpu_alert: gpu-alert {
242					temperature = <80000>;
243					hysteresis = <2000>;
244					type = "passive";
245				};
246
247				gpu-crit {
248					temperature = <90000>;
249					hysteresis = <2000>;
250					type = "critical";
251				};
252			};
253
254			cooling-maps {
255				map0 {
256					trip = <&gpu_alert>;
257					cooling-device =
258						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
259				};
260			};
261		};
262
263		vpu-thermal {
264			polling-delay-passive = <250>;
265			polling-delay = <2000>;
266			thermal-sensors = <&tmu 2>;
267
268			trips {
269				vpu-crit {
270					temperature = <90000>;
271					hysteresis = <2000>;
272					type = "critical";
273				};
274			};
275		};
276	};
277
278	timer {
279		compatible = "arm,armv8-timer";
280		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
281		             <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
282		             <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
283		             <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
284		interrupt-parent = <&gic>;
285		arm,no-tick-in-suspend;
286	};
287
288	soc@0 {
289		compatible = "simple-bus";
290		#address-cells = <1>;
291		#size-cells = <1>;
292		ranges = <0x0 0x0 0x0 0x3e000000>;
293		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
294
295		bus@30000000 { /* AIPS1 */
296			compatible = "fsl,aips-bus", "simple-bus";
297			reg = <0x30000000 0x400000>;
298			#address-cells = <1>;
299			#size-cells = <1>;
300			ranges = <0x30000000 0x30000000 0x400000>;
301
302			sai1: sai@30010000 {
303				#sound-dai-cells = <0>;
304				compatible = "fsl,imx8mq-sai";
305				reg = <0x30010000 0x10000>;
306				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
307				clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
308				         <&clk IMX8MQ_CLK_SAI1_ROOT>,
309				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
310				clock-names = "bus", "mclk1", "mclk2", "mclk3";
311				dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
312				dma-names = "rx", "tx";
313				status = "disabled";
314			};
315
316			sai6: sai@30030000 {
317				#sound-dai-cells = <0>;
318				compatible = "fsl,imx8mq-sai";
319				reg = <0x30030000 0x10000>;
320				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
321				clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
322				         <&clk IMX8MQ_CLK_SAI6_ROOT>,
323				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
324				clock-names = "bus", "mclk1", "mclk2", "mclk3";
325				dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
326				dma-names = "rx", "tx";
327				status = "disabled";
328			};
329
330			sai5: sai@30040000 {
331				#sound-dai-cells = <0>;
332				compatible = "fsl,imx8mq-sai";
333				reg = <0x30040000 0x10000>;
334				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
335				clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
336				         <&clk IMX8MQ_CLK_SAI5_ROOT>,
337				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
338				clock-names = "bus", "mclk1", "mclk2", "mclk3";
339				dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
340				dma-names = "rx", "tx";
341				status = "disabled";
342			};
343
344			sai4: sai@30050000 {
345				#sound-dai-cells = <0>;
346				compatible = "fsl,imx8mq-sai";
347				reg = <0x30050000 0x10000>;
348				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
349				clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
350				         <&clk IMX8MQ_CLK_SAI4_ROOT>,
351				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
352				clock-names = "bus", "mclk1", "mclk2", "mclk3";
353				dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
354				dma-names = "rx", "tx";
355				status = "disabled";
356			};
357
358			gpio1: gpio@30200000 {
359				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
360				reg = <0x30200000 0x10000>;
361				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
362				             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
363				clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
364				gpio-controller;
365				#gpio-cells = <2>;
366				interrupt-controller;
367				#interrupt-cells = <2>;
368				gpio-ranges = <&iomuxc 0 10 30>;
369			};
370
371			gpio2: gpio@30210000 {
372				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
373				reg = <0x30210000 0x10000>;
374				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
375				             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
376				clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
377				gpio-controller;
378				#gpio-cells = <2>;
379				interrupt-controller;
380				#interrupt-cells = <2>;
381				gpio-ranges = <&iomuxc 0 40 21>;
382			};
383
384			gpio3: gpio@30220000 {
385				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
386				reg = <0x30220000 0x10000>;
387				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
388				             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
389				clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
390				gpio-controller;
391				#gpio-cells = <2>;
392				interrupt-controller;
393				#interrupt-cells = <2>;
394				gpio-ranges = <&iomuxc 0 61 26>;
395			};
396
397			gpio4: gpio@30230000 {
398				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
399				reg = <0x30230000 0x10000>;
400				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
401				             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
402				clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
403				gpio-controller;
404				#gpio-cells = <2>;
405				interrupt-controller;
406				#interrupt-cells = <2>;
407				gpio-ranges = <&iomuxc 0 87 32>;
408			};
409
410			gpio5: gpio@30240000 {
411				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
412				reg = <0x30240000 0x10000>;
413				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
414				             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
415				clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
416				gpio-controller;
417				#gpio-cells = <2>;
418				interrupt-controller;
419				#interrupt-cells = <2>;
420				gpio-ranges = <&iomuxc 0 119 30>;
421			};
422
423			tmu: tmu@30260000 {
424				compatible = "fsl,imx8mq-tmu";
425				reg = <0x30260000 0x10000>;
426				interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
427				clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
428				little-endian;
429				fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
430				fsl,tmu-calibration = <0x00000000 0x00000023
431						       0x00000001 0x00000029
432						       0x00000002 0x0000002f
433						       0x00000003 0x00000035
434						       0x00000004 0x0000003d
435						       0x00000005 0x00000043
436						       0x00000006 0x0000004b
437						       0x00000007 0x00000051
438						       0x00000008 0x00000057
439						       0x00000009 0x0000005f
440						       0x0000000a 0x00000067
441						       0x0000000b 0x0000006f
442
443						       0x00010000 0x0000001b
444						       0x00010001 0x00000023
445						       0x00010002 0x0000002b
446						       0x00010003 0x00000033
447						       0x00010004 0x0000003b
448						       0x00010005 0x00000043
449						       0x00010006 0x0000004b
450						       0x00010007 0x00000055
451						       0x00010008 0x0000005d
452						       0x00010009 0x00000067
453						       0x0001000a 0x00000070
454
455						       0x00020000 0x00000017
456						       0x00020001 0x00000023
457						       0x00020002 0x0000002d
458						       0x00020003 0x00000037
459						       0x00020004 0x00000041
460						       0x00020005 0x0000004b
461						       0x00020006 0x00000057
462						       0x00020007 0x00000063
463						       0x00020008 0x0000006f
464
465						       0x00030000 0x00000015
466						       0x00030001 0x00000021
467						       0x00030002 0x0000002d
468						       0x00030003 0x00000039
469						       0x00030004 0x00000045
470						       0x00030005 0x00000053
471						       0x00030006 0x0000005f
472						       0x00030007 0x00000071>;
473				#thermal-sensor-cells =  <1>;
474			};
475
476			wdog1: watchdog@30280000 {
477				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
478				reg = <0x30280000 0x10000>;
479				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
480				clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
481				status = "disabled";
482			};
483
484			wdog2: watchdog@30290000 {
485				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
486				reg = <0x30290000 0x10000>;
487				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
488				clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
489				status = "disabled";
490			};
491
492			wdog3: watchdog@302a0000 {
493				compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
494				reg = <0x302a0000 0x10000>;
495				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
496				clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
497				status = "disabled";
498			};
499
500			sdma2: sdma@302c0000 {
501				compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
502				reg = <0x302c0000 0x10000>;
503				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
504				clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
505					 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
506				clock-names = "ipg", "ahb";
507				#dma-cells = <3>;
508				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
509			};
510
511			lcdif: lcd-controller@30320000 {
512				compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
513				reg = <0x30320000 0x10000>;
514				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
515				clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
516				clock-names = "pix";
517				assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
518						  <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
519						  <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
520						  <&clk IMX8MQ_VIDEO_PLL1>;
521				assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
522						  <&clk IMX8MQ_VIDEO_PLL1>,
523						  <&clk IMX8MQ_VIDEO_PLL1_OUT>;
524				assigned-clock-rates = <0>, <0>, <0>, <594000000>;
525				status = "disabled";
526			};
527
528			iomuxc: pinctrl@30330000 {
529				compatible = "fsl,imx8mq-iomuxc";
530				reg = <0x30330000 0x10000>;
531			};
532
533			iomuxc_gpr: syscon@30340000 {
534				compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
535					     "syscon", "simple-mfd";
536				reg = <0x30340000 0x10000>;
537
538				mux: mux-controller {
539					compatible = "mmio-mux";
540					#mux-control-cells = <1>;
541					mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
542				};
543			};
544
545			ocotp: efuse@30350000 {
546				compatible = "fsl,imx8mq-ocotp", "syscon";
547				reg = <0x30350000 0x10000>;
548				clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
549				#address-cells = <1>;
550				#size-cells = <1>;
551
552				cpu_speed_grade: speed-grade@10 {
553					reg = <0x10 4>;
554				};
555			};
556
557			anatop: syscon@30360000 {
558				compatible = "fsl,imx8mq-anatop", "syscon";
559				reg = <0x30360000 0x10000>;
560				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
561			};
562
563			snvs: snvs@30370000 {
564				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
565				reg = <0x30370000 0x10000>;
566
567				snvs_rtc: snvs-rtc-lp{
568					compatible = "fsl,sec-v4.0-mon-rtc-lp";
569					regmap =<&snvs>;
570					offset = <0x34>;
571					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
572						<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
573					clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
574					clock-names = "snvs-rtc";
575				};
576
577				snvs_pwrkey: snvs-powerkey {
578					compatible = "fsl,sec-v4.0-pwrkey";
579					regmap = <&snvs>;
580					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
581					clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
582					clock-names = "snvs-pwrkey";
583					linux,keycode = <KEY_POWER>;
584					wakeup-source;
585					status = "disabled";
586				};
587			};
588
589			clk: clock-controller@30380000 {
590				compatible = "fsl,imx8mq-ccm";
591				reg = <0x30380000 0x10000>;
592				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
593				             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
594				#clock-cells = <1>;
595				clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
596				         <&clk_ext1>, <&clk_ext2>,
597				         <&clk_ext3>, <&clk_ext4>;
598				clock-names = "ckil", "osc_25m", "osc_27m",
599				              "clk_ext1", "clk_ext2",
600				              "clk_ext3", "clk_ext4";
601				assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
602						  <&clk IMX8MQ_CLK_A53_CORE>,
603						  <&clk IMX8MQ_CLK_NOC>;
604				assigned-clock-rates = <0>, <0>,
605						       <800000000>;
606				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
607							 <&clk IMX8MQ_ARM_PLL_OUT>;
608			};
609
610			src: reset-controller@30390000 {
611				compatible = "fsl,imx8mq-src", "syscon";
612				reg = <0x30390000 0x10000>;
613				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
614				#reset-cells = <1>;
615			};
616
617			gpc: gpc@303a0000 {
618				compatible = "fsl,imx8mq-gpc";
619				reg = <0x303a0000 0x10000>;
620				interrupt-parent = <&gic>;
621				interrupt-controller;
622				#interrupt-cells = <3>;
623
624				pgc {
625					#address-cells = <1>;
626					#size-cells = <0>;
627
628					pgc_mipi: power-domain@0 {
629						#power-domain-cells = <0>;
630						reg = <IMX8M_POWER_DOMAIN_MIPI>;
631					};
632
633					/*
634					 * As per comment in ATF source code:
635					 *
636					 * PCIE1 and PCIE2 share the
637					 * same reset signal, if we
638					 * power down PCIE2, PCIE1
639					 * will be held in reset too.
640					 *
641					 * So instead of creating two
642					 * separate power domains for
643					 * PCIE1 and PCIE2 we create a
644					 * link between both and use
645					 * it as a shared PCIE power
646					 * domain.
647					 */
648					pgc_pcie: power-domain@1 {
649						#power-domain-cells = <0>;
650						reg = <IMX8M_POWER_DOMAIN_PCIE1>;
651						power-domains = <&pgc_pcie2>;
652					};
653
654					pgc_otg1: power-domain@2 {
655						#power-domain-cells = <0>;
656						reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
657					};
658
659					pgc_otg2: power-domain@3 {
660						#power-domain-cells = <0>;
661						reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
662					};
663
664					pgc_ddr1: power-domain@4 {
665						#power-domain-cells = <0>;
666						reg = <IMX8M_POWER_DOMAIN_DDR1>;
667					};
668
669					pgc_gpu: power-domain@5 {
670						#power-domain-cells = <0>;
671						reg = <IMX8M_POWER_DOMAIN_GPU>;
672						clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
673						         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
674							 <&clk IMX8MQ_CLK_GPU_AXI>,
675						         <&clk IMX8MQ_CLK_GPU_AHB>;
676					};
677
678					pgc_vpu: power-domain@6 {
679						#power-domain-cells = <0>;
680						reg = <IMX8M_POWER_DOMAIN_VPU>;
681						clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
682					};
683
684					pgc_disp: power-domain@7 {
685						#power-domain-cells = <0>;
686						reg = <IMX8M_POWER_DOMAIN_DISP>;
687					};
688
689					pgc_mipi_csi1: power-domain@8 {
690						#power-domain-cells = <0>;
691						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
692					};
693
694					pgc_mipi_csi2: power-domain@9 {
695						#power-domain-cells = <0>;
696						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
697					};
698
699					pgc_pcie2: power-domain@a {
700						#power-domain-cells = <0>;
701						reg = <IMX8M_POWER_DOMAIN_PCIE2>;
702					};
703				};
704			};
705		};
706
707		bus@30400000 { /* AIPS2 */
708			compatible = "fsl,aips-bus", "simple-bus";
709			reg = <0x30400000 0x400000>;
710			#address-cells = <1>;
711			#size-cells = <1>;
712			ranges = <0x30400000 0x30400000 0x400000>;
713
714			pwm1: pwm@30660000 {
715				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
716				reg = <0x30660000 0x10000>;
717				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
718				clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
719				         <&clk IMX8MQ_CLK_PWM1_ROOT>;
720				clock-names = "ipg", "per";
721				#pwm-cells = <2>;
722				status = "disabled";
723			};
724
725			pwm2: pwm@30670000 {
726				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
727				reg = <0x30670000 0x10000>;
728				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
729				clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
730				         <&clk IMX8MQ_CLK_PWM2_ROOT>;
731				clock-names = "ipg", "per";
732				#pwm-cells = <2>;
733				status = "disabled";
734			};
735
736			pwm3: pwm@30680000 {
737				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
738				reg = <0x30680000 0x10000>;
739				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
740				clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
741				         <&clk IMX8MQ_CLK_PWM3_ROOT>;
742				clock-names = "ipg", "per";
743				#pwm-cells = <2>;
744				status = "disabled";
745			};
746
747			pwm4: pwm@30690000 {
748				compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
749				reg = <0x30690000 0x10000>;
750				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
751				clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
752				         <&clk IMX8MQ_CLK_PWM4_ROOT>;
753				clock-names = "ipg", "per";
754				#pwm-cells = <2>;
755				status = "disabled";
756			};
757
758			system_counter: timer@306a0000 {
759				compatible = "nxp,sysctr-timer";
760				reg = <0x306a0000 0x20000>;
761				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
762				clocks = <&osc_25m>;
763				clock-names = "per";
764			};
765		};
766
767		bus@30800000 { /* AIPS3 */
768			compatible = "fsl,aips-bus", "simple-bus";
769			reg = <0x30800000 0x400000>;
770			#address-cells = <1>;
771			#size-cells = <1>;
772			ranges = <0x30800000 0x30800000 0x400000>,
773				 <0x08000000 0x08000000 0x10000000>;
774
775			ecspi1: spi@30820000 {
776				#address-cells = <1>;
777				#size-cells = <0>;
778				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
779				reg = <0x30820000 0x10000>;
780				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
781				clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
782					 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
783				clock-names = "ipg", "per";
784				status = "disabled";
785			};
786
787			ecspi2: spi@30830000 {
788				#address-cells = <1>;
789				#size-cells = <0>;
790				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
791				reg = <0x30830000 0x10000>;
792				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
793				clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
794					 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
795				clock-names = "ipg", "per";
796				status = "disabled";
797			};
798
799			ecspi3: spi@30840000 {
800				#address-cells = <1>;
801				#size-cells = <0>;
802				compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
803				reg = <0x30840000 0x10000>;
804				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
805				clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
806					 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
807				clock-names = "ipg", "per";
808				status = "disabled";
809			};
810
811			uart1: serial@30860000 {
812				compatible = "fsl,imx8mq-uart",
813				             "fsl,imx6q-uart";
814				reg = <0x30860000 0x10000>;
815				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
816				clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
817				         <&clk IMX8MQ_CLK_UART1_ROOT>;
818				clock-names = "ipg", "per";
819				status = "disabled";
820			};
821
822			uart3: serial@30880000 {
823				compatible = "fsl,imx8mq-uart",
824				             "fsl,imx6q-uart";
825				reg = <0x30880000 0x10000>;
826				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
827				clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
828				         <&clk IMX8MQ_CLK_UART3_ROOT>;
829				clock-names = "ipg", "per";
830				status = "disabled";
831			};
832
833			uart2: serial@30890000 {
834				compatible = "fsl,imx8mq-uart",
835				             "fsl,imx6q-uart";
836				reg = <0x30890000 0x10000>;
837				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
838				clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
839				         <&clk IMX8MQ_CLK_UART2_ROOT>;
840				clock-names = "ipg", "per";
841				status = "disabled";
842			};
843
844			sai2: sai@308b0000 {
845				#sound-dai-cells = <0>;
846				compatible = "fsl,imx8mq-sai";
847				reg = <0x308b0000 0x10000>;
848				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
849				clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
850					 <&clk IMX8MQ_CLK_SAI2_ROOT>,
851					 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
852				clock-names = "bus", "mclk1", "mclk2", "mclk3";
853				dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
854				dma-names = "rx", "tx";
855				status = "disabled";
856			};
857
858			sai3: sai@308c0000 {
859				#sound-dai-cells = <0>;
860				compatible = "fsl,imx8mq-sai";
861				reg = <0x308c0000 0x10000>;
862				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
863				clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
864				         <&clk IMX8MQ_CLK_SAI3_ROOT>,
865				         <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
866				clock-names = "bus", "mclk1", "mclk2", "mclk3";
867				dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
868				dma-names = "rx", "tx";
869				status = "disabled";
870			};
871
872			crypto: crypto@30900000 {
873				compatible = "fsl,sec-v4.0";
874				#address-cells = <1>;
875				#size-cells = <1>;
876				reg = <0x30900000 0x40000>;
877				ranges = <0 0x30900000 0x40000>;
878				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
879				clocks = <&clk IMX8MQ_CLK_AHB>,
880					 <&clk IMX8MQ_CLK_IPG_ROOT>;
881				clock-names = "aclk", "ipg";
882
883				sec_jr0: jr@1000 {
884					compatible = "fsl,sec-v4.0-job-ring";
885					reg = <0x1000 0x1000>;
886					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
887				};
888
889				sec_jr1: jr@2000 {
890					compatible = "fsl,sec-v4.0-job-ring";
891					reg = <0x2000 0x1000>;
892					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
893				};
894
895				sec_jr2: jr@3000 {
896					compatible = "fsl,sec-v4.0-job-ring";
897					reg = <0x3000 0x1000>;
898					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
899				};
900			};
901
902			dphy: dphy@30a00300 {
903				compatible = "fsl,imx8mq-mipi-dphy";
904				reg = <0x30a00300 0x100>;
905				clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
906				clock-names = "phy_ref";
907				assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
908				assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
909				assigned-clock-rates = <24000000>;
910				#phy-cells = <0>;
911				power-domains = <&pgc_mipi>;
912				status = "disabled";
913			};
914
915			i2c1: i2c@30a20000 {
916				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
917				reg = <0x30a20000 0x10000>;
918				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
919				clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
920				#address-cells = <1>;
921				#size-cells = <0>;
922				status = "disabled";
923			};
924
925			i2c2: i2c@30a30000 {
926				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
927				reg = <0x30a30000 0x10000>;
928				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
929				clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
930				#address-cells = <1>;
931				#size-cells = <0>;
932				status = "disabled";
933			};
934
935			i2c3: i2c@30a40000 {
936				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
937				reg = <0x30a40000 0x10000>;
938				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
939				clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
940				#address-cells = <1>;
941				#size-cells = <0>;
942				status = "disabled";
943			};
944
945			i2c4: i2c@30a50000 {
946				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
947				reg = <0x30a50000 0x10000>;
948				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
949				clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
950				#address-cells = <1>;
951				#size-cells = <0>;
952				status = "disabled";
953			};
954
955			uart4: serial@30a60000 {
956				compatible = "fsl,imx8mq-uart",
957				             "fsl,imx6q-uart";
958				reg = <0x30a60000 0x10000>;
959				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
960				clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
961				         <&clk IMX8MQ_CLK_UART4_ROOT>;
962				clock-names = "ipg", "per";
963				status = "disabled";
964			};
965
966			mu: mailbox@30aa0000 {
967				compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
968				reg = <0x30aa0000 0x10000>;
969				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
970				clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
971				#mbox-cells = <2>;
972			};
973
974			usdhc1: mmc@30b40000 {
975				compatible = "fsl,imx8mq-usdhc",
976				             "fsl,imx7d-usdhc";
977				reg = <0x30b40000 0x10000>;
978				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
979				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
980				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
981				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
982				clock-names = "ipg", "ahb", "per";
983				fsl,tuning-start-tap = <20>;
984				fsl,tuning-step = <2>;
985				bus-width = <4>;
986				status = "disabled";
987			};
988
989			usdhc2: mmc@30b50000 {
990				compatible = "fsl,imx8mq-usdhc",
991				             "fsl,imx7d-usdhc";
992				reg = <0x30b50000 0x10000>;
993				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
994				clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
995				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
996				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
997				clock-names = "ipg", "ahb", "per";
998				fsl,tuning-start-tap = <20>;
999				fsl,tuning-step = <2>;
1000				bus-width = <4>;
1001				status = "disabled";
1002			};
1003
1004			qspi0: spi@30bb0000 {
1005				#address-cells = <1>;
1006				#size-cells = <0>;
1007				compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1008				reg = <0x30bb0000 0x10000>,
1009				      <0x08000000 0x10000000>;
1010				reg-names = "QuadSPI", "QuadSPI-memory";
1011				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1012				clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
1013					 <&clk IMX8MQ_CLK_QSPI_ROOT>;
1014				clock-names = "qspi_en", "qspi";
1015				status = "disabled";
1016			};
1017
1018			sdma1: sdma@30bd0000 {
1019				compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1020				reg = <0x30bd0000 0x10000>;
1021				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1022				clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
1023					 <&clk IMX8MQ_CLK_AHB>;
1024				clock-names = "ipg", "ahb";
1025				#dma-cells = <3>;
1026				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1027			};
1028
1029			fec1: ethernet@30be0000 {
1030				compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1031				reg = <0x30be0000 0x10000>;
1032				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1033				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1034				             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1035				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1036				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
1037				         <&clk IMX8MQ_CLK_ENET_TIMER>,
1038				         <&clk IMX8MQ_CLK_ENET_REF>,
1039				         <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1040				clock-names = "ipg", "ahb", "ptp",
1041				              "enet_clk_ref", "enet_out";
1042				fsl,num-tx-queues = <3>;
1043				fsl,num-rx-queues = <3>;
1044				status = "disabled";
1045			};
1046		};
1047
1048		bus@32c00000 { /* AIPS4 */
1049			compatible = "fsl,aips-bus", "simple-bus";
1050			reg = <0x32c00000 0x400000>;
1051			#address-cells = <1>;
1052			#size-cells = <1>;
1053			ranges = <0x32c00000 0x32c00000 0x400000>;
1054
1055			irqsteer: interrupt-controller@32e2d000 {
1056				compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1057				reg = <0x32e2d000 0x1000>;
1058				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1059				clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
1060				clock-names = "ipg";
1061				fsl,channel = <0>;
1062				fsl,num-irqs = <64>;
1063				interrupt-controller;
1064				#interrupt-cells = <1>;
1065			};
1066		};
1067
1068		gpu: gpu@38000000 {
1069			compatible = "vivante,gc";
1070			reg = <0x38000000 0x40000>;
1071			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1072			clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
1073			         <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
1074			         <&clk IMX8MQ_CLK_GPU_AXI>,
1075			         <&clk IMX8MQ_CLK_GPU_AHB>;
1076			clock-names = "core", "shader", "bus", "reg";
1077			#cooling-cells = <2>;
1078			assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1079			                  <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
1080			                  <&clk IMX8MQ_CLK_GPU_AXI>,
1081			                  <&clk IMX8MQ_CLK_GPU_AHB>,
1082			                  <&clk IMX8MQ_GPU_PLL_BYPASS>;
1083			assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1084			                         <&clk IMX8MQ_GPU_PLL_OUT>,
1085			                         <&clk IMX8MQ_GPU_PLL_OUT>,
1086			                         <&clk IMX8MQ_GPU_PLL_OUT>,
1087			                         <&clk IMX8MQ_GPU_PLL>;
1088			assigned-clock-rates = <800000000>, <800000000>,
1089			                       <800000000>, <800000000>, <0>;
1090			power-domains = <&pgc_gpu>;
1091		};
1092
1093		usb_dwc3_0: usb@38100000 {
1094			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1095			reg = <0x38100000 0x10000>;
1096			clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
1097			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
1098				 <&clk IMX8MQ_CLK_32K>;
1099			clock-names = "bus_early", "ref", "suspend";
1100			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1101			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
1102			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1103			                         <&clk IMX8MQ_SYS1_PLL_100M>;
1104			assigned-clock-rates = <500000000>, <100000000>;
1105			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1106			phys = <&usb3_phy0>, <&usb3_phy0>;
1107			phy-names = "usb2-phy", "usb3-phy";
1108			power-domains = <&pgc_otg1>;
1109			usb3-resume-missing-cas;
1110			status = "disabled";
1111		};
1112
1113		usb3_phy0: usb-phy@381f0040 {
1114			compatible = "fsl,imx8mq-usb-phy";
1115			reg = <0x381f0040 0x40>;
1116			clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1117			clock-names = "phy";
1118			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1119			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1120			assigned-clock-rates = <100000000>;
1121			#phy-cells = <0>;
1122			status = "disabled";
1123		};
1124
1125		usb_dwc3_1: usb@38200000 {
1126			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1127			reg = <0x38200000 0x10000>;
1128			clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1129			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
1130				 <&clk IMX8MQ_CLK_32K>;
1131			clock-names = "bus_early", "ref", "suspend";
1132			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1133			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
1134			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1135			                         <&clk IMX8MQ_SYS1_PLL_100M>;
1136			assigned-clock-rates = <500000000>, <100000000>;
1137			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1138			phys = <&usb3_phy1>, <&usb3_phy1>;
1139			phy-names = "usb2-phy", "usb3-phy";
1140			power-domains = <&pgc_otg2>;
1141			usb3-resume-missing-cas;
1142			status = "disabled";
1143		};
1144
1145		usb3_phy1: usb-phy@382f0040 {
1146			compatible = "fsl,imx8mq-usb-phy";
1147			reg = <0x382f0040 0x40>;
1148			clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1149			clock-names = "phy";
1150			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1151			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1152			assigned-clock-rates = <100000000>;
1153			#phy-cells = <0>;
1154			status = "disabled";
1155		};
1156
1157		vpu: video-codec@38300000 {
1158			compatible = "nxp,imx8mq-vpu";
1159			reg = <0x38300000 0x10000>,
1160			      <0x38310000 0x10000>,
1161			      <0x38320000 0x10000>;
1162			reg-names = "g1", "g2", "ctrl";
1163			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1164				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1165			interrupt-names = "g1", "g2";
1166			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
1167				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
1168				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
1169			clock-names = "g1", "g2", "bus";
1170			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
1171					  <&clk IMX8MQ_CLK_VPU_G2>,
1172					  <&clk IMX8MQ_CLK_VPU_BUS>,
1173					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
1174			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
1175						 <&clk IMX8MQ_VPU_PLL_OUT>,
1176						 <&clk IMX8MQ_SYS1_PLL_800M>,
1177						 <&clk IMX8MQ_VPU_PLL>;
1178			assigned-clock-rates = <600000000>, <600000000>,
1179					       <800000000>, <0>;
1180			power-domains = <&pgc_vpu>;
1181		};
1182
1183		pcie0: pcie@33800000 {
1184			compatible = "fsl,imx8mq-pcie";
1185			reg = <0x33800000 0x400000>,
1186			      <0x1ff00000 0x80000>;
1187			reg-names = "dbi", "config";
1188			#address-cells = <3>;
1189			#size-cells = <2>;
1190			device_type = "pci";
1191			bus-range = <0x00 0xff>;
1192			ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1193			          0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1194			num-lanes = <1>;
1195			num-viewport = <4>;
1196			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1197			interrupt-names = "msi";
1198			#interrupt-cells = <1>;
1199			interrupt-map-mask = <0 0 0 0x7>;
1200			interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1201			                <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1202			                <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1203			                <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1204			fsl,max-link-speed = <2>;
1205			power-domains = <&pgc_pcie>;
1206			resets = <&src IMX8MQ_RESET_PCIEPHY>,
1207			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1208			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1209			reset-names = "pciephy", "apps", "turnoff";
1210			status = "disabled";
1211		};
1212
1213		pcie1: pcie@33c00000 {
1214			compatible = "fsl,imx8mq-pcie";
1215			reg = <0x33c00000 0x400000>,
1216			      <0x27f00000 0x80000>;
1217			reg-names = "dbi", "config";
1218			#address-cells = <3>;
1219			#size-cells = <2>;
1220			device_type = "pci";
1221			ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1222				   0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1223			num-lanes = <1>;
1224			num-viewport = <4>;
1225			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1226			interrupt-names = "msi";
1227			#interrupt-cells = <1>;
1228			interrupt-map-mask = <0 0 0 0x7>;
1229			interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1230					<0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1231					<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1232					<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1233			fsl,max-link-speed = <2>;
1234			power-domains = <&pgc_pcie>;
1235			resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1236			         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1237			         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1238			reset-names = "pciephy", "apps", "turnoff";
1239			status = "disabled";
1240		};
1241
1242		gic: interrupt-controller@38800000 {
1243			compatible = "arm,gic-v3";
1244			reg = <0x38800000 0x10000>,	/* GIC Dist */
1245			      <0x38880000 0xc0000>,	/* GICR */
1246			      <0x31000000 0x2000>,	/* GICC */
1247			      <0x31010000 0x2000>,	/* GICV */
1248			      <0x31020000 0x2000>;	/* GICH */
1249			#interrupt-cells = <3>;
1250			interrupt-controller;
1251			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1252			interrupt-parent = <&gic>;
1253		};
1254
1255		ddrc: memory-controller@3d400000 {
1256			compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1257			reg = <0x3d400000 0x400000>;
1258			clock-names = "core", "pll", "alt", "apb";
1259			clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1260				 <&clk IMX8MQ_DRAM_PLL_OUT>,
1261				 <&clk IMX8MQ_CLK_DRAM_ALT>,
1262				 <&clk IMX8MQ_CLK_DRAM_APB>;
1263		};
1264
1265		ddr-pmu@3d800000 {
1266			compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1267			reg = <0x3d800000 0x400000>;
1268			interrupt-parent = <&gic>;
1269			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1270		};
1271	};
1272};
1273