1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7#include <dt-bindings/clock/imx8mq-clock.h> 8#include <dt-bindings/power/imx8mq-power.h> 9#include <dt-bindings/reset/imx8mq-reset.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "dt-bindings/input/input.h" 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/interconnect/imx8mq.h> 15#include "imx8mq-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gpc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ethernet0 = &fec1; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 mmc0 = &usdhc1; 35 mmc1 = &usdhc2; 36 serial0 = &uart1; 37 serial1 = &uart2; 38 serial2 = &uart3; 39 serial3 = &uart4; 40 spi0 = &ecspi1; 41 spi1 = &ecspi2; 42 spi2 = &ecspi3; 43 }; 44 45 ckil: clock-ckil { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <32768>; 49 clock-output-names = "ckil"; 50 }; 51 52 osc_25m: clock-osc-25m { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 clock-output-names = "osc_25m"; 57 }; 58 59 osc_27m: clock-osc-27m { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <27000000>; 63 clock-output-names = "osc_27m"; 64 }; 65 66 hdmi_phy_27m: clock-hdmi-phy-27m { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <27000000>; 70 clock-output-names = "hdmi_phy_27m"; 71 }; 72 73 clk_ext1: clock-ext1 { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <133000000>; 77 clock-output-names = "clk_ext1"; 78 }; 79 80 clk_ext2: clock-ext2 { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <133000000>; 84 clock-output-names = "clk_ext2"; 85 }; 86 87 clk_ext3: clock-ext3 { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <133000000>; 91 clock-output-names = "clk_ext3"; 92 }; 93 94 clk_ext4: clock-ext4 { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <133000000>; 98 clock-output-names = "clk_ext4"; 99 }; 100 101 cpus { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 105 A53_0: cpu@0 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0>; 109 clock-latency = <61036>; /* two CLK32 periods */ 110 clocks = <&clk IMX8MQ_CLK_ARM>; 111 enable-method = "psci"; 112 i-cache-size = <0x8000>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <256>; 115 d-cache-size = <0x8000>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <128>; 118 next-level-cache = <&A53_L2>; 119 operating-points-v2 = <&a53_opp_table>; 120 #cooling-cells = <2>; 121 nvmem-cells = <&cpu_speed_grade>; 122 nvmem-cell-names = "speed_grade"; 123 }; 124 125 A53_1: cpu@1 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53"; 128 reg = <0x1>; 129 clock-latency = <61036>; /* two CLK32 periods */ 130 clocks = <&clk IMX8MQ_CLK_ARM>; 131 enable-method = "psci"; 132 i-cache-size = <0x8000>; 133 i-cache-line-size = <64>; 134 i-cache-sets = <256>; 135 d-cache-size = <0x8000>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <128>; 138 next-level-cache = <&A53_L2>; 139 operating-points-v2 = <&a53_opp_table>; 140 #cooling-cells = <2>; 141 }; 142 143 A53_2: cpu@2 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a53"; 146 reg = <0x2>; 147 clock-latency = <61036>; /* two CLK32 periods */ 148 clocks = <&clk IMX8MQ_CLK_ARM>; 149 enable-method = "psci"; 150 i-cache-size = <0x8000>; 151 i-cache-line-size = <64>; 152 i-cache-sets = <256>; 153 d-cache-size = <0x8000>; 154 d-cache-line-size = <64>; 155 d-cache-sets = <128>; 156 next-level-cache = <&A53_L2>; 157 operating-points-v2 = <&a53_opp_table>; 158 #cooling-cells = <2>; 159 }; 160 161 A53_3: cpu@3 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a53"; 164 reg = <0x3>; 165 clock-latency = <61036>; /* two CLK32 periods */ 166 clocks = <&clk IMX8MQ_CLK_ARM>; 167 enable-method = "psci"; 168 i-cache-size = <0x8000>; 169 i-cache-line-size = <64>; 170 i-cache-sets = <256>; 171 d-cache-size = <0x8000>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 next-level-cache = <&A53_L2>; 175 operating-points-v2 = <&a53_opp_table>; 176 #cooling-cells = <2>; 177 }; 178 179 A53_L2: l2-cache0 { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-size = <0x100000>; 183 cache-line-size = <64>; 184 cache-sets = <1024>; 185 }; 186 }; 187 188 a53_opp_table: opp-table { 189 compatible = "operating-points-v2"; 190 opp-shared; 191 192 opp-800000000 { 193 opp-hz = /bits/ 64 <800000000>; 194 opp-microvolt = <900000>; 195 /* Industrial only */ 196 opp-supported-hw = <0xf>, <0x4>; 197 clock-latency-ns = <150000>; 198 opp-suspend; 199 }; 200 201 opp-1000000000 { 202 opp-hz = /bits/ 64 <1000000000>; 203 opp-microvolt = <900000>; 204 /* Consumer only */ 205 opp-supported-hw = <0xe>, <0x3>; 206 clock-latency-ns = <150000>; 207 opp-suspend; 208 }; 209 210 opp-1300000000 { 211 opp-hz = /bits/ 64 <1300000000>; 212 opp-microvolt = <1000000>; 213 opp-supported-hw = <0xc>, <0x4>; 214 clock-latency-ns = <150000>; 215 opp-suspend; 216 }; 217 218 opp-1500000000 { 219 opp-hz = /bits/ 64 <1500000000>; 220 opp-microvolt = <1000000>; 221 opp-supported-hw = <0x8>, <0x3>; 222 clock-latency-ns = <150000>; 223 opp-suspend; 224 }; 225 }; 226 227 pmu { 228 compatible = "arm,cortex-a53-pmu"; 229 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-parent = <&gic>; 231 }; 232 233 psci { 234 compatible = "arm,psci-1.0"; 235 method = "smc"; 236 }; 237 238 thermal-zones { 239 cpu_thermal: cpu-thermal { 240 polling-delay-passive = <250>; 241 polling-delay = <2000>; 242 thermal-sensors = <&tmu 0>; 243 244 trips { 245 cpu_alert: cpu-alert { 246 temperature = <80000>; 247 hysteresis = <2000>; 248 type = "passive"; 249 }; 250 251 cpu-crit { 252 temperature = <90000>; 253 hysteresis = <2000>; 254 type = "critical"; 255 }; 256 }; 257 258 cooling-maps { 259 map0 { 260 trip = <&cpu_alert>; 261 cooling-device = 262 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 263 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 264 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 265 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 266 }; 267 }; 268 }; 269 270 gpu-thermal { 271 polling-delay-passive = <250>; 272 polling-delay = <2000>; 273 thermal-sensors = <&tmu 1>; 274 275 trips { 276 gpu_alert: gpu-alert { 277 temperature = <80000>; 278 hysteresis = <2000>; 279 type = "passive"; 280 }; 281 282 gpu-crit { 283 temperature = <90000>; 284 hysteresis = <2000>; 285 type = "critical"; 286 }; 287 }; 288 289 cooling-maps { 290 map0 { 291 trip = <&gpu_alert>; 292 cooling-device = 293 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 294 }; 295 }; 296 }; 297 298 vpu-thermal { 299 polling-delay-passive = <250>; 300 polling-delay = <2000>; 301 thermal-sensors = <&tmu 2>; 302 303 trips { 304 vpu-crit { 305 temperature = <90000>; 306 hysteresis = <2000>; 307 type = "critical"; 308 }; 309 }; 310 }; 311 }; 312 313 timer { 314 compatible = "arm,armv8-timer"; 315 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 316 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 317 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 318 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 319 interrupt-parent = <&gic>; 320 arm,no-tick-in-suspend; 321 }; 322 323 soc: soc@0 { 324 compatible = "fsl,imx8mq-soc", "simple-bus"; 325 #address-cells = <1>; 326 #size-cells = <1>; 327 ranges = <0x0 0x0 0x0 0x3e000000>; 328 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 329 nvmem-cells = <&imx8mq_uid>; 330 nvmem-cell-names = "soc_unique_id"; 331 332 aips1: bus@30000000 { /* AIPS1 */ 333 compatible = "fsl,aips-bus", "simple-bus"; 334 reg = <0x30000000 0x400000>; 335 #address-cells = <1>; 336 #size-cells = <1>; 337 ranges = <0x30000000 0x30000000 0x400000>; 338 339 sai1: sai@30010000 { 340 #sound-dai-cells = <0>; 341 compatible = "fsl,imx8mq-sai"; 342 reg = <0x30010000 0x10000>; 343 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, 345 <&clk IMX8MQ_CLK_SAI1_ROOT>, 346 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 347 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 348 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; 349 dma-names = "rx", "tx"; 350 status = "disabled"; 351 }; 352 353 sai6: sai@30030000 { 354 #sound-dai-cells = <0>; 355 compatible = "fsl,imx8mq-sai"; 356 reg = <0x30030000 0x10000>; 357 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, 359 <&clk IMX8MQ_CLK_SAI6_ROOT>, 360 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 361 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 362 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; 363 dma-names = "rx", "tx"; 364 status = "disabled"; 365 }; 366 367 sai5: sai@30040000 { 368 #sound-dai-cells = <0>; 369 compatible = "fsl,imx8mq-sai"; 370 reg = <0x30040000 0x10000>; 371 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, 373 <&clk IMX8MQ_CLK_SAI5_ROOT>, 374 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 375 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 376 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; 377 dma-names = "rx", "tx"; 378 status = "disabled"; 379 }; 380 381 sai4: sai@30050000 { 382 #sound-dai-cells = <0>; 383 compatible = "fsl,imx8mq-sai"; 384 reg = <0x30050000 0x10000>; 385 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, 387 <&clk IMX8MQ_CLK_SAI4_ROOT>, 388 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 389 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 390 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; 391 dma-names = "rx", "tx"; 392 status = "disabled"; 393 }; 394 395 gpio1: gpio@30200000 { 396 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 397 reg = <0x30200000 0x10000>; 398 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; 401 gpio-controller; 402 #gpio-cells = <2>; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 gpio-ranges = <&iomuxc 0 10 30>; 406 }; 407 408 gpio2: gpio@30210000 { 409 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 410 reg = <0x30210000 0x10000>; 411 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; 414 gpio-controller; 415 #gpio-cells = <2>; 416 interrupt-controller; 417 #interrupt-cells = <2>; 418 gpio-ranges = <&iomuxc 0 40 21>; 419 }; 420 421 gpio3: gpio@30220000 { 422 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 423 reg = <0x30220000 0x10000>; 424 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; 427 gpio-controller; 428 #gpio-cells = <2>; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 gpio-ranges = <&iomuxc 0 61 26>; 432 }; 433 434 gpio4: gpio@30230000 { 435 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 436 reg = <0x30230000 0x10000>; 437 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 gpio-ranges = <&iomuxc 0 87 32>; 445 }; 446 447 gpio5: gpio@30240000 { 448 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 449 reg = <0x30240000 0x10000>; 450 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; 453 gpio-controller; 454 #gpio-cells = <2>; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 gpio-ranges = <&iomuxc 0 119 30>; 458 }; 459 460 tmu: tmu@30260000 { 461 compatible = "fsl,imx8mq-tmu"; 462 reg = <0x30260000 0x10000>; 463 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; 465 little-endian; 466 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 467 fsl,tmu-calibration = <0x00000000 0x00000023>, 468 <0x00000001 0x00000029>, 469 <0x00000002 0x0000002f>, 470 <0x00000003 0x00000035>, 471 <0x00000004 0x0000003d>, 472 <0x00000005 0x00000043>, 473 <0x00000006 0x0000004b>, 474 <0x00000007 0x00000051>, 475 <0x00000008 0x00000057>, 476 <0x00000009 0x0000005f>, 477 <0x0000000a 0x00000067>, 478 <0x0000000b 0x0000006f>, 479 480 <0x00010000 0x0000001b>, 481 <0x00010001 0x00000023>, 482 <0x00010002 0x0000002b>, 483 <0x00010003 0x00000033>, 484 <0x00010004 0x0000003b>, 485 <0x00010005 0x00000043>, 486 <0x00010006 0x0000004b>, 487 <0x00010007 0x00000055>, 488 <0x00010008 0x0000005d>, 489 <0x00010009 0x00000067>, 490 <0x0001000a 0x00000070>, 491 492 <0x00020000 0x00000017>, 493 <0x00020001 0x00000023>, 494 <0x00020002 0x0000002d>, 495 <0x00020003 0x00000037>, 496 <0x00020004 0x00000041>, 497 <0x00020005 0x0000004b>, 498 <0x00020006 0x00000057>, 499 <0x00020007 0x00000063>, 500 <0x00020008 0x0000006f>, 501 502 <0x00030000 0x00000015>, 503 <0x00030001 0x00000021>, 504 <0x00030002 0x0000002d>, 505 <0x00030003 0x00000039>, 506 <0x00030004 0x00000045>, 507 <0x00030005 0x00000053>, 508 <0x00030006 0x0000005f>, 509 <0x00030007 0x00000071>; 510 #thermal-sensor-cells = <1>; 511 }; 512 513 wdog1: watchdog@30280000 { 514 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 515 reg = <0x30280000 0x10000>; 516 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; 518 status = "disabled"; 519 }; 520 521 wdog2: watchdog@30290000 { 522 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 523 reg = <0x30290000 0x10000>; 524 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; 526 status = "disabled"; 527 }; 528 529 wdog3: watchdog@302a0000 { 530 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 531 reg = <0x302a0000 0x10000>; 532 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; 534 status = "disabled"; 535 }; 536 537 sdma2: dma-controller@302c0000 { 538 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 539 reg = <0x302c0000 0x10000>; 540 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, 542 <&clk IMX8MQ_CLK_SDMA2_ROOT>; 543 clock-names = "ipg", "ahb"; 544 #dma-cells = <3>; 545 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 546 }; 547 548 lcdif: lcd-controller@30320000 { 549 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; 550 reg = <0x30320000 0x10000>; 551 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 553 clock-names = "pix"; 554 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 555 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 556 <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 557 <&clk IMX8MQ_VIDEO_PLL1>; 558 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 559 <&clk IMX8MQ_VIDEO_PLL1>, 560 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 561 assigned-clock-rates = <0>, <0>, <0>, <594000000>; 562 status = "disabled"; 563 564 port { 565 lcdif_mipi_dsi: endpoint { 566 remote-endpoint = <&mipi_dsi_lcdif_in>; 567 }; 568 }; 569 }; 570 571 iomuxc: pinctrl@30330000 { 572 compatible = "fsl,imx8mq-iomuxc"; 573 reg = <0x30330000 0x10000>; 574 }; 575 576 iomuxc_gpr: syscon@30340000 { 577 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", 578 "syscon", "simple-mfd"; 579 reg = <0x30340000 0x10000>; 580 581 mux: mux-controller { 582 compatible = "mmio-mux"; 583 #mux-control-cells = <1>; 584 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ 585 }; 586 }; 587 588 ocotp: efuse@30350000 { 589 compatible = "fsl,imx8mq-ocotp", "syscon"; 590 reg = <0x30350000 0x10000>; 591 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 592 #address-cells = <1>; 593 #size-cells = <1>; 594 595 imx8mq_uid: soc-uid@410 { 596 reg = <0x4 0x8>; 597 }; 598 599 cpu_speed_grade: speed-grade@10 { 600 reg = <0x10 4>; 601 }; 602 603 fec_mac_address: mac-address@90 { 604 reg = <0x90 6>; 605 }; 606 }; 607 608 anatop: syscon@30360000 { 609 compatible = "fsl,imx8mq-anatop", "syscon"; 610 reg = <0x30360000 0x10000>; 611 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 612 }; 613 614 snvs: snvs@30370000 { 615 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 616 reg = <0x30370000 0x10000>; 617 618 snvs_rtc: snvs-rtc-lp{ 619 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 620 regmap =<&snvs>; 621 offset = <0x34>; 622 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 625 clock-names = "snvs-rtc"; 626 }; 627 628 snvs_pwrkey: snvs-powerkey { 629 compatible = "fsl,sec-v4.0-pwrkey"; 630 regmap = <&snvs>; 631 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 633 clock-names = "snvs-pwrkey"; 634 linux,keycode = <KEY_POWER>; 635 wakeup-source; 636 status = "disabled"; 637 }; 638 }; 639 640 clk: clock-controller@30380000 { 641 compatible = "fsl,imx8mq-ccm"; 642 reg = <0x30380000 0x10000>; 643 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 645 #clock-cells = <1>; 646 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, 647 <&clk_ext1>, <&clk_ext2>, 648 <&clk_ext3>, <&clk_ext4>; 649 clock-names = "ckil", "osc_25m", "osc_27m", 650 "clk_ext1", "clk_ext2", 651 "clk_ext3", "clk_ext4"; 652 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, 653 <&clk IMX8MQ_CLK_A53_CORE>, 654 <&clk IMX8MQ_CLK_NOC>, 655 <&clk IMX8MQ_CLK_AUDIO_AHB>, 656 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, 657 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, 658 <&clk IMX8MQ_AUDIO_PLL1>, 659 <&clk IMX8MQ_AUDIO_PLL2>; 660 assigned-clock-rates = <0>, <0>, 661 <800000000>, 662 <0>, 663 <0>, 664 <0>, 665 <786432000>, 666 <722534400>; 667 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, 668 <&clk IMX8MQ_ARM_PLL_OUT>, 669 <0>, 670 <&clk IMX8MQ_SYS2_PLL_500M>, 671 <&clk IMX8MQ_AUDIO_PLL1>, 672 <&clk IMX8MQ_AUDIO_PLL2>; 673 }; 674 675 src: reset-controller@30390000 { 676 compatible = "fsl,imx8mq-src", "syscon"; 677 reg = <0x30390000 0x10000>; 678 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 679 #reset-cells = <1>; 680 }; 681 682 gpc: gpc@303a0000 { 683 compatible = "fsl,imx8mq-gpc"; 684 reg = <0x303a0000 0x10000>; 685 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 686 interrupt-parent = <&gic>; 687 interrupt-controller; 688 #interrupt-cells = <3>; 689 690 pgc { 691 #address-cells = <1>; 692 #size-cells = <0>; 693 694 pgc_mipi: power-domain@0 { 695 #power-domain-cells = <0>; 696 reg = <IMX8M_POWER_DOMAIN_MIPI>; 697 }; 698 699 /* 700 * As per comment in ATF source code: 701 * 702 * PCIE1 and PCIE2 share the 703 * same reset signal, if we 704 * power down PCIE2, PCIE1 705 * will be held in reset too. 706 * 707 * So instead of creating two 708 * separate power domains for 709 * PCIE1 and PCIE2 we create a 710 * link between both and use 711 * it as a shared PCIE power 712 * domain. 713 */ 714 pgc_pcie: power-domain@1 { 715 #power-domain-cells = <0>; 716 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 717 power-domains = <&pgc_pcie2>; 718 }; 719 720 pgc_otg1: power-domain@2 { 721 #power-domain-cells = <0>; 722 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; 723 }; 724 725 pgc_otg2: power-domain@3 { 726 #power-domain-cells = <0>; 727 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; 728 }; 729 730 pgc_ddr1: power-domain@4 { 731 #power-domain-cells = <0>; 732 reg = <IMX8M_POWER_DOMAIN_DDR1>; 733 }; 734 735 pgc_gpu: power-domain@5 { 736 #power-domain-cells = <0>; 737 reg = <IMX8M_POWER_DOMAIN_GPU>; 738 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 739 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 740 <&clk IMX8MQ_CLK_GPU_AXI>, 741 <&clk IMX8MQ_CLK_GPU_AHB>; 742 }; 743 744 pgc_vpu: power-domain@6 { 745 #power-domain-cells = <0>; 746 reg = <IMX8M_POWER_DOMAIN_VPU>; 747 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, 748 <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 749 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 750 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, 751 <&clk IMX8MQ_CLK_VPU_G2>, 752 <&clk IMX8MQ_CLK_VPU_BUS>, 753 <&clk IMX8MQ_VPU_PLL_BYPASS>; 754 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, 755 <&clk IMX8MQ_VPU_PLL_OUT>, 756 <&clk IMX8MQ_SYS1_PLL_800M>, 757 <&clk IMX8MQ_VPU_PLL>; 758 assigned-clock-rates = <600000000>, 759 <600000000>, 760 <800000000>, 761 <0>; 762 }; 763 764 pgc_disp: power-domain@7 { 765 #power-domain-cells = <0>; 766 reg = <IMX8M_POWER_DOMAIN_DISP>; 767 }; 768 769 pgc_mipi_csi1: power-domain@8 { 770 #power-domain-cells = <0>; 771 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; 772 }; 773 774 pgc_mipi_csi2: power-domain@9 { 775 #power-domain-cells = <0>; 776 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; 777 }; 778 779 pgc_pcie2: power-domain@a { 780 #power-domain-cells = <0>; 781 reg = <IMX8M_POWER_DOMAIN_PCIE2>; 782 }; 783 }; 784 }; 785 }; 786 787 aips2: bus@30400000 { /* AIPS2 */ 788 compatible = "fsl,aips-bus", "simple-bus"; 789 reg = <0x30400000 0x400000>; 790 #address-cells = <1>; 791 #size-cells = <1>; 792 ranges = <0x30400000 0x30400000 0x400000>; 793 794 pwm1: pwm@30660000 { 795 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 796 reg = <0x30660000 0x10000>; 797 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, 799 <&clk IMX8MQ_CLK_PWM1_ROOT>; 800 clock-names = "ipg", "per"; 801 #pwm-cells = <3>; 802 status = "disabled"; 803 }; 804 805 pwm2: pwm@30670000 { 806 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 807 reg = <0x30670000 0x10000>; 808 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, 810 <&clk IMX8MQ_CLK_PWM2_ROOT>; 811 clock-names = "ipg", "per"; 812 #pwm-cells = <3>; 813 status = "disabled"; 814 }; 815 816 pwm3: pwm@30680000 { 817 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 818 reg = <0x30680000 0x10000>; 819 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, 821 <&clk IMX8MQ_CLK_PWM3_ROOT>; 822 clock-names = "ipg", "per"; 823 #pwm-cells = <3>; 824 status = "disabled"; 825 }; 826 827 pwm4: pwm@30690000 { 828 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 829 reg = <0x30690000 0x10000>; 830 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, 832 <&clk IMX8MQ_CLK_PWM4_ROOT>; 833 clock-names = "ipg", "per"; 834 #pwm-cells = <3>; 835 status = "disabled"; 836 }; 837 838 system_counter: timer@306a0000 { 839 compatible = "nxp,sysctr-timer"; 840 reg = <0x306a0000 0x20000>; 841 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&osc_25m>; 843 clock-names = "per"; 844 }; 845 }; 846 847 aips3: bus@30800000 { /* AIPS3 */ 848 compatible = "fsl,aips-bus", "simple-bus"; 849 reg = <0x30800000 0x400000>; 850 #address-cells = <1>; 851 #size-cells = <1>; 852 ranges = <0x30800000 0x30800000 0x400000>, 853 <0x08000000 0x08000000 0x10000000>; 854 855 spdif1: spdif@30810000 { 856 compatible = "fsl,imx35-spdif"; 857 reg = <0x30810000 0x10000>; 858 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 860 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 861 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ 862 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 863 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 864 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 865 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 866 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 867 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 868 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 869 clock-names = "core", "rxtx0", 870 "rxtx1", "rxtx2", 871 "rxtx3", "rxtx4", 872 "rxtx5", "rxtx6", 873 "rxtx7", "spba"; 874 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; 875 dma-names = "rx", "tx"; 876 status = "disabled"; 877 }; 878 879 ecspi1: spi@30820000 { 880 #address-cells = <1>; 881 #size-cells = <0>; 882 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 883 reg = <0x30820000 0x10000>; 884 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, 886 <&clk IMX8MQ_CLK_ECSPI1_ROOT>; 887 clock-names = "ipg", "per"; 888 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 889 dma-names = "rx", "tx"; 890 status = "disabled"; 891 }; 892 893 ecspi2: spi@30830000 { 894 #address-cells = <1>; 895 #size-cells = <0>; 896 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 897 reg = <0x30830000 0x10000>; 898 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, 900 <&clk IMX8MQ_CLK_ECSPI2_ROOT>; 901 clock-names = "ipg", "per"; 902 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 903 dma-names = "rx", "tx"; 904 status = "disabled"; 905 }; 906 907 ecspi3: spi@30840000 { 908 #address-cells = <1>; 909 #size-cells = <0>; 910 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 911 reg = <0x30840000 0x10000>; 912 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, 914 <&clk IMX8MQ_CLK_ECSPI3_ROOT>; 915 clock-names = "ipg", "per"; 916 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 917 dma-names = "rx", "tx"; 918 status = "disabled"; 919 }; 920 921 uart1: serial@30860000 { 922 compatible = "fsl,imx8mq-uart", 923 "fsl,imx6q-uart"; 924 reg = <0x30860000 0x10000>; 925 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, 927 <&clk IMX8MQ_CLK_UART1_ROOT>; 928 clock-names = "ipg", "per"; 929 status = "disabled"; 930 }; 931 932 uart3: serial@30880000 { 933 compatible = "fsl,imx8mq-uart", 934 "fsl,imx6q-uart"; 935 reg = <0x30880000 0x10000>; 936 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, 938 <&clk IMX8MQ_CLK_UART3_ROOT>; 939 clock-names = "ipg", "per"; 940 status = "disabled"; 941 }; 942 943 uart2: serial@30890000 { 944 compatible = "fsl,imx8mq-uart", 945 "fsl,imx6q-uart"; 946 reg = <0x30890000 0x10000>; 947 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, 949 <&clk IMX8MQ_CLK_UART2_ROOT>; 950 clock-names = "ipg", "per"; 951 status = "disabled"; 952 }; 953 954 spdif2: spdif@308a0000 { 955 compatible = "fsl,imx35-spdif"; 956 reg = <0x308a0000 0x10000>; 957 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 959 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 960 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ 961 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 962 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 963 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 964 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 965 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 966 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 967 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 968 clock-names = "core", "rxtx0", 969 "rxtx1", "rxtx2", 970 "rxtx3", "rxtx4", 971 "rxtx5", "rxtx6", 972 "rxtx7", "spba"; 973 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; 974 dma-names = "rx", "tx"; 975 status = "disabled"; 976 }; 977 978 sai2: sai@308b0000 { 979 #sound-dai-cells = <0>; 980 compatible = "fsl,imx8mq-sai"; 981 reg = <0x308b0000 0x10000>; 982 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, 984 <&clk IMX8MQ_CLK_SAI2_ROOT>, 985 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 986 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 987 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; 988 dma-names = "rx", "tx"; 989 status = "disabled"; 990 }; 991 992 sai3: sai@308c0000 { 993 #sound-dai-cells = <0>; 994 compatible = "fsl,imx8mq-sai"; 995 reg = <0x308c0000 0x10000>; 996 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, 998 <&clk IMX8MQ_CLK_SAI3_ROOT>, 999 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 1000 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1001 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; 1002 dma-names = "rx", "tx"; 1003 status = "disabled"; 1004 }; 1005 1006 crypto: crypto@30900000 { 1007 compatible = "fsl,sec-v4.0"; 1008 #address-cells = <1>; 1009 #size-cells = <1>; 1010 reg = <0x30900000 0x40000>; 1011 ranges = <0 0x30900000 0x40000>; 1012 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&clk IMX8MQ_CLK_AHB>, 1014 <&clk IMX8MQ_CLK_IPG_ROOT>; 1015 clock-names = "aclk", "ipg"; 1016 1017 sec_jr0: jr@1000 { 1018 compatible = "fsl,sec-v4.0-job-ring"; 1019 reg = <0x1000 0x1000>; 1020 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1021 status = "disabled"; 1022 }; 1023 1024 sec_jr1: jr@2000 { 1025 compatible = "fsl,sec-v4.0-job-ring"; 1026 reg = <0x2000 0x1000>; 1027 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1028 }; 1029 1030 sec_jr2: jr@3000 { 1031 compatible = "fsl,sec-v4.0-job-ring"; 1032 reg = <0x3000 0x1000>; 1033 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1034 }; 1035 }; 1036 1037 mipi_dsi: mipi-dsi@30a00000 { 1038 compatible = "fsl,imx8mq-nwl-dsi"; 1039 reg = <0x30a00000 0x300>; 1040 clocks = <&clk IMX8MQ_CLK_DSI_CORE>, 1041 <&clk IMX8MQ_CLK_DSI_AHB>, 1042 <&clk IMX8MQ_CLK_DSI_IPG_DIV>, 1043 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1044 <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 1045 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; 1046 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, 1047 <&clk IMX8MQ_CLK_DSI_CORE>, 1048 <&clk IMX8MQ_CLK_DSI_IPG_DIV>; 1049 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, 1050 <&clk IMX8MQ_SYS1_PLL_266M>; 1051 assigned-clock-rates = <80000000>, <266000000>, <20000000>; 1052 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1053 mux-controls = <&mux 0>; 1054 power-domains = <&pgc_mipi>; 1055 phys = <&dphy>; 1056 phy-names = "dphy"; 1057 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, 1058 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, 1059 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, 1060 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; 1061 reset-names = "byte", "dpi", "esc", "pclk"; 1062 status = "disabled"; 1063 1064 ports { 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 1068 port@0 { 1069 reg = <0>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 mipi_dsi_lcdif_in: endpoint@0 { 1073 reg = <0>; 1074 remote-endpoint = <&lcdif_mipi_dsi>; 1075 }; 1076 }; 1077 }; 1078 }; 1079 1080 dphy: dphy@30a00300 { 1081 compatible = "fsl,imx8mq-mipi-dphy"; 1082 reg = <0x30a00300 0x100>; 1083 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 1084 clock-names = "phy_ref"; 1085 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 1086 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 1087 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1088 <&clk IMX8MQ_VIDEO_PLL1>; 1089 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 1090 <&clk IMX8MQ_VIDEO_PLL1>, 1091 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 1092 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; 1093 #phy-cells = <0>; 1094 power-domains = <&pgc_mipi>; 1095 status = "disabled"; 1096 }; 1097 1098 i2c1: i2c@30a20000 { 1099 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1100 reg = <0x30a20000 0x10000>; 1101 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 status = "disabled"; 1106 }; 1107 1108 i2c2: i2c@30a30000 { 1109 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1110 reg = <0x30a30000 0x10000>; 1111 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 status = "disabled"; 1116 }; 1117 1118 i2c3: i2c@30a40000 { 1119 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1120 reg = <0x30a40000 0x10000>; 1121 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 i2c4: i2c@30a50000 { 1129 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1130 reg = <0x30a50000 0x10000>; 1131 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 status = "disabled"; 1136 }; 1137 1138 uart4: serial@30a60000 { 1139 compatible = "fsl,imx8mq-uart", 1140 "fsl,imx6q-uart"; 1141 reg = <0x30a60000 0x10000>; 1142 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, 1144 <&clk IMX8MQ_CLK_UART4_ROOT>; 1145 clock-names = "ipg", "per"; 1146 status = "disabled"; 1147 }; 1148 1149 mipi_csi1: csi@30a70000 { 1150 compatible = "fsl,imx8mq-mipi-csi2"; 1151 reg = <0x30a70000 0x1000>; 1152 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1153 <&clk IMX8MQ_CLK_CSI1_ESC>, 1154 <&clk IMX8MQ_CLK_CSI1_PHY_REF>; 1155 clock-names = "core", "esc", "ui"; 1156 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1157 <&clk IMX8MQ_CLK_CSI1_PHY_REF>, 1158 <&clk IMX8MQ_CLK_CSI1_ESC>; 1159 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1160 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1161 <&clk IMX8MQ_SYS2_PLL_1000M>, 1162 <&clk IMX8MQ_SYS1_PLL_800M>; 1163 power-domains = <&pgc_mipi_csi1>; 1164 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, 1165 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, 1166 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; 1167 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; 1168 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; 1169 interconnect-names = "dram"; 1170 status = "disabled"; 1171 1172 ports { 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 1176 port@1 { 1177 reg = <1>; 1178 1179 csi1_mipi_ep: endpoint { 1180 remote-endpoint = <&csi1_ep>; 1181 }; 1182 }; 1183 }; 1184 }; 1185 1186 csi1: csi@30a90000 { 1187 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; 1188 reg = <0x30a90000 0x10000>; 1189 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; 1191 clock-names = "mclk"; 1192 status = "disabled"; 1193 1194 port { 1195 csi1_ep: endpoint { 1196 remote-endpoint = <&csi1_mipi_ep>; 1197 }; 1198 }; 1199 }; 1200 1201 mipi_csi2: csi@30b60000 { 1202 compatible = "fsl,imx8mq-mipi-csi2"; 1203 reg = <0x30b60000 0x1000>; 1204 clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1205 <&clk IMX8MQ_CLK_CSI2_ESC>, 1206 <&clk IMX8MQ_CLK_CSI2_PHY_REF>; 1207 clock-names = "core", "esc", "ui"; 1208 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1209 <&clk IMX8MQ_CLK_CSI2_PHY_REF>, 1210 <&clk IMX8MQ_CLK_CSI2_ESC>; 1211 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1212 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1213 <&clk IMX8MQ_SYS2_PLL_1000M>, 1214 <&clk IMX8MQ_SYS1_PLL_800M>; 1215 power-domains = <&pgc_mipi_csi2>; 1216 resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, 1217 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, 1218 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; 1219 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; 1220 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; 1221 interconnect-names = "dram"; 1222 status = "disabled"; 1223 1224 ports { 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 1228 port@1 { 1229 reg = <1>; 1230 1231 csi2_mipi_ep: endpoint { 1232 remote-endpoint = <&csi2_ep>; 1233 }; 1234 }; 1235 }; 1236 }; 1237 1238 csi2: csi@30b80000 { 1239 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; 1240 reg = <0x30b80000 0x10000>; 1241 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; 1243 clock-names = "mclk"; 1244 status = "disabled"; 1245 1246 port { 1247 csi2_ep: endpoint { 1248 remote-endpoint = <&csi2_mipi_ep>; 1249 }; 1250 }; 1251 }; 1252 1253 mu: mailbox@30aa0000 { 1254 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; 1255 reg = <0x30aa0000 0x10000>; 1256 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&clk IMX8MQ_CLK_MU_ROOT>; 1258 #mbox-cells = <2>; 1259 }; 1260 1261 usdhc1: mmc@30b40000 { 1262 compatible = "fsl,imx8mq-usdhc", 1263 "fsl,imx7d-usdhc"; 1264 reg = <0x30b40000 0x10000>; 1265 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1267 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1268 <&clk IMX8MQ_CLK_USDHC1_ROOT>; 1269 clock-names = "ipg", "ahb", "per"; 1270 fsl,tuning-start-tap = <20>; 1271 fsl,tuning-step = <2>; 1272 bus-width = <4>; 1273 status = "disabled"; 1274 }; 1275 1276 usdhc2: mmc@30b50000 { 1277 compatible = "fsl,imx8mq-usdhc", 1278 "fsl,imx7d-usdhc"; 1279 reg = <0x30b50000 0x10000>; 1280 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1281 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1282 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1283 <&clk IMX8MQ_CLK_USDHC2_ROOT>; 1284 clock-names = "ipg", "ahb", "per"; 1285 fsl,tuning-start-tap = <20>; 1286 fsl,tuning-step = <2>; 1287 bus-width = <4>; 1288 status = "disabled"; 1289 }; 1290 1291 qspi0: spi@30bb0000 { 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; 1295 reg = <0x30bb0000 0x10000>, 1296 <0x08000000 0x10000000>; 1297 reg-names = "QuadSPI", "QuadSPI-memory"; 1298 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1299 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, 1300 <&clk IMX8MQ_CLK_QSPI_ROOT>; 1301 clock-names = "qspi_en", "qspi"; 1302 status = "disabled"; 1303 }; 1304 1305 sdma1: dma-controller@30bd0000 { 1306 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 1307 reg = <0x30bd0000 0x10000>; 1308 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, 1310 <&clk IMX8MQ_CLK_AHB>; 1311 clock-names = "ipg", "ahb"; 1312 #dma-cells = <3>; 1313 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1314 }; 1315 1316 fec1: ethernet@30be0000 { 1317 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1318 reg = <0x30be0000 0x10000>; 1319 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1323 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, 1324 <&clk IMX8MQ_CLK_ENET1_ROOT>, 1325 <&clk IMX8MQ_CLK_ENET_TIMER>, 1326 <&clk IMX8MQ_CLK_ENET_REF>, 1327 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1328 clock-names = "ipg", "ahb", "ptp", 1329 "enet_clk_ref", "enet_out"; 1330 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, 1331 <&clk IMX8MQ_CLK_ENET_TIMER>, 1332 <&clk IMX8MQ_CLK_ENET_REF>, 1333 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1334 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1335 <&clk IMX8MQ_SYS2_PLL_100M>, 1336 <&clk IMX8MQ_SYS2_PLL_125M>, 1337 <&clk IMX8MQ_SYS2_PLL_50M>; 1338 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1339 fsl,num-tx-queues = <3>; 1340 fsl,num-rx-queues = <3>; 1341 nvmem-cells = <&fec_mac_address>; 1342 nvmem-cell-names = "mac-address"; 1343 fsl,stop-mode = <&iomuxc_gpr 0x10 3>; 1344 status = "disabled"; 1345 }; 1346 }; 1347 1348 noc: interconnect@32700000 { 1349 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; 1350 reg = <0x32700000 0x100000>; 1351 clocks = <&clk IMX8MQ_CLK_NOC>; 1352 fsl,ddrc = <&ddrc>; 1353 #interconnect-cells = <1>; 1354 operating-points-v2 = <&noc_opp_table>; 1355 1356 noc_opp_table: opp-table { 1357 compatible = "operating-points-v2"; 1358 1359 opp-133M { 1360 opp-hz = /bits/ 64 <133333333>; 1361 }; 1362 1363 opp-400M { 1364 opp-hz = /bits/ 64 <400000000>; 1365 }; 1366 1367 opp-800M { 1368 opp-hz = /bits/ 64 <800000000>; 1369 }; 1370 }; 1371 }; 1372 1373 aips4: bus@32c00000 { /* AIPS4 */ 1374 compatible = "fsl,aips-bus", "simple-bus"; 1375 reg = <0x32c00000 0x400000>; 1376 #address-cells = <1>; 1377 #size-cells = <1>; 1378 ranges = <0x32c00000 0x32c00000 0x400000>; 1379 1380 irqsteer: interrupt-controller@32e2d000 { 1381 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; 1382 reg = <0x32e2d000 0x1000>; 1383 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 1385 clock-names = "ipg"; 1386 fsl,channel = <0>; 1387 fsl,num-irqs = <64>; 1388 interrupt-controller; 1389 #interrupt-cells = <1>; 1390 }; 1391 }; 1392 1393 gpu: gpu@38000000 { 1394 compatible = "vivante,gc"; 1395 reg = <0x38000000 0x40000>; 1396 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1397 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 1398 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 1399 <&clk IMX8MQ_CLK_GPU_AXI>, 1400 <&clk IMX8MQ_CLK_GPU_AHB>; 1401 clock-names = "core", "shader", "bus", "reg"; 1402 #cooling-cells = <2>; 1403 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, 1404 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, 1405 <&clk IMX8MQ_CLK_GPU_AXI>, 1406 <&clk IMX8MQ_CLK_GPU_AHB>, 1407 <&clk IMX8MQ_GPU_PLL_BYPASS>; 1408 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, 1409 <&clk IMX8MQ_GPU_PLL_OUT>, 1410 <&clk IMX8MQ_GPU_PLL_OUT>, 1411 <&clk IMX8MQ_GPU_PLL_OUT>, 1412 <&clk IMX8MQ_GPU_PLL>; 1413 assigned-clock-rates = <800000000>, <800000000>, 1414 <800000000>, <800000000>, <0>; 1415 power-domains = <&pgc_gpu>; 1416 }; 1417 1418 usb_dwc3_0: usb@38100000 { 1419 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1420 reg = <0x38100000 0x10000>; 1421 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, 1422 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1423 <&clk IMX8MQ_CLK_32K>; 1424 clock-names = "bus_early", "ref", "suspend"; 1425 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1426 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1427 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1428 <&clk IMX8MQ_SYS1_PLL_100M>; 1429 assigned-clock-rates = <500000000>, <100000000>; 1430 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1431 phys = <&usb3_phy0>, <&usb3_phy0>; 1432 phy-names = "usb2-phy", "usb3-phy"; 1433 power-domains = <&pgc_otg1>; 1434 usb3-resume-missing-cas; 1435 status = "disabled"; 1436 }; 1437 1438 usb3_phy0: usb-phy@381f0040 { 1439 compatible = "fsl,imx8mq-usb-phy"; 1440 reg = <0x381f0040 0x40>; 1441 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 1442 clock-names = "phy"; 1443 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1444 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1445 assigned-clock-rates = <100000000>; 1446 #phy-cells = <0>; 1447 status = "disabled"; 1448 }; 1449 1450 usb_dwc3_1: usb@38200000 { 1451 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1452 reg = <0x38200000 0x10000>; 1453 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, 1454 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1455 <&clk IMX8MQ_CLK_32K>; 1456 clock-names = "bus_early", "ref", "suspend"; 1457 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1458 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1459 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1460 <&clk IMX8MQ_SYS1_PLL_100M>; 1461 assigned-clock-rates = <500000000>, <100000000>; 1462 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1463 phys = <&usb3_phy1>, <&usb3_phy1>; 1464 phy-names = "usb2-phy", "usb3-phy"; 1465 power-domains = <&pgc_otg2>; 1466 usb3-resume-missing-cas; 1467 status = "disabled"; 1468 }; 1469 1470 usb3_phy1: usb-phy@382f0040 { 1471 compatible = "fsl,imx8mq-usb-phy"; 1472 reg = <0x382f0040 0x40>; 1473 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; 1474 clock-names = "phy"; 1475 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1476 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1477 assigned-clock-rates = <100000000>; 1478 #phy-cells = <0>; 1479 status = "disabled"; 1480 }; 1481 1482 vpu_g1: video-codec@38300000 { 1483 compatible = "nxp,imx8mq-vpu-g1"; 1484 reg = <0x38300000 0x10000>; 1485 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1486 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; 1487 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; 1488 }; 1489 1490 vpu_g2: video-codec@38310000 { 1491 compatible = "nxp,imx8mq-vpu-g2"; 1492 reg = <0x38310000 0x10000>; 1493 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1494 clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1495 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; 1496 }; 1497 1498 vpu_blk_ctrl: blk-ctrl@38320000 { 1499 compatible = "fsl,imx8mq-vpu-blk-ctrl"; 1500 reg = <0x38320000 0x100>; 1501 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; 1502 power-domain-names = "bus", "g1", "g2"; 1503 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 1504 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1505 clock-names = "g1", "g2"; 1506 #power-domain-cells = <1>; 1507 }; 1508 1509 pcie0: pcie@33800000 { 1510 compatible = "fsl,imx8mq-pcie"; 1511 reg = <0x33800000 0x400000>, 1512 <0x1ff00000 0x80000>; 1513 reg-names = "dbi", "config"; 1514 #address-cells = <3>; 1515 #size-cells = <2>; 1516 device_type = "pci"; 1517 bus-range = <0x00 0xff>; 1518 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1519 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1520 num-lanes = <1>; 1521 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1522 interrupt-names = "msi"; 1523 #interrupt-cells = <1>; 1524 interrupt-map-mask = <0 0 0 0x7>; 1525 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1526 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1527 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1528 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1529 fsl,max-link-speed = <2>; 1530 linux,pci-domain = <0>; 1531 power-domains = <&pgc_pcie>; 1532 resets = <&src IMX8MQ_RESET_PCIEPHY>, 1533 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1534 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1535 reset-names = "pciephy", "apps", "turnoff"; 1536 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, 1537 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1538 <&clk IMX8MQ_CLK_PCIE1_AUX>; 1539 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1540 <&clk IMX8MQ_SYS2_PLL_100M>, 1541 <&clk IMX8MQ_SYS1_PLL_80M>; 1542 assigned-clock-rates = <250000000>, <100000000>, 1543 <10000000>; 1544 status = "disabled"; 1545 }; 1546 1547 pcie1: pcie@33c00000 { 1548 compatible = "fsl,imx8mq-pcie"; 1549 reg = <0x33c00000 0x400000>, 1550 <0x27f00000 0x80000>; 1551 reg-names = "dbi", "config"; 1552 #address-cells = <3>; 1553 #size-cells = <2>; 1554 device_type = "pci"; 1555 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ 1556 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1557 num-lanes = <1>; 1558 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1559 interrupt-names = "msi"; 1560 #interrupt-cells = <1>; 1561 interrupt-map-mask = <0 0 0 0x7>; 1562 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1563 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1564 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1565 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1566 fsl,max-link-speed = <2>; 1567 linux,pci-domain = <1>; 1568 power-domains = <&pgc_pcie>; 1569 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1570 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1571 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1572 reset-names = "pciephy", "apps", "turnoff"; 1573 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, 1574 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1575 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1576 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1577 <&clk IMX8MQ_SYS2_PLL_100M>, 1578 <&clk IMX8MQ_SYS1_PLL_80M>; 1579 assigned-clock-rates = <250000000>, <100000000>, 1580 <10000000>; 1581 status = "disabled"; 1582 }; 1583 1584 gic: interrupt-controller@38800000 { 1585 compatible = "arm,gic-v3"; 1586 reg = <0x38800000 0x10000>, /* GIC Dist */ 1587 <0x38880000 0xc0000>, /* GICR */ 1588 <0x31000000 0x2000>, /* GICC */ 1589 <0x31010000 0x2000>, /* GICV */ 1590 <0x31020000 0x2000>; /* GICH */ 1591 #interrupt-cells = <3>; 1592 interrupt-controller; 1593 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1594 interrupt-parent = <&gic>; 1595 }; 1596 1597 ddrc: memory-controller@3d400000 { 1598 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; 1599 reg = <0x3d400000 0x400000>; 1600 clock-names = "core", "pll", "alt", "apb"; 1601 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, 1602 <&clk IMX8MQ_DRAM_PLL_OUT>, 1603 <&clk IMX8MQ_CLK_DRAM_ALT>, 1604 <&clk IMX8MQ_CLK_DRAM_APB>; 1605 status = "disabled"; 1606 }; 1607 1608 ddr-pmu@3d800000 { 1609 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1610 reg = <0x3d800000 0x400000>; 1611 interrupt-parent = <&gic>; 1612 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1613 }; 1614 }; 1615}; 1616