1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7#include <dt-bindings/clock/imx8mq-clock.h> 8#include <dt-bindings/power/imx8mq-power.h> 9#include <dt-bindings/reset/imx8mq-reset.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "dt-bindings/input/input.h" 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/interconnect/imx8mq.h> 15#include "imx8mq-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gpc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ethernet0 = &fec1; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 mmc0 = &usdhc1; 35 mmc1 = &usdhc2; 36 serial0 = &uart1; 37 serial1 = &uart2; 38 serial2 = &uart3; 39 serial3 = &uart4; 40 spi0 = &ecspi1; 41 spi1 = &ecspi2; 42 spi2 = &ecspi3; 43 }; 44 45 ckil: clock-ckil { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <32768>; 49 clock-output-names = "ckil"; 50 }; 51 52 osc_25m: clock-osc-25m { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 clock-output-names = "osc_25m"; 57 }; 58 59 osc_27m: clock-osc-27m { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <27000000>; 63 clock-output-names = "osc_27m"; 64 }; 65 66 hdmi_phy_27m: clock-hdmi-phy-27m { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <27000000>; 70 clock-output-names = "hdmi_phy_27m"; 71 }; 72 73 clk_ext1: clock-ext1 { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <133000000>; 77 clock-output-names = "clk_ext1"; 78 }; 79 80 clk_ext2: clock-ext2 { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <133000000>; 84 clock-output-names = "clk_ext2"; 85 }; 86 87 clk_ext3: clock-ext3 { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <133000000>; 91 clock-output-names = "clk_ext3"; 92 }; 93 94 clk_ext4: clock-ext4 { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <133000000>; 98 clock-output-names = "clk_ext4"; 99 }; 100 101 cpus { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 105 A53_0: cpu@0 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0>; 109 clock-latency = <61036>; /* two CLK32 periods */ 110 clocks = <&clk IMX8MQ_CLK_ARM>; 111 enable-method = "psci"; 112 i-cache-size = <0x8000>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <256>; 115 d-cache-size = <0x8000>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <128>; 118 next-level-cache = <&A53_L2>; 119 operating-points-v2 = <&a53_opp_table>; 120 #cooling-cells = <2>; 121 nvmem-cells = <&cpu_speed_grade>; 122 nvmem-cell-names = "speed_grade"; 123 }; 124 125 A53_1: cpu@1 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53"; 128 reg = <0x1>; 129 clock-latency = <61036>; /* two CLK32 periods */ 130 clocks = <&clk IMX8MQ_CLK_ARM>; 131 enable-method = "psci"; 132 i-cache-size = <0x8000>; 133 i-cache-line-size = <64>; 134 i-cache-sets = <256>; 135 d-cache-size = <0x8000>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <128>; 138 next-level-cache = <&A53_L2>; 139 operating-points-v2 = <&a53_opp_table>; 140 #cooling-cells = <2>; 141 }; 142 143 A53_2: cpu@2 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a53"; 146 reg = <0x2>; 147 clock-latency = <61036>; /* two CLK32 periods */ 148 clocks = <&clk IMX8MQ_CLK_ARM>; 149 enable-method = "psci"; 150 i-cache-size = <0x8000>; 151 i-cache-line-size = <64>; 152 i-cache-sets = <256>; 153 d-cache-size = <0x8000>; 154 d-cache-line-size = <64>; 155 d-cache-sets = <128>; 156 next-level-cache = <&A53_L2>; 157 operating-points-v2 = <&a53_opp_table>; 158 #cooling-cells = <2>; 159 }; 160 161 A53_3: cpu@3 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a53"; 164 reg = <0x3>; 165 clock-latency = <61036>; /* two CLK32 periods */ 166 clocks = <&clk IMX8MQ_CLK_ARM>; 167 enable-method = "psci"; 168 i-cache-size = <0x8000>; 169 i-cache-line-size = <64>; 170 i-cache-sets = <256>; 171 d-cache-size = <0x8000>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 next-level-cache = <&A53_L2>; 175 operating-points-v2 = <&a53_opp_table>; 176 #cooling-cells = <2>; 177 }; 178 179 A53_L2: l2-cache0 { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-unified; 183 cache-size = <0x100000>; 184 cache-line-size = <64>; 185 cache-sets = <1024>; 186 }; 187 }; 188 189 a53_opp_table: opp-table { 190 compatible = "operating-points-v2"; 191 opp-shared; 192 193 opp-800000000 { 194 opp-hz = /bits/ 64 <800000000>; 195 opp-microvolt = <900000>; 196 /* Industrial only */ 197 opp-supported-hw = <0xf>, <0x4>; 198 clock-latency-ns = <150000>; 199 opp-suspend; 200 }; 201 202 opp-1000000000 { 203 opp-hz = /bits/ 64 <1000000000>; 204 opp-microvolt = <900000>; 205 /* Consumer only */ 206 opp-supported-hw = <0xe>, <0x3>; 207 clock-latency-ns = <150000>; 208 opp-suspend; 209 }; 210 211 opp-1300000000 { 212 opp-hz = /bits/ 64 <1300000000>; 213 opp-microvolt = <1000000>; 214 opp-supported-hw = <0xc>, <0x4>; 215 clock-latency-ns = <150000>; 216 opp-suspend; 217 }; 218 219 opp-1500000000 { 220 opp-hz = /bits/ 64 <1500000000>; 221 opp-microvolt = <1000000>; 222 opp-supported-hw = <0x8>, <0x3>; 223 clock-latency-ns = <150000>; 224 opp-suspend; 225 }; 226 }; 227 228 pmu { 229 compatible = "arm,cortex-a53-pmu"; 230 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-parent = <&gic>; 232 }; 233 234 psci { 235 compatible = "arm,psci-1.0"; 236 method = "smc"; 237 }; 238 239 thermal-zones { 240 cpu_thermal: cpu-thermal { 241 polling-delay-passive = <250>; 242 polling-delay = <2000>; 243 thermal-sensors = <&tmu 0>; 244 245 trips { 246 cpu_alert: cpu-alert { 247 temperature = <80000>; 248 hysteresis = <2000>; 249 type = "passive"; 250 }; 251 252 cpu-crit { 253 temperature = <90000>; 254 hysteresis = <2000>; 255 type = "critical"; 256 }; 257 }; 258 259 cooling-maps { 260 map0 { 261 trip = <&cpu_alert>; 262 cooling-device = 263 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 264 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 265 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 266 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 267 }; 268 }; 269 }; 270 271 gpu-thermal { 272 polling-delay-passive = <250>; 273 polling-delay = <2000>; 274 thermal-sensors = <&tmu 1>; 275 276 trips { 277 gpu_alert: gpu-alert { 278 temperature = <80000>; 279 hysteresis = <2000>; 280 type = "passive"; 281 }; 282 283 gpu-crit { 284 temperature = <90000>; 285 hysteresis = <2000>; 286 type = "critical"; 287 }; 288 }; 289 290 cooling-maps { 291 map0 { 292 trip = <&gpu_alert>; 293 cooling-device = 294 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 295 }; 296 }; 297 }; 298 299 vpu-thermal { 300 polling-delay-passive = <250>; 301 polling-delay = <2000>; 302 thermal-sensors = <&tmu 2>; 303 304 trips { 305 vpu-crit { 306 temperature = <90000>; 307 hysteresis = <2000>; 308 type = "critical"; 309 }; 310 }; 311 }; 312 }; 313 314 timer { 315 compatible = "arm,armv8-timer"; 316 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 317 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 318 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 319 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 320 interrupt-parent = <&gic>; 321 arm,no-tick-in-suspend; 322 }; 323 324 soc: soc@0 { 325 compatible = "fsl,imx8mq-soc", "simple-bus"; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 ranges = <0x0 0x0 0x0 0x3e000000>; 329 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 330 nvmem-cells = <&imx8mq_uid>; 331 nvmem-cell-names = "soc_unique_id"; 332 333 aips1: bus@30000000 { /* AIPS1 */ 334 compatible = "fsl,aips-bus", "simple-bus"; 335 reg = <0x30000000 0x400000>; 336 #address-cells = <1>; 337 #size-cells = <1>; 338 ranges = <0x30000000 0x30000000 0x400000>; 339 340 sai1: sai@30010000 { 341 #sound-dai-cells = <0>; 342 compatible = "fsl,imx8mq-sai"; 343 reg = <0x30010000 0x10000>; 344 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, 346 <&clk IMX8MQ_CLK_SAI1_ROOT>, 347 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 348 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 349 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 }; 353 354 sai6: sai@30030000 { 355 #sound-dai-cells = <0>; 356 compatible = "fsl,imx8mq-sai"; 357 reg = <0x30030000 0x10000>; 358 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, 360 <&clk IMX8MQ_CLK_SAI6_ROOT>, 361 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 362 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 363 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; 364 dma-names = "rx", "tx"; 365 status = "disabled"; 366 }; 367 368 sai5: sai@30040000 { 369 #sound-dai-cells = <0>; 370 compatible = "fsl,imx8mq-sai"; 371 reg = <0x30040000 0x10000>; 372 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, 374 <&clk IMX8MQ_CLK_SAI5_ROOT>, 375 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 376 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 377 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; 378 dma-names = "rx", "tx"; 379 status = "disabled"; 380 }; 381 382 sai4: sai@30050000 { 383 #sound-dai-cells = <0>; 384 compatible = "fsl,imx8mq-sai"; 385 reg = <0x30050000 0x10000>; 386 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, 388 <&clk IMX8MQ_CLK_SAI4_ROOT>, 389 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 390 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 391 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; 392 dma-names = "rx", "tx"; 393 status = "disabled"; 394 }; 395 396 gpio1: gpio@30200000 { 397 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 398 reg = <0x30200000 0x10000>; 399 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 gpio-ranges = <&iomuxc 0 10 30>; 407 }; 408 409 gpio2: gpio@30210000 { 410 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 411 reg = <0x30210000 0x10000>; 412 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; 415 gpio-controller; 416 #gpio-cells = <2>; 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 gpio-ranges = <&iomuxc 0 40 21>; 420 }; 421 422 gpio3: gpio@30220000 { 423 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 424 reg = <0x30220000 0x10000>; 425 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; 428 gpio-controller; 429 #gpio-cells = <2>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 gpio-ranges = <&iomuxc 0 61 26>; 433 }; 434 435 gpio4: gpio@30230000 { 436 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 437 reg = <0x30230000 0x10000>; 438 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 gpio-ranges = <&iomuxc 0 87 32>; 446 }; 447 448 gpio5: gpio@30240000 { 449 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 450 reg = <0x30240000 0x10000>; 451 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; 454 gpio-controller; 455 #gpio-cells = <2>; 456 interrupt-controller; 457 #interrupt-cells = <2>; 458 gpio-ranges = <&iomuxc 0 119 30>; 459 }; 460 461 tmu: tmu@30260000 { 462 compatible = "fsl,imx8mq-tmu"; 463 reg = <0x30260000 0x10000>; 464 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; 466 little-endian; 467 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 468 fsl,tmu-calibration = <0x00000000 0x00000023>, 469 <0x00000001 0x00000029>, 470 <0x00000002 0x0000002f>, 471 <0x00000003 0x00000035>, 472 <0x00000004 0x0000003d>, 473 <0x00000005 0x00000043>, 474 <0x00000006 0x0000004b>, 475 <0x00000007 0x00000051>, 476 <0x00000008 0x00000057>, 477 <0x00000009 0x0000005f>, 478 <0x0000000a 0x00000067>, 479 <0x0000000b 0x0000006f>, 480 481 <0x00010000 0x0000001b>, 482 <0x00010001 0x00000023>, 483 <0x00010002 0x0000002b>, 484 <0x00010003 0x00000033>, 485 <0x00010004 0x0000003b>, 486 <0x00010005 0x00000043>, 487 <0x00010006 0x0000004b>, 488 <0x00010007 0x00000055>, 489 <0x00010008 0x0000005d>, 490 <0x00010009 0x00000067>, 491 <0x0001000a 0x00000070>, 492 493 <0x00020000 0x00000017>, 494 <0x00020001 0x00000023>, 495 <0x00020002 0x0000002d>, 496 <0x00020003 0x00000037>, 497 <0x00020004 0x00000041>, 498 <0x00020005 0x0000004b>, 499 <0x00020006 0x00000057>, 500 <0x00020007 0x00000063>, 501 <0x00020008 0x0000006f>, 502 503 <0x00030000 0x00000015>, 504 <0x00030001 0x00000021>, 505 <0x00030002 0x0000002d>, 506 <0x00030003 0x00000039>, 507 <0x00030004 0x00000045>, 508 <0x00030005 0x00000053>, 509 <0x00030006 0x0000005f>, 510 <0x00030007 0x00000071>; 511 #thermal-sensor-cells = <1>; 512 }; 513 514 wdog1: watchdog@30280000 { 515 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 516 reg = <0x30280000 0x10000>; 517 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; 519 status = "disabled"; 520 }; 521 522 wdog2: watchdog@30290000 { 523 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 524 reg = <0x30290000 0x10000>; 525 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; 527 status = "disabled"; 528 }; 529 530 wdog3: watchdog@302a0000 { 531 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 532 reg = <0x302a0000 0x10000>; 533 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; 535 status = "disabled"; 536 }; 537 538 sdma2: dma-controller@302c0000 { 539 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 540 reg = <0x302c0000 0x10000>; 541 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, 543 <&clk IMX8MQ_CLK_SDMA2_ROOT>; 544 clock-names = "ipg", "ahb"; 545 #dma-cells = <3>; 546 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 547 }; 548 549 lcdif: lcd-controller@30320000 { 550 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; 551 reg = <0x30320000 0x10000>; 552 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 554 clock-names = "pix"; 555 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 556 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 557 <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 558 <&clk IMX8MQ_VIDEO_PLL1>; 559 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 560 <&clk IMX8MQ_VIDEO_PLL1>, 561 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 562 assigned-clock-rates = <0>, <0>, <0>, <594000000>; 563 status = "disabled"; 564 565 port { 566 lcdif_mipi_dsi: endpoint { 567 remote-endpoint = <&mipi_dsi_lcdif_in>; 568 }; 569 }; 570 }; 571 572 iomuxc: pinctrl@30330000 { 573 compatible = "fsl,imx8mq-iomuxc"; 574 reg = <0x30330000 0x10000>; 575 }; 576 577 iomuxc_gpr: syscon@30340000 { 578 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", 579 "syscon", "simple-mfd"; 580 reg = <0x30340000 0x10000>; 581 582 mux: mux-controller { 583 compatible = "mmio-mux"; 584 #mux-control-cells = <1>; 585 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ 586 }; 587 }; 588 589 ocotp: efuse@30350000 { 590 compatible = "fsl,imx8mq-ocotp", "syscon"; 591 reg = <0x30350000 0x10000>; 592 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 596 imx8mq_uid: soc-uid@410 { 597 reg = <0x4 0x8>; 598 }; 599 600 cpu_speed_grade: speed-grade@10 { 601 reg = <0x10 4>; 602 }; 603 604 fec_mac_address: mac-address@90 { 605 reg = <0x90 6>; 606 }; 607 }; 608 609 anatop: clock-controller@30360000 { 610 compatible = "fsl,imx8mq-anatop"; 611 reg = <0x30360000 0x10000>; 612 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 613 #clock-cells = <1>; 614 }; 615 616 snvs: snvs@30370000 { 617 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 618 reg = <0x30370000 0x10000>; 619 620 snvs_rtc: snvs-rtc-lp{ 621 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 622 regmap =<&snvs>; 623 offset = <0x34>; 624 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 627 clock-names = "snvs-rtc"; 628 }; 629 630 snvs_pwrkey: snvs-powerkey { 631 compatible = "fsl,sec-v4.0-pwrkey"; 632 regmap = <&snvs>; 633 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 635 clock-names = "snvs-pwrkey"; 636 linux,keycode = <KEY_POWER>; 637 wakeup-source; 638 status = "disabled"; 639 }; 640 }; 641 642 clk: clock-controller@30380000 { 643 compatible = "fsl,imx8mq-ccm"; 644 reg = <0x30380000 0x10000>; 645 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 647 #clock-cells = <1>; 648 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, 649 <&clk_ext1>, <&clk_ext2>, 650 <&clk_ext3>, <&clk_ext4>; 651 clock-names = "ckil", "osc_25m", "osc_27m", 652 "clk_ext1", "clk_ext2", 653 "clk_ext3", "clk_ext4"; 654 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, 655 <&clk IMX8MQ_CLK_A53_CORE>, 656 <&clk IMX8MQ_CLK_NOC>, 657 <&clk IMX8MQ_CLK_AUDIO_AHB>, 658 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, 659 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, 660 <&clk IMX8MQ_AUDIO_PLL1>, 661 <&clk IMX8MQ_AUDIO_PLL2>; 662 assigned-clock-rates = <0>, <0>, 663 <800000000>, 664 <0>, 665 <0>, 666 <0>, 667 <786432000>, 668 <722534400>; 669 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, 670 <&clk IMX8MQ_ARM_PLL_OUT>, 671 <0>, 672 <&clk IMX8MQ_SYS2_PLL_500M>, 673 <&clk IMX8MQ_AUDIO_PLL1>, 674 <&clk IMX8MQ_AUDIO_PLL2>; 675 }; 676 677 src: reset-controller@30390000 { 678 compatible = "fsl,imx8mq-src", "syscon"; 679 reg = <0x30390000 0x10000>; 680 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 681 #reset-cells = <1>; 682 }; 683 684 gpc: gpc@303a0000 { 685 compatible = "fsl,imx8mq-gpc"; 686 reg = <0x303a0000 0x10000>; 687 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 688 interrupt-parent = <&gic>; 689 interrupt-controller; 690 #interrupt-cells = <3>; 691 692 pgc { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 696 pgc_mipi: power-domain@0 { 697 #power-domain-cells = <0>; 698 reg = <IMX8M_POWER_DOMAIN_MIPI>; 699 }; 700 701 /* 702 * As per comment in ATF source code: 703 * 704 * PCIE1 and PCIE2 share the 705 * same reset signal, if we 706 * power down PCIE2, PCIE1 707 * will be held in reset too. 708 * 709 * So instead of creating two 710 * separate power domains for 711 * PCIE1 and PCIE2 we create a 712 * link between both and use 713 * it as a shared PCIE power 714 * domain. 715 */ 716 pgc_pcie: power-domain@1 { 717 #power-domain-cells = <0>; 718 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 719 power-domains = <&pgc_pcie2>; 720 }; 721 722 pgc_otg1: power-domain@2 { 723 #power-domain-cells = <0>; 724 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; 725 }; 726 727 pgc_otg2: power-domain@3 { 728 #power-domain-cells = <0>; 729 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; 730 }; 731 732 pgc_ddr1: power-domain@4 { 733 #power-domain-cells = <0>; 734 reg = <IMX8M_POWER_DOMAIN_DDR1>; 735 }; 736 737 pgc_gpu: power-domain@5 { 738 #power-domain-cells = <0>; 739 reg = <IMX8M_POWER_DOMAIN_GPU>; 740 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 741 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 742 <&clk IMX8MQ_CLK_GPU_AXI>, 743 <&clk IMX8MQ_CLK_GPU_AHB>; 744 }; 745 746 pgc_vpu: power-domain@6 { 747 #power-domain-cells = <0>; 748 reg = <IMX8M_POWER_DOMAIN_VPU>; 749 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, 750 <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 751 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 752 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, 753 <&clk IMX8MQ_CLK_VPU_G2>, 754 <&clk IMX8MQ_CLK_VPU_BUS>, 755 <&clk IMX8MQ_VPU_PLL_BYPASS>; 756 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, 757 <&clk IMX8MQ_VPU_PLL_OUT>, 758 <&clk IMX8MQ_SYS1_PLL_800M>, 759 <&clk IMX8MQ_VPU_PLL>; 760 assigned-clock-rates = <600000000>, 761 <600000000>, 762 <800000000>, 763 <0>; 764 }; 765 766 pgc_disp: power-domain@7 { 767 #power-domain-cells = <0>; 768 reg = <IMX8M_POWER_DOMAIN_DISP>; 769 }; 770 771 pgc_mipi_csi1: power-domain@8 { 772 #power-domain-cells = <0>; 773 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; 774 }; 775 776 pgc_mipi_csi2: power-domain@9 { 777 #power-domain-cells = <0>; 778 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; 779 }; 780 781 pgc_pcie2: power-domain@a { 782 #power-domain-cells = <0>; 783 reg = <IMX8M_POWER_DOMAIN_PCIE2>; 784 }; 785 }; 786 }; 787 }; 788 789 aips2: bus@30400000 { /* AIPS2 */ 790 compatible = "fsl,aips-bus", "simple-bus"; 791 reg = <0x30400000 0x400000>; 792 #address-cells = <1>; 793 #size-cells = <1>; 794 ranges = <0x30400000 0x30400000 0x400000>; 795 796 pwm1: pwm@30660000 { 797 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 798 reg = <0x30660000 0x10000>; 799 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, 801 <&clk IMX8MQ_CLK_PWM1_ROOT>; 802 clock-names = "ipg", "per"; 803 #pwm-cells = <3>; 804 status = "disabled"; 805 }; 806 807 pwm2: pwm@30670000 { 808 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 809 reg = <0x30670000 0x10000>; 810 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, 812 <&clk IMX8MQ_CLK_PWM2_ROOT>; 813 clock-names = "ipg", "per"; 814 #pwm-cells = <3>; 815 status = "disabled"; 816 }; 817 818 pwm3: pwm@30680000 { 819 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 820 reg = <0x30680000 0x10000>; 821 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, 823 <&clk IMX8MQ_CLK_PWM3_ROOT>; 824 clock-names = "ipg", "per"; 825 #pwm-cells = <3>; 826 status = "disabled"; 827 }; 828 829 pwm4: pwm@30690000 { 830 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 831 reg = <0x30690000 0x10000>; 832 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, 834 <&clk IMX8MQ_CLK_PWM4_ROOT>; 835 clock-names = "ipg", "per"; 836 #pwm-cells = <3>; 837 status = "disabled"; 838 }; 839 840 system_counter: timer@306a0000 { 841 compatible = "nxp,sysctr-timer"; 842 reg = <0x306a0000 0x20000>; 843 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&osc_25m>; 845 clock-names = "per"; 846 }; 847 }; 848 849 aips3: bus@30800000 { /* AIPS3 */ 850 compatible = "fsl,aips-bus", "simple-bus"; 851 reg = <0x30800000 0x400000>; 852 #address-cells = <1>; 853 #size-cells = <1>; 854 ranges = <0x30800000 0x30800000 0x400000>, 855 <0x08000000 0x08000000 0x10000000>; 856 857 spdif1: spdif@30810000 { 858 compatible = "fsl,imx35-spdif"; 859 reg = <0x30810000 0x10000>; 860 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 862 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 863 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ 864 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 865 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 866 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 867 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 868 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 869 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 870 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 871 clock-names = "core", "rxtx0", 872 "rxtx1", "rxtx2", 873 "rxtx3", "rxtx4", 874 "rxtx5", "rxtx6", 875 "rxtx7", "spba"; 876 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; 877 dma-names = "rx", "tx"; 878 status = "disabled"; 879 }; 880 881 ecspi1: spi@30820000 { 882 #address-cells = <1>; 883 #size-cells = <0>; 884 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 885 reg = <0x30820000 0x10000>; 886 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, 888 <&clk IMX8MQ_CLK_ECSPI1_ROOT>; 889 clock-names = "ipg", "per"; 890 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 891 dma-names = "rx", "tx"; 892 status = "disabled"; 893 }; 894 895 ecspi2: spi@30830000 { 896 #address-cells = <1>; 897 #size-cells = <0>; 898 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 899 reg = <0x30830000 0x10000>; 900 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, 902 <&clk IMX8MQ_CLK_ECSPI2_ROOT>; 903 clock-names = "ipg", "per"; 904 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 905 dma-names = "rx", "tx"; 906 status = "disabled"; 907 }; 908 909 ecspi3: spi@30840000 { 910 #address-cells = <1>; 911 #size-cells = <0>; 912 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 913 reg = <0x30840000 0x10000>; 914 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, 916 <&clk IMX8MQ_CLK_ECSPI3_ROOT>; 917 clock-names = "ipg", "per"; 918 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 919 dma-names = "rx", "tx"; 920 status = "disabled"; 921 }; 922 923 uart1: serial@30860000 { 924 compatible = "fsl,imx8mq-uart", 925 "fsl,imx6q-uart"; 926 reg = <0x30860000 0x10000>; 927 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, 929 <&clk IMX8MQ_CLK_UART1_ROOT>; 930 clock-names = "ipg", "per"; 931 status = "disabled"; 932 }; 933 934 uart3: serial@30880000 { 935 compatible = "fsl,imx8mq-uart", 936 "fsl,imx6q-uart"; 937 reg = <0x30880000 0x10000>; 938 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, 940 <&clk IMX8MQ_CLK_UART3_ROOT>; 941 clock-names = "ipg", "per"; 942 status = "disabled"; 943 }; 944 945 uart2: serial@30890000 { 946 compatible = "fsl,imx8mq-uart", 947 "fsl,imx6q-uart"; 948 reg = <0x30890000 0x10000>; 949 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, 951 <&clk IMX8MQ_CLK_UART2_ROOT>; 952 clock-names = "ipg", "per"; 953 status = "disabled"; 954 }; 955 956 spdif2: spdif@308a0000 { 957 compatible = "fsl,imx35-spdif"; 958 reg = <0x308a0000 0x10000>; 959 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 961 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 962 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ 963 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 964 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 965 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 966 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 967 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 968 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 969 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 970 clock-names = "core", "rxtx0", 971 "rxtx1", "rxtx2", 972 "rxtx3", "rxtx4", 973 "rxtx5", "rxtx6", 974 "rxtx7", "spba"; 975 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; 976 dma-names = "rx", "tx"; 977 status = "disabled"; 978 }; 979 980 sai2: sai@308b0000 { 981 #sound-dai-cells = <0>; 982 compatible = "fsl,imx8mq-sai"; 983 reg = <0x308b0000 0x10000>; 984 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, 986 <&clk IMX8MQ_CLK_SAI2_ROOT>, 987 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 988 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 989 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; 990 dma-names = "rx", "tx"; 991 status = "disabled"; 992 }; 993 994 sai3: sai@308c0000 { 995 #sound-dai-cells = <0>; 996 compatible = "fsl,imx8mq-sai"; 997 reg = <0x308c0000 0x10000>; 998 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, 1000 <&clk IMX8MQ_CLK_SAI3_ROOT>, 1001 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 1002 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1003 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; 1004 dma-names = "rx", "tx"; 1005 status = "disabled"; 1006 }; 1007 1008 crypto: crypto@30900000 { 1009 compatible = "fsl,sec-v4.0"; 1010 #address-cells = <1>; 1011 #size-cells = <1>; 1012 reg = <0x30900000 0x40000>; 1013 ranges = <0 0x30900000 0x40000>; 1014 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&clk IMX8MQ_CLK_AHB>, 1016 <&clk IMX8MQ_CLK_IPG_ROOT>; 1017 clock-names = "aclk", "ipg"; 1018 1019 sec_jr0: jr@1000 { 1020 compatible = "fsl,sec-v4.0-job-ring"; 1021 reg = <0x1000 0x1000>; 1022 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1023 status = "disabled"; 1024 }; 1025 1026 sec_jr1: jr@2000 { 1027 compatible = "fsl,sec-v4.0-job-ring"; 1028 reg = <0x2000 0x1000>; 1029 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1030 }; 1031 1032 sec_jr2: jr@3000 { 1033 compatible = "fsl,sec-v4.0-job-ring"; 1034 reg = <0x3000 0x1000>; 1035 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1036 }; 1037 }; 1038 1039 mipi_dsi: mipi-dsi@30a00000 { 1040 compatible = "fsl,imx8mq-nwl-dsi"; 1041 reg = <0x30a00000 0x300>; 1042 clocks = <&clk IMX8MQ_CLK_DSI_CORE>, 1043 <&clk IMX8MQ_CLK_DSI_AHB>, 1044 <&clk IMX8MQ_CLK_DSI_IPG_DIV>, 1045 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1046 <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 1047 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; 1048 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, 1049 <&clk IMX8MQ_CLK_DSI_CORE>, 1050 <&clk IMX8MQ_CLK_DSI_IPG_DIV>; 1051 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, 1052 <&clk IMX8MQ_SYS1_PLL_266M>; 1053 assigned-clock-rates = <80000000>, <266000000>, <20000000>; 1054 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1055 mux-controls = <&mux 0>; 1056 power-domains = <&pgc_mipi>; 1057 phys = <&dphy>; 1058 phy-names = "dphy"; 1059 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, 1060 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, 1061 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, 1062 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; 1063 reset-names = "byte", "dpi", "esc", "pclk"; 1064 status = "disabled"; 1065 1066 ports { 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 1070 port@0 { 1071 reg = <0>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 mipi_dsi_lcdif_in: endpoint@0 { 1075 reg = <0>; 1076 remote-endpoint = <&lcdif_mipi_dsi>; 1077 }; 1078 }; 1079 }; 1080 }; 1081 1082 dphy: dphy@30a00300 { 1083 compatible = "fsl,imx8mq-mipi-dphy"; 1084 reg = <0x30a00300 0x100>; 1085 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 1086 clock-names = "phy_ref"; 1087 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 1088 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 1089 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1090 <&clk IMX8MQ_VIDEO_PLL1>; 1091 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 1092 <&clk IMX8MQ_VIDEO_PLL1>, 1093 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 1094 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; 1095 #phy-cells = <0>; 1096 power-domains = <&pgc_mipi>; 1097 status = "disabled"; 1098 }; 1099 1100 i2c1: i2c@30a20000 { 1101 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1102 reg = <0x30a20000 0x10000>; 1103 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 i2c2: i2c@30a30000 { 1111 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1112 reg = <0x30a30000 0x10000>; 1113 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 status = "disabled"; 1118 }; 1119 1120 i2c3: i2c@30a40000 { 1121 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1122 reg = <0x30a40000 0x10000>; 1123 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 i2c4: i2c@30a50000 { 1131 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1132 reg = <0x30a50000 0x10000>; 1133 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 uart4: serial@30a60000 { 1141 compatible = "fsl,imx8mq-uart", 1142 "fsl,imx6q-uart"; 1143 reg = <0x30a60000 0x10000>; 1144 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, 1146 <&clk IMX8MQ_CLK_UART4_ROOT>; 1147 clock-names = "ipg", "per"; 1148 status = "disabled"; 1149 }; 1150 1151 mipi_csi1: csi@30a70000 { 1152 compatible = "fsl,imx8mq-mipi-csi2"; 1153 reg = <0x30a70000 0x1000>; 1154 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1155 <&clk IMX8MQ_CLK_CSI1_ESC>, 1156 <&clk IMX8MQ_CLK_CSI1_PHY_REF>; 1157 clock-names = "core", "esc", "ui"; 1158 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1159 <&clk IMX8MQ_CLK_CSI1_PHY_REF>, 1160 <&clk IMX8MQ_CLK_CSI1_ESC>; 1161 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1162 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1163 <&clk IMX8MQ_SYS2_PLL_1000M>, 1164 <&clk IMX8MQ_SYS1_PLL_800M>; 1165 power-domains = <&pgc_mipi_csi1>; 1166 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, 1167 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, 1168 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; 1169 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; 1170 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; 1171 interconnect-names = "dram"; 1172 status = "disabled"; 1173 1174 ports { 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 1178 port@1 { 1179 reg = <1>; 1180 1181 csi1_mipi_ep: endpoint { 1182 remote-endpoint = <&csi1_ep>; 1183 }; 1184 }; 1185 }; 1186 }; 1187 1188 csi1: csi@30a90000 { 1189 compatible = "fsl,imx8mq-csi"; 1190 reg = <0x30a90000 0x10000>; 1191 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1192 clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; 1193 clock-names = "mclk"; 1194 status = "disabled"; 1195 1196 port { 1197 csi1_ep: endpoint { 1198 remote-endpoint = <&csi1_mipi_ep>; 1199 }; 1200 }; 1201 }; 1202 1203 mipi_csi2: csi@30b60000 { 1204 compatible = "fsl,imx8mq-mipi-csi2"; 1205 reg = <0x30b60000 0x1000>; 1206 clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1207 <&clk IMX8MQ_CLK_CSI2_ESC>, 1208 <&clk IMX8MQ_CLK_CSI2_PHY_REF>; 1209 clock-names = "core", "esc", "ui"; 1210 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1211 <&clk IMX8MQ_CLK_CSI2_PHY_REF>, 1212 <&clk IMX8MQ_CLK_CSI2_ESC>; 1213 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1214 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1215 <&clk IMX8MQ_SYS2_PLL_1000M>, 1216 <&clk IMX8MQ_SYS1_PLL_800M>; 1217 power-domains = <&pgc_mipi_csi2>; 1218 resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, 1219 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, 1220 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; 1221 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; 1222 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; 1223 interconnect-names = "dram"; 1224 status = "disabled"; 1225 1226 ports { 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 1230 port@1 { 1231 reg = <1>; 1232 1233 csi2_mipi_ep: endpoint { 1234 remote-endpoint = <&csi2_ep>; 1235 }; 1236 }; 1237 }; 1238 }; 1239 1240 csi2: csi@30b80000 { 1241 compatible = "fsl,imx8mq-csi"; 1242 reg = <0x30b80000 0x10000>; 1243 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1244 clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; 1245 clock-names = "mclk"; 1246 status = "disabled"; 1247 1248 port { 1249 csi2_ep: endpoint { 1250 remote-endpoint = <&csi2_mipi_ep>; 1251 }; 1252 }; 1253 }; 1254 1255 mu: mailbox@30aa0000 { 1256 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; 1257 reg = <0x30aa0000 0x10000>; 1258 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&clk IMX8MQ_CLK_MU_ROOT>; 1260 #mbox-cells = <2>; 1261 }; 1262 1263 usdhc1: mmc@30b40000 { 1264 compatible = "fsl,imx8mq-usdhc", 1265 "fsl,imx7d-usdhc"; 1266 reg = <0x30b40000 0x10000>; 1267 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1269 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1270 <&clk IMX8MQ_CLK_USDHC1_ROOT>; 1271 clock-names = "ipg", "ahb", "per"; 1272 fsl,tuning-start-tap = <20>; 1273 fsl,tuning-step = <2>; 1274 bus-width = <4>; 1275 status = "disabled"; 1276 }; 1277 1278 usdhc2: mmc@30b50000 { 1279 compatible = "fsl,imx8mq-usdhc", 1280 "fsl,imx7d-usdhc"; 1281 reg = <0x30b50000 0x10000>; 1282 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1284 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1285 <&clk IMX8MQ_CLK_USDHC2_ROOT>; 1286 clock-names = "ipg", "ahb", "per"; 1287 fsl,tuning-start-tap = <20>; 1288 fsl,tuning-step = <2>; 1289 bus-width = <4>; 1290 status = "disabled"; 1291 }; 1292 1293 qspi0: spi@30bb0000 { 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; 1297 reg = <0x30bb0000 0x10000>, 1298 <0x08000000 0x10000000>; 1299 reg-names = "QuadSPI", "QuadSPI-memory"; 1300 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1301 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, 1302 <&clk IMX8MQ_CLK_QSPI_ROOT>; 1303 clock-names = "qspi_en", "qspi"; 1304 status = "disabled"; 1305 }; 1306 1307 sdma1: dma-controller@30bd0000 { 1308 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 1309 reg = <0x30bd0000 0x10000>; 1310 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1311 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, 1312 <&clk IMX8MQ_CLK_AHB>; 1313 clock-names = "ipg", "ahb"; 1314 #dma-cells = <3>; 1315 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1316 }; 1317 1318 fec1: ethernet@30be0000 { 1319 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1320 reg = <0x30be0000 0x10000>; 1321 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, 1326 <&clk IMX8MQ_CLK_ENET1_ROOT>, 1327 <&clk IMX8MQ_CLK_ENET_TIMER>, 1328 <&clk IMX8MQ_CLK_ENET_REF>, 1329 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1330 clock-names = "ipg", "ahb", "ptp", 1331 "enet_clk_ref", "enet_out"; 1332 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, 1333 <&clk IMX8MQ_CLK_ENET_TIMER>, 1334 <&clk IMX8MQ_CLK_ENET_REF>, 1335 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1336 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1337 <&clk IMX8MQ_SYS2_PLL_100M>, 1338 <&clk IMX8MQ_SYS2_PLL_125M>, 1339 <&clk IMX8MQ_SYS2_PLL_50M>; 1340 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1341 fsl,num-tx-queues = <3>; 1342 fsl,num-rx-queues = <3>; 1343 nvmem-cells = <&fec_mac_address>; 1344 nvmem-cell-names = "mac-address"; 1345 fsl,stop-mode = <&iomuxc_gpr 0x10 3>; 1346 status = "disabled"; 1347 }; 1348 }; 1349 1350 noc: interconnect@32700000 { 1351 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; 1352 reg = <0x32700000 0x100000>; 1353 clocks = <&clk IMX8MQ_CLK_NOC>; 1354 fsl,ddrc = <&ddrc>; 1355 #interconnect-cells = <1>; 1356 operating-points-v2 = <&noc_opp_table>; 1357 1358 noc_opp_table: opp-table { 1359 compatible = "operating-points-v2"; 1360 1361 opp-133000000 { 1362 opp-hz = /bits/ 64 <133333333>; 1363 }; 1364 1365 opp-400000000 { 1366 opp-hz = /bits/ 64 <400000000>; 1367 }; 1368 1369 opp-800000000 { 1370 opp-hz = /bits/ 64 <800000000>; 1371 }; 1372 }; 1373 }; 1374 1375 aips4: bus@32c00000 { /* AIPS4 */ 1376 compatible = "fsl,aips-bus", "simple-bus"; 1377 reg = <0x32c00000 0x400000>; 1378 #address-cells = <1>; 1379 #size-cells = <1>; 1380 ranges = <0x32c00000 0x32c00000 0x400000>; 1381 1382 irqsteer: interrupt-controller@32e2d000 { 1383 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; 1384 reg = <0x32e2d000 0x1000>; 1385 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1386 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 1387 clock-names = "ipg"; 1388 fsl,channel = <0>; 1389 fsl,num-irqs = <64>; 1390 interrupt-controller; 1391 #interrupt-cells = <1>; 1392 }; 1393 }; 1394 1395 gpu: gpu@38000000 { 1396 compatible = "vivante,gc"; 1397 reg = <0x38000000 0x40000>; 1398 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1399 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 1400 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 1401 <&clk IMX8MQ_CLK_GPU_AXI>, 1402 <&clk IMX8MQ_CLK_GPU_AHB>; 1403 clock-names = "core", "shader", "bus", "reg"; 1404 #cooling-cells = <2>; 1405 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, 1406 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, 1407 <&clk IMX8MQ_CLK_GPU_AXI>, 1408 <&clk IMX8MQ_CLK_GPU_AHB>, 1409 <&clk IMX8MQ_GPU_PLL_BYPASS>; 1410 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, 1411 <&clk IMX8MQ_GPU_PLL_OUT>, 1412 <&clk IMX8MQ_GPU_PLL_OUT>, 1413 <&clk IMX8MQ_GPU_PLL_OUT>, 1414 <&clk IMX8MQ_GPU_PLL>; 1415 assigned-clock-rates = <800000000>, <800000000>, 1416 <800000000>, <800000000>, <0>; 1417 power-domains = <&pgc_gpu>; 1418 }; 1419 1420 usb_dwc3_0: usb@38100000 { 1421 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1422 reg = <0x38100000 0x10000>; 1423 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, 1424 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1425 <&clk IMX8MQ_CLK_32K>; 1426 clock-names = "bus_early", "ref", "suspend"; 1427 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1428 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1429 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1430 <&clk IMX8MQ_SYS1_PLL_100M>; 1431 assigned-clock-rates = <500000000>, <100000000>; 1432 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1433 phys = <&usb3_phy0>, <&usb3_phy0>; 1434 phy-names = "usb2-phy", "usb3-phy"; 1435 power-domains = <&pgc_otg1>; 1436 usb3-resume-missing-cas; 1437 status = "disabled"; 1438 }; 1439 1440 usb3_phy0: usb-phy@381f0040 { 1441 compatible = "fsl,imx8mq-usb-phy"; 1442 reg = <0x381f0040 0x40>; 1443 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 1444 clock-names = "phy"; 1445 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1446 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1447 assigned-clock-rates = <100000000>; 1448 #phy-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 1452 usb_dwc3_1: usb@38200000 { 1453 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1454 reg = <0x38200000 0x10000>; 1455 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, 1456 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1457 <&clk IMX8MQ_CLK_32K>; 1458 clock-names = "bus_early", "ref", "suspend"; 1459 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1460 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1461 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1462 <&clk IMX8MQ_SYS1_PLL_100M>; 1463 assigned-clock-rates = <500000000>, <100000000>; 1464 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1465 phys = <&usb3_phy1>, <&usb3_phy1>; 1466 phy-names = "usb2-phy", "usb3-phy"; 1467 power-domains = <&pgc_otg2>; 1468 usb3-resume-missing-cas; 1469 status = "disabled"; 1470 }; 1471 1472 usb3_phy1: usb-phy@382f0040 { 1473 compatible = "fsl,imx8mq-usb-phy"; 1474 reg = <0x382f0040 0x40>; 1475 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; 1476 clock-names = "phy"; 1477 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1478 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1479 assigned-clock-rates = <100000000>; 1480 #phy-cells = <0>; 1481 status = "disabled"; 1482 }; 1483 1484 vpu_g1: video-codec@38300000 { 1485 compatible = "nxp,imx8mq-vpu-g1"; 1486 reg = <0x38300000 0x10000>; 1487 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1488 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; 1489 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; 1490 }; 1491 1492 vpu_g2: video-codec@38310000 { 1493 compatible = "nxp,imx8mq-vpu-g2"; 1494 reg = <0x38310000 0x10000>; 1495 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1496 clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1497 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; 1498 }; 1499 1500 vpu_blk_ctrl: blk-ctrl@38320000 { 1501 compatible = "fsl,imx8mq-vpu-blk-ctrl"; 1502 reg = <0x38320000 0x100>; 1503 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; 1504 power-domain-names = "bus", "g1", "g2"; 1505 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 1506 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1507 clock-names = "g1", "g2"; 1508 #power-domain-cells = <1>; 1509 }; 1510 1511 pcie0: pcie@33800000 { 1512 compatible = "fsl,imx8mq-pcie"; 1513 reg = <0x33800000 0x400000>, 1514 <0x1ff00000 0x80000>; 1515 reg-names = "dbi", "config"; 1516 #address-cells = <3>; 1517 #size-cells = <2>; 1518 device_type = "pci"; 1519 bus-range = <0x00 0xff>; 1520 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1521 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1522 num-lanes = <1>; 1523 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1524 interrupt-names = "msi"; 1525 #interrupt-cells = <1>; 1526 interrupt-map-mask = <0 0 0 0x7>; 1527 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1528 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1529 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1530 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1531 fsl,max-link-speed = <2>; 1532 linux,pci-domain = <0>; 1533 power-domains = <&pgc_pcie>; 1534 resets = <&src IMX8MQ_RESET_PCIEPHY>, 1535 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1536 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1537 reset-names = "pciephy", "apps", "turnoff"; 1538 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, 1539 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1540 <&clk IMX8MQ_CLK_PCIE1_AUX>; 1541 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1542 <&clk IMX8MQ_SYS2_PLL_100M>, 1543 <&clk IMX8MQ_SYS1_PLL_80M>; 1544 assigned-clock-rates = <250000000>, <100000000>, 1545 <10000000>; 1546 status = "disabled"; 1547 }; 1548 1549 pcie1: pcie@33c00000 { 1550 compatible = "fsl,imx8mq-pcie"; 1551 reg = <0x33c00000 0x400000>, 1552 <0x27f00000 0x80000>; 1553 reg-names = "dbi", "config"; 1554 #address-cells = <3>; 1555 #size-cells = <2>; 1556 device_type = "pci"; 1557 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ 1558 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1559 num-lanes = <1>; 1560 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1561 interrupt-names = "msi"; 1562 #interrupt-cells = <1>; 1563 interrupt-map-mask = <0 0 0 0x7>; 1564 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1565 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1566 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1567 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1568 fsl,max-link-speed = <2>; 1569 linux,pci-domain = <1>; 1570 power-domains = <&pgc_pcie>; 1571 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1572 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1573 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1574 reset-names = "pciephy", "apps", "turnoff"; 1575 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, 1576 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1577 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1578 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1579 <&clk IMX8MQ_SYS2_PLL_100M>, 1580 <&clk IMX8MQ_SYS1_PLL_80M>; 1581 assigned-clock-rates = <250000000>, <100000000>, 1582 <10000000>; 1583 status = "disabled"; 1584 }; 1585 1586 gic: interrupt-controller@38800000 { 1587 compatible = "arm,gic-v3"; 1588 reg = <0x38800000 0x10000>, /* GIC Dist */ 1589 <0x38880000 0xc0000>, /* GICR */ 1590 <0x31000000 0x2000>, /* GICC */ 1591 <0x31010000 0x2000>, /* GICV */ 1592 <0x31020000 0x2000>; /* GICH */ 1593 #interrupt-cells = <3>; 1594 interrupt-controller; 1595 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1596 interrupt-parent = <&gic>; 1597 }; 1598 1599 ddrc: memory-controller@3d400000 { 1600 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; 1601 reg = <0x3d400000 0x400000>; 1602 clock-names = "core", "pll", "alt", "apb"; 1603 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, 1604 <&clk IMX8MQ_DRAM_PLL_OUT>, 1605 <&clk IMX8MQ_CLK_DRAM_ALT>, 1606 <&clk IMX8MQ_CLK_DRAM_APB>; 1607 status = "disabled"; 1608 }; 1609 1610 ddr-pmu@3d800000 { 1611 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1612 reg = <0x3d800000 0x400000>; 1613 interrupt-parent = <&gic>; 1614 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1615 }; 1616 }; 1617}; 1618