1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7#include <dt-bindings/clock/imx8mq-clock.h> 8#include <dt-bindings/power/imx8mq-power.h> 9#include <dt-bindings/reset/imx8mq-reset.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "dt-bindings/input/input.h" 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/interconnect/imx8mq.h> 15#include "imx8mq-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gpc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ethernet0 = &fec1; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 mmc0 = &usdhc1; 35 mmc1 = &usdhc2; 36 serial0 = &uart1; 37 serial1 = &uart2; 38 serial2 = &uart3; 39 serial3 = &uart4; 40 spi0 = &ecspi1; 41 spi1 = &ecspi2; 42 spi2 = &ecspi3; 43 }; 44 45 ckil: clock-ckil { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <32768>; 49 clock-output-names = "ckil"; 50 }; 51 52 osc_25m: clock-osc-25m { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 clock-output-names = "osc_25m"; 57 }; 58 59 osc_27m: clock-osc-27m { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <27000000>; 63 clock-output-names = "osc_27m"; 64 }; 65 66 clk_ext1: clock-ext1 { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <133000000>; 70 clock-output-names = "clk_ext1"; 71 }; 72 73 clk_ext2: clock-ext2 { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <133000000>; 77 clock-output-names = "clk_ext2"; 78 }; 79 80 clk_ext3: clock-ext3 { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <133000000>; 84 clock-output-names = "clk_ext3"; 85 }; 86 87 clk_ext4: clock-ext4 { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency= <133000000>; 91 clock-output-names = "clk_ext4"; 92 }; 93 94 cpus { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 A53_0: cpu@0 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x0>; 102 clock-latency = <61036>; /* two CLK32 periods */ 103 clocks = <&clk IMX8MQ_CLK_ARM>; 104 enable-method = "psci"; 105 i-cache-size = <0x8000>; 106 i-cache-line-size = <64>; 107 i-cache-sets = <256>; 108 d-cache-size = <0x8000>; 109 d-cache-line-size = <64>; 110 d-cache-sets = <128>; 111 next-level-cache = <&A53_L2>; 112 operating-points-v2 = <&a53_opp_table>; 113 #cooling-cells = <2>; 114 nvmem-cells = <&cpu_speed_grade>; 115 nvmem-cell-names = "speed_grade"; 116 }; 117 118 A53_1: cpu@1 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a53"; 121 reg = <0x1>; 122 clock-latency = <61036>; /* two CLK32 periods */ 123 clocks = <&clk IMX8MQ_CLK_ARM>; 124 enable-method = "psci"; 125 i-cache-size = <0x8000>; 126 i-cache-line-size = <64>; 127 i-cache-sets = <256>; 128 d-cache-size = <0x8000>; 129 d-cache-line-size = <64>; 130 d-cache-sets = <128>; 131 next-level-cache = <&A53_L2>; 132 operating-points-v2 = <&a53_opp_table>; 133 #cooling-cells = <2>; 134 }; 135 136 A53_2: cpu@2 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a53"; 139 reg = <0x2>; 140 clock-latency = <61036>; /* two CLK32 periods */ 141 clocks = <&clk IMX8MQ_CLK_ARM>; 142 enable-method = "psci"; 143 i-cache-size = <0x8000>; 144 i-cache-line-size = <64>; 145 i-cache-sets = <256>; 146 d-cache-size = <0x8000>; 147 d-cache-line-size = <64>; 148 d-cache-sets = <128>; 149 next-level-cache = <&A53_L2>; 150 operating-points-v2 = <&a53_opp_table>; 151 #cooling-cells = <2>; 152 }; 153 154 A53_3: cpu@3 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a53"; 157 reg = <0x3>; 158 clock-latency = <61036>; /* two CLK32 periods */ 159 clocks = <&clk IMX8MQ_CLK_ARM>; 160 enable-method = "psci"; 161 i-cache-size = <0x8000>; 162 i-cache-line-size = <64>; 163 i-cache-sets = <256>; 164 d-cache-size = <0x8000>; 165 d-cache-line-size = <64>; 166 d-cache-sets = <128>; 167 next-level-cache = <&A53_L2>; 168 operating-points-v2 = <&a53_opp_table>; 169 #cooling-cells = <2>; 170 }; 171 172 A53_L2: l2-cache0 { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-size = <0x100000>; 176 cache-line-size = <64>; 177 cache-sets = <1024>; 178 }; 179 }; 180 181 a53_opp_table: opp-table { 182 compatible = "operating-points-v2"; 183 opp-shared; 184 185 opp-800000000 { 186 opp-hz = /bits/ 64 <800000000>; 187 opp-microvolt = <900000>; 188 /* Industrial only */ 189 opp-supported-hw = <0xf>, <0x4>; 190 clock-latency-ns = <150000>; 191 opp-suspend; 192 }; 193 194 opp-1000000000 { 195 opp-hz = /bits/ 64 <1000000000>; 196 opp-microvolt = <900000>; 197 /* Consumer only */ 198 opp-supported-hw = <0xe>, <0x3>; 199 clock-latency-ns = <150000>; 200 opp-suspend; 201 }; 202 203 opp-1300000000 { 204 opp-hz = /bits/ 64 <1300000000>; 205 opp-microvolt = <1000000>; 206 opp-supported-hw = <0xc>, <0x4>; 207 clock-latency-ns = <150000>; 208 opp-suspend; 209 }; 210 211 opp-1500000000 { 212 opp-hz = /bits/ 64 <1500000000>; 213 opp-microvolt = <1000000>; 214 opp-supported-hw = <0x8>, <0x3>; 215 clock-latency-ns = <150000>; 216 opp-suspend; 217 }; 218 }; 219 220 pmu { 221 compatible = "arm,cortex-a53-pmu"; 222 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 223 interrupt-parent = <&gic>; 224 }; 225 226 psci { 227 compatible = "arm,psci-1.0"; 228 method = "smc"; 229 }; 230 231 thermal-zones { 232 cpu_thermal: cpu-thermal { 233 polling-delay-passive = <250>; 234 polling-delay = <2000>; 235 thermal-sensors = <&tmu 0>; 236 237 trips { 238 cpu_alert: cpu-alert { 239 temperature = <80000>; 240 hysteresis = <2000>; 241 type = "passive"; 242 }; 243 244 cpu-crit { 245 temperature = <90000>; 246 hysteresis = <2000>; 247 type = "critical"; 248 }; 249 }; 250 251 cooling-maps { 252 map0 { 253 trip = <&cpu_alert>; 254 cooling-device = 255 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 256 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 257 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 258 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 259 }; 260 }; 261 }; 262 263 gpu-thermal { 264 polling-delay-passive = <250>; 265 polling-delay = <2000>; 266 thermal-sensors = <&tmu 1>; 267 268 trips { 269 gpu_alert: gpu-alert { 270 temperature = <80000>; 271 hysteresis = <2000>; 272 type = "passive"; 273 }; 274 275 gpu-crit { 276 temperature = <90000>; 277 hysteresis = <2000>; 278 type = "critical"; 279 }; 280 }; 281 282 cooling-maps { 283 map0 { 284 trip = <&gpu_alert>; 285 cooling-device = 286 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 287 }; 288 }; 289 }; 290 291 vpu-thermal { 292 polling-delay-passive = <250>; 293 polling-delay = <2000>; 294 thermal-sensors = <&tmu 2>; 295 296 trips { 297 vpu-crit { 298 temperature = <90000>; 299 hysteresis = <2000>; 300 type = "critical"; 301 }; 302 }; 303 }; 304 }; 305 306 timer { 307 compatible = "arm,armv8-timer"; 308 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 309 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 310 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 311 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 312 interrupt-parent = <&gic>; 313 arm,no-tick-in-suspend; 314 }; 315 316 soc@0 { 317 compatible = "fsl,imx8mq-soc", "simple-bus"; 318 #address-cells = <1>; 319 #size-cells = <1>; 320 ranges = <0x0 0x0 0x0 0x3e000000>; 321 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 322 nvmem-cells = <&imx8mq_uid>; 323 nvmem-cell-names = "soc_unique_id"; 324 325 bus@30000000 { /* AIPS1 */ 326 compatible = "fsl,aips-bus", "simple-bus"; 327 reg = <0x30000000 0x400000>; 328 #address-cells = <1>; 329 #size-cells = <1>; 330 ranges = <0x30000000 0x30000000 0x400000>; 331 332 sai1: sai@30010000 { 333 #sound-dai-cells = <0>; 334 compatible = "fsl,imx8mq-sai"; 335 reg = <0x30010000 0x10000>; 336 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, 338 <&clk IMX8MQ_CLK_SAI1_ROOT>, 339 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 340 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 341 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; 342 dma-names = "rx", "tx"; 343 status = "disabled"; 344 }; 345 346 sai6: sai@30030000 { 347 #sound-dai-cells = <0>; 348 compatible = "fsl,imx8mq-sai"; 349 reg = <0x30030000 0x10000>; 350 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, 352 <&clk IMX8MQ_CLK_SAI6_ROOT>, 353 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 354 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 355 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; 356 dma-names = "rx", "tx"; 357 status = "disabled"; 358 }; 359 360 sai5: sai@30040000 { 361 #sound-dai-cells = <0>; 362 compatible = "fsl,imx8mq-sai"; 363 reg = <0x30040000 0x10000>; 364 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, 366 <&clk IMX8MQ_CLK_SAI5_ROOT>, 367 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 368 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 369 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; 370 dma-names = "rx", "tx"; 371 status = "disabled"; 372 }; 373 374 sai4: sai@30050000 { 375 #sound-dai-cells = <0>; 376 compatible = "fsl,imx8mq-sai"; 377 reg = <0x30050000 0x10000>; 378 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, 380 <&clk IMX8MQ_CLK_SAI4_ROOT>, 381 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 382 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 383 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; 384 dma-names = "rx", "tx"; 385 status = "disabled"; 386 }; 387 388 gpio1: gpio@30200000 { 389 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 390 reg = <0x30200000 0x10000>; 391 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; 394 gpio-controller; 395 #gpio-cells = <2>; 396 interrupt-controller; 397 #interrupt-cells = <2>; 398 gpio-ranges = <&iomuxc 0 10 30>; 399 }; 400 401 gpio2: gpio@30210000 { 402 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 403 reg = <0x30210000 0x10000>; 404 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; 407 gpio-controller; 408 #gpio-cells = <2>; 409 interrupt-controller; 410 #interrupt-cells = <2>; 411 gpio-ranges = <&iomuxc 0 40 21>; 412 }; 413 414 gpio3: gpio@30220000 { 415 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 416 reg = <0x30220000 0x10000>; 417 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; 420 gpio-controller; 421 #gpio-cells = <2>; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 gpio-ranges = <&iomuxc 0 61 26>; 425 }; 426 427 gpio4: gpio@30230000 { 428 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 429 reg = <0x30230000 0x10000>; 430 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 gpio-ranges = <&iomuxc 0 87 32>; 438 }; 439 440 gpio5: gpio@30240000 { 441 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 442 reg = <0x30240000 0x10000>; 443 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; 446 gpio-controller; 447 #gpio-cells = <2>; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 gpio-ranges = <&iomuxc 0 119 30>; 451 }; 452 453 tmu: tmu@30260000 { 454 compatible = "fsl,imx8mq-tmu"; 455 reg = <0x30260000 0x10000>; 456 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; 458 little-endian; 459 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 460 fsl,tmu-calibration = <0x00000000 0x00000023>, 461 <0x00000001 0x00000029>, 462 <0x00000002 0x0000002f>, 463 <0x00000003 0x00000035>, 464 <0x00000004 0x0000003d>, 465 <0x00000005 0x00000043>, 466 <0x00000006 0x0000004b>, 467 <0x00000007 0x00000051>, 468 <0x00000008 0x00000057>, 469 <0x00000009 0x0000005f>, 470 <0x0000000a 0x00000067>, 471 <0x0000000b 0x0000006f>, 472 473 <0x00010000 0x0000001b>, 474 <0x00010001 0x00000023>, 475 <0x00010002 0x0000002b>, 476 <0x00010003 0x00000033>, 477 <0x00010004 0x0000003b>, 478 <0x00010005 0x00000043>, 479 <0x00010006 0x0000004b>, 480 <0x00010007 0x00000055>, 481 <0x00010008 0x0000005d>, 482 <0x00010009 0x00000067>, 483 <0x0001000a 0x00000070>, 484 485 <0x00020000 0x00000017>, 486 <0x00020001 0x00000023>, 487 <0x00020002 0x0000002d>, 488 <0x00020003 0x00000037>, 489 <0x00020004 0x00000041>, 490 <0x00020005 0x0000004b>, 491 <0x00020006 0x00000057>, 492 <0x00020007 0x00000063>, 493 <0x00020008 0x0000006f>, 494 495 <0x00030000 0x00000015>, 496 <0x00030001 0x00000021>, 497 <0x00030002 0x0000002d>, 498 <0x00030003 0x00000039>, 499 <0x00030004 0x00000045>, 500 <0x00030005 0x00000053>, 501 <0x00030006 0x0000005f>, 502 <0x00030007 0x00000071>; 503 #thermal-sensor-cells = <1>; 504 }; 505 506 wdog1: watchdog@30280000 { 507 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 508 reg = <0x30280000 0x10000>; 509 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; 511 status = "disabled"; 512 }; 513 514 wdog2: watchdog@30290000 { 515 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 516 reg = <0x30290000 0x10000>; 517 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; 519 status = "disabled"; 520 }; 521 522 wdog3: watchdog@302a0000 { 523 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 524 reg = <0x302a0000 0x10000>; 525 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; 527 status = "disabled"; 528 }; 529 530 sdma2: sdma@302c0000 { 531 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 532 reg = <0x302c0000 0x10000>; 533 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, 535 <&clk IMX8MQ_CLK_SDMA2_ROOT>; 536 clock-names = "ipg", "ahb"; 537 #dma-cells = <3>; 538 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 539 }; 540 541 lcdif: lcd-controller@30320000 { 542 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; 543 reg = <0x30320000 0x10000>; 544 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 546 clock-names = "pix"; 547 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 548 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 549 <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 550 <&clk IMX8MQ_VIDEO_PLL1>; 551 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 552 <&clk IMX8MQ_VIDEO_PLL1>, 553 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 554 assigned-clock-rates = <0>, <0>, <0>, <594000000>; 555 status = "disabled"; 556 557 port { 558 lcdif_mipi_dsi: endpoint { 559 remote-endpoint = <&mipi_dsi_lcdif_in>; 560 }; 561 }; 562 }; 563 564 iomuxc: pinctrl@30330000 { 565 compatible = "fsl,imx8mq-iomuxc"; 566 reg = <0x30330000 0x10000>; 567 }; 568 569 iomuxc_gpr: syscon@30340000 { 570 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", 571 "syscon", "simple-mfd"; 572 reg = <0x30340000 0x10000>; 573 574 mux: mux-controller { 575 compatible = "mmio-mux"; 576 #mux-control-cells = <1>; 577 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ 578 }; 579 }; 580 581 ocotp: efuse@30350000 { 582 compatible = "fsl,imx8mq-ocotp", "syscon"; 583 reg = <0x30350000 0x10000>; 584 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 588 imx8mq_uid: soc-uid@410 { 589 reg = <0x4 0x8>; 590 }; 591 592 cpu_speed_grade: speed-grade@10 { 593 reg = <0x10 4>; 594 }; 595 596 fec_mac_address: mac-address@90 { 597 reg = <0x90 6>; 598 }; 599 }; 600 601 anatop: syscon@30360000 { 602 compatible = "fsl,imx8mq-anatop", "syscon"; 603 reg = <0x30360000 0x10000>; 604 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 605 }; 606 607 snvs: snvs@30370000 { 608 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 609 reg = <0x30370000 0x10000>; 610 611 snvs_rtc: snvs-rtc-lp{ 612 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 613 regmap =<&snvs>; 614 offset = <0x34>; 615 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 618 clock-names = "snvs-rtc"; 619 }; 620 621 snvs_pwrkey: snvs-powerkey { 622 compatible = "fsl,sec-v4.0-pwrkey"; 623 regmap = <&snvs>; 624 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 626 clock-names = "snvs-pwrkey"; 627 linux,keycode = <KEY_POWER>; 628 wakeup-source; 629 status = "disabled"; 630 }; 631 }; 632 633 clk: clock-controller@30380000 { 634 compatible = "fsl,imx8mq-ccm"; 635 reg = <0x30380000 0x10000>; 636 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 638 #clock-cells = <1>; 639 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, 640 <&clk_ext1>, <&clk_ext2>, 641 <&clk_ext3>, <&clk_ext4>; 642 clock-names = "ckil", "osc_25m", "osc_27m", 643 "clk_ext1", "clk_ext2", 644 "clk_ext3", "clk_ext4"; 645 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, 646 <&clk IMX8MQ_CLK_A53_CORE>, 647 <&clk IMX8MQ_CLK_NOC>, 648 <&clk IMX8MQ_CLK_AUDIO_AHB>, 649 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, 650 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, 651 <&clk IMX8MQ_AUDIO_PLL1>, 652 <&clk IMX8MQ_AUDIO_PLL2>; 653 assigned-clock-rates = <0>, <0>, 654 <800000000>, 655 <0>, 656 <0>, 657 <0>, 658 <786432000>, 659 <722534400>; 660 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, 661 <&clk IMX8MQ_ARM_PLL_OUT>, 662 <0>, 663 <&clk IMX8MQ_SYS2_PLL_500M>, 664 <&clk IMX8MQ_AUDIO_PLL1>, 665 <&clk IMX8MQ_AUDIO_PLL2>; 666 }; 667 668 src: reset-controller@30390000 { 669 compatible = "fsl,imx8mq-src", "syscon"; 670 reg = <0x30390000 0x10000>; 671 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 672 #reset-cells = <1>; 673 }; 674 675 gpc: gpc@303a0000 { 676 compatible = "fsl,imx8mq-gpc"; 677 reg = <0x303a0000 0x10000>; 678 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 679 interrupt-parent = <&gic>; 680 interrupt-controller; 681 #interrupt-cells = <3>; 682 683 pgc { 684 #address-cells = <1>; 685 #size-cells = <0>; 686 687 pgc_mipi: power-domain@0 { 688 #power-domain-cells = <0>; 689 reg = <IMX8M_POWER_DOMAIN_MIPI>; 690 }; 691 692 /* 693 * As per comment in ATF source code: 694 * 695 * PCIE1 and PCIE2 share the 696 * same reset signal, if we 697 * power down PCIE2, PCIE1 698 * will be held in reset too. 699 * 700 * So instead of creating two 701 * separate power domains for 702 * PCIE1 and PCIE2 we create a 703 * link between both and use 704 * it as a shared PCIE power 705 * domain. 706 */ 707 pgc_pcie: power-domain@1 { 708 #power-domain-cells = <0>; 709 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 710 power-domains = <&pgc_pcie2>; 711 }; 712 713 pgc_otg1: power-domain@2 { 714 #power-domain-cells = <0>; 715 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; 716 }; 717 718 pgc_otg2: power-domain@3 { 719 #power-domain-cells = <0>; 720 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; 721 }; 722 723 pgc_ddr1: power-domain@4 { 724 #power-domain-cells = <0>; 725 reg = <IMX8M_POWER_DOMAIN_DDR1>; 726 }; 727 728 pgc_gpu: power-domain@5 { 729 #power-domain-cells = <0>; 730 reg = <IMX8M_POWER_DOMAIN_GPU>; 731 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 732 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 733 <&clk IMX8MQ_CLK_GPU_AXI>, 734 <&clk IMX8MQ_CLK_GPU_AHB>; 735 }; 736 737 pgc_vpu: power-domain@6 { 738 #power-domain-cells = <0>; 739 reg = <IMX8M_POWER_DOMAIN_VPU>; 740 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, 741 <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 742 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 743 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, 744 <&clk IMX8MQ_CLK_VPU_G2>, 745 <&clk IMX8MQ_CLK_VPU_BUS>, 746 <&clk IMX8MQ_VPU_PLL_BYPASS>; 747 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, 748 <&clk IMX8MQ_VPU_PLL_OUT>, 749 <&clk IMX8MQ_SYS1_PLL_800M>, 750 <&clk IMX8MQ_VPU_PLL>; 751 assigned-clock-rates = <600000000>, 752 <600000000>, 753 <800000000>, 754 <0>; 755 }; 756 757 pgc_disp: power-domain@7 { 758 #power-domain-cells = <0>; 759 reg = <IMX8M_POWER_DOMAIN_DISP>; 760 }; 761 762 pgc_mipi_csi1: power-domain@8 { 763 #power-domain-cells = <0>; 764 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; 765 }; 766 767 pgc_mipi_csi2: power-domain@9 { 768 #power-domain-cells = <0>; 769 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; 770 }; 771 772 pgc_pcie2: power-domain@a { 773 #power-domain-cells = <0>; 774 reg = <IMX8M_POWER_DOMAIN_PCIE2>; 775 }; 776 }; 777 }; 778 }; 779 780 bus@30400000 { /* AIPS2 */ 781 compatible = "fsl,aips-bus", "simple-bus"; 782 reg = <0x30400000 0x400000>; 783 #address-cells = <1>; 784 #size-cells = <1>; 785 ranges = <0x30400000 0x30400000 0x400000>; 786 787 pwm1: pwm@30660000 { 788 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 789 reg = <0x30660000 0x10000>; 790 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, 792 <&clk IMX8MQ_CLK_PWM1_ROOT>; 793 clock-names = "ipg", "per"; 794 #pwm-cells = <2>; 795 status = "disabled"; 796 }; 797 798 pwm2: pwm@30670000 { 799 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 800 reg = <0x30670000 0x10000>; 801 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, 803 <&clk IMX8MQ_CLK_PWM2_ROOT>; 804 clock-names = "ipg", "per"; 805 #pwm-cells = <2>; 806 status = "disabled"; 807 }; 808 809 pwm3: pwm@30680000 { 810 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 811 reg = <0x30680000 0x10000>; 812 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, 814 <&clk IMX8MQ_CLK_PWM3_ROOT>; 815 clock-names = "ipg", "per"; 816 #pwm-cells = <2>; 817 status = "disabled"; 818 }; 819 820 pwm4: pwm@30690000 { 821 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 822 reg = <0x30690000 0x10000>; 823 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, 825 <&clk IMX8MQ_CLK_PWM4_ROOT>; 826 clock-names = "ipg", "per"; 827 #pwm-cells = <2>; 828 status = "disabled"; 829 }; 830 831 system_counter: timer@306a0000 { 832 compatible = "nxp,sysctr-timer"; 833 reg = <0x306a0000 0x20000>; 834 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&osc_25m>; 836 clock-names = "per"; 837 }; 838 }; 839 840 bus@30800000 { /* AIPS3 */ 841 compatible = "fsl,aips-bus", "simple-bus"; 842 reg = <0x30800000 0x400000>; 843 #address-cells = <1>; 844 #size-cells = <1>; 845 ranges = <0x30800000 0x30800000 0x400000>, 846 <0x08000000 0x08000000 0x10000000>; 847 848 spdif1: spdif@30810000 { 849 compatible = "fsl,imx35-spdif"; 850 reg = <0x30810000 0x10000>; 851 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 853 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 854 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ 855 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 856 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 857 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 858 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 859 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 860 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 861 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 862 clock-names = "core", "rxtx0", 863 "rxtx1", "rxtx2", 864 "rxtx3", "rxtx4", 865 "rxtx5", "rxtx6", 866 "rxtx7", "spba"; 867 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; 868 dma-names = "rx", "tx"; 869 status = "disabled"; 870 }; 871 872 ecspi1: spi@30820000 { 873 #address-cells = <1>; 874 #size-cells = <0>; 875 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 876 reg = <0x30820000 0x10000>; 877 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, 879 <&clk IMX8MQ_CLK_ECSPI1_ROOT>; 880 clock-names = "ipg", "per"; 881 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 882 dma-names = "rx", "tx"; 883 status = "disabled"; 884 }; 885 886 ecspi2: spi@30830000 { 887 #address-cells = <1>; 888 #size-cells = <0>; 889 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 890 reg = <0x30830000 0x10000>; 891 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, 893 <&clk IMX8MQ_CLK_ECSPI2_ROOT>; 894 clock-names = "ipg", "per"; 895 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 896 dma-names = "rx", "tx"; 897 status = "disabled"; 898 }; 899 900 ecspi3: spi@30840000 { 901 #address-cells = <1>; 902 #size-cells = <0>; 903 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 904 reg = <0x30840000 0x10000>; 905 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, 907 <&clk IMX8MQ_CLK_ECSPI3_ROOT>; 908 clock-names = "ipg", "per"; 909 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 910 dma-names = "rx", "tx"; 911 status = "disabled"; 912 }; 913 914 uart1: serial@30860000 { 915 compatible = "fsl,imx8mq-uart", 916 "fsl,imx6q-uart"; 917 reg = <0x30860000 0x10000>; 918 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, 920 <&clk IMX8MQ_CLK_UART1_ROOT>; 921 clock-names = "ipg", "per"; 922 status = "disabled"; 923 }; 924 925 uart3: serial@30880000 { 926 compatible = "fsl,imx8mq-uart", 927 "fsl,imx6q-uart"; 928 reg = <0x30880000 0x10000>; 929 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, 931 <&clk IMX8MQ_CLK_UART3_ROOT>; 932 clock-names = "ipg", "per"; 933 status = "disabled"; 934 }; 935 936 uart2: serial@30890000 { 937 compatible = "fsl,imx8mq-uart", 938 "fsl,imx6q-uart"; 939 reg = <0x30890000 0x10000>; 940 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, 942 <&clk IMX8MQ_CLK_UART2_ROOT>; 943 clock-names = "ipg", "per"; 944 status = "disabled"; 945 }; 946 947 spdif2: spdif@308a0000 { 948 compatible = "fsl,imx35-spdif"; 949 reg = <0x308a0000 0x10000>; 950 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 952 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 953 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ 954 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 955 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 956 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 957 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 958 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 959 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 960 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 961 clock-names = "core", "rxtx0", 962 "rxtx1", "rxtx2", 963 "rxtx3", "rxtx4", 964 "rxtx5", "rxtx6", 965 "rxtx7", "spba"; 966 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; 967 dma-names = "rx", "tx"; 968 status = "disabled"; 969 }; 970 971 sai2: sai@308b0000 { 972 #sound-dai-cells = <0>; 973 compatible = "fsl,imx8mq-sai"; 974 reg = <0x308b0000 0x10000>; 975 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, 977 <&clk IMX8MQ_CLK_SAI2_ROOT>, 978 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 979 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 980 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; 981 dma-names = "rx", "tx"; 982 status = "disabled"; 983 }; 984 985 sai3: sai@308c0000 { 986 #sound-dai-cells = <0>; 987 compatible = "fsl,imx8mq-sai"; 988 reg = <0x308c0000 0x10000>; 989 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, 991 <&clk IMX8MQ_CLK_SAI3_ROOT>, 992 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 993 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 994 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; 995 dma-names = "rx", "tx"; 996 status = "disabled"; 997 }; 998 999 crypto: crypto@30900000 { 1000 compatible = "fsl,sec-v4.0"; 1001 #address-cells = <1>; 1002 #size-cells = <1>; 1003 reg = <0x30900000 0x40000>; 1004 ranges = <0 0x30900000 0x40000>; 1005 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&clk IMX8MQ_CLK_AHB>, 1007 <&clk IMX8MQ_CLK_IPG_ROOT>; 1008 clock-names = "aclk", "ipg"; 1009 1010 sec_jr0: jr@1000 { 1011 compatible = "fsl,sec-v4.0-job-ring"; 1012 reg = <0x1000 0x1000>; 1013 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1014 }; 1015 1016 sec_jr1: jr@2000 { 1017 compatible = "fsl,sec-v4.0-job-ring"; 1018 reg = <0x2000 0x1000>; 1019 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1020 }; 1021 1022 sec_jr2: jr@3000 { 1023 compatible = "fsl,sec-v4.0-job-ring"; 1024 reg = <0x3000 0x1000>; 1025 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1026 }; 1027 }; 1028 1029 mipi_dsi: mipi-dsi@30a00000 { 1030 compatible = "fsl,imx8mq-nwl-dsi"; 1031 reg = <0x30a00000 0x300>; 1032 clocks = <&clk IMX8MQ_CLK_DSI_CORE>, 1033 <&clk IMX8MQ_CLK_DSI_AHB>, 1034 <&clk IMX8MQ_CLK_DSI_IPG_DIV>, 1035 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1036 <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 1037 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; 1038 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, 1039 <&clk IMX8MQ_CLK_DSI_CORE>, 1040 <&clk IMX8MQ_CLK_DSI_IPG_DIV>; 1041 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, 1042 <&clk IMX8MQ_SYS1_PLL_266M>; 1043 assigned-clock-rates = <80000000>, <266000000>, <20000000>; 1044 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1045 mux-controls = <&mux 0>; 1046 power-domains = <&pgc_mipi>; 1047 phys = <&dphy>; 1048 phy-names = "dphy"; 1049 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, 1050 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, 1051 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, 1052 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; 1053 reset-names = "byte", "dpi", "esc", "pclk"; 1054 status = "disabled"; 1055 1056 ports { 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 1060 port@0 { 1061 reg = <0>; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 mipi_dsi_lcdif_in: endpoint@0 { 1065 reg = <0>; 1066 remote-endpoint = <&lcdif_mipi_dsi>; 1067 }; 1068 }; 1069 }; 1070 }; 1071 1072 dphy: dphy@30a00300 { 1073 compatible = "fsl,imx8mq-mipi-dphy"; 1074 reg = <0x30a00300 0x100>; 1075 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 1076 clock-names = "phy_ref"; 1077 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 1078 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 1079 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1080 <&clk IMX8MQ_VIDEO_PLL1>; 1081 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 1082 <&clk IMX8MQ_VIDEO_PLL1>, 1083 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 1084 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; 1085 #phy-cells = <0>; 1086 power-domains = <&pgc_mipi>; 1087 status = "disabled"; 1088 }; 1089 1090 i2c1: i2c@30a20000 { 1091 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1092 reg = <0x30a20000 0x10000>; 1093 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 i2c2: i2c@30a30000 { 1101 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1102 reg = <0x30a30000 0x10000>; 1103 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 i2c3: i2c@30a40000 { 1111 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1112 reg = <0x30a40000 0x10000>; 1113 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 status = "disabled"; 1118 }; 1119 1120 i2c4: i2c@30a50000 { 1121 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1122 reg = <0x30a50000 0x10000>; 1123 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 status = "disabled"; 1128 }; 1129 1130 uart4: serial@30a60000 { 1131 compatible = "fsl,imx8mq-uart", 1132 "fsl,imx6q-uart"; 1133 reg = <0x30a60000 0x10000>; 1134 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, 1136 <&clk IMX8MQ_CLK_UART4_ROOT>; 1137 clock-names = "ipg", "per"; 1138 status = "disabled"; 1139 }; 1140 1141 mipi_csi1: csi@30a70000 { 1142 compatible = "fsl,imx8mq-mipi-csi2"; 1143 reg = <0x30a70000 0x1000>; 1144 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1145 <&clk IMX8MQ_CLK_CSI1_ESC>, 1146 <&clk IMX8MQ_CLK_CSI1_PHY_REF>; 1147 clock-names = "core", "esc", "ui"; 1148 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1149 <&clk IMX8MQ_CLK_CSI1_PHY_REF>, 1150 <&clk IMX8MQ_CLK_CSI1_ESC>; 1151 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1152 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1153 <&clk IMX8MQ_SYS2_PLL_1000M>, 1154 <&clk IMX8MQ_SYS1_PLL_800M>; 1155 power-domains = <&pgc_mipi_csi1>; 1156 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, 1157 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, 1158 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; 1159 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; 1160 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; 1161 interconnect-names = "dram"; 1162 status = "disabled"; 1163 1164 ports { 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 1168 port@1 { 1169 reg = <1>; 1170 1171 csi1_mipi_ep: endpoint { 1172 remote-endpoint = <&csi1_ep>; 1173 }; 1174 }; 1175 }; 1176 }; 1177 1178 csi1: csi@30a90000 { 1179 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; 1180 reg = <0x30a90000 0x10000>; 1181 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; 1183 clock-names = "mclk"; 1184 status = "disabled"; 1185 1186 port { 1187 csi1_ep: endpoint { 1188 remote-endpoint = <&csi1_mipi_ep>; 1189 }; 1190 }; 1191 }; 1192 1193 mipi_csi2: csi@30b60000 { 1194 compatible = "fsl,imx8mq-mipi-csi2"; 1195 reg = <0x30b60000 0x1000>; 1196 clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1197 <&clk IMX8MQ_CLK_CSI2_ESC>, 1198 <&clk IMX8MQ_CLK_CSI2_PHY_REF>; 1199 clock-names = "core", "esc", "ui"; 1200 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1201 <&clk IMX8MQ_CLK_CSI2_PHY_REF>, 1202 <&clk IMX8MQ_CLK_CSI2_ESC>; 1203 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1204 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1205 <&clk IMX8MQ_SYS2_PLL_1000M>, 1206 <&clk IMX8MQ_SYS1_PLL_800M>; 1207 power-domains = <&pgc_mipi_csi2>; 1208 resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, 1209 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, 1210 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; 1211 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; 1212 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; 1213 interconnect-names = "dram"; 1214 status = "disabled"; 1215 1216 ports { 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 1220 port@1 { 1221 reg = <1>; 1222 1223 csi2_mipi_ep: endpoint { 1224 remote-endpoint = <&csi2_ep>; 1225 }; 1226 }; 1227 }; 1228 }; 1229 1230 csi2: csi@30b80000 { 1231 compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; 1232 reg = <0x30b80000 0x10000>; 1233 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; 1235 clock-names = "mclk"; 1236 status = "disabled"; 1237 1238 port { 1239 csi2_ep: endpoint { 1240 remote-endpoint = <&csi2_mipi_ep>; 1241 }; 1242 }; 1243 }; 1244 1245 mu: mailbox@30aa0000 { 1246 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; 1247 reg = <0x30aa0000 0x10000>; 1248 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1249 clocks = <&clk IMX8MQ_CLK_MU_ROOT>; 1250 #mbox-cells = <2>; 1251 }; 1252 1253 usdhc1: mmc@30b40000 { 1254 compatible = "fsl,imx8mq-usdhc", 1255 "fsl,imx7d-usdhc"; 1256 reg = <0x30b40000 0x10000>; 1257 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1259 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1260 <&clk IMX8MQ_CLK_USDHC1_ROOT>; 1261 clock-names = "ipg", "ahb", "per"; 1262 fsl,tuning-start-tap = <20>; 1263 fsl,tuning-step = <2>; 1264 bus-width = <4>; 1265 status = "disabled"; 1266 }; 1267 1268 usdhc2: mmc@30b50000 { 1269 compatible = "fsl,imx8mq-usdhc", 1270 "fsl,imx7d-usdhc"; 1271 reg = <0x30b50000 0x10000>; 1272 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1274 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1275 <&clk IMX8MQ_CLK_USDHC2_ROOT>; 1276 clock-names = "ipg", "ahb", "per"; 1277 fsl,tuning-start-tap = <20>; 1278 fsl,tuning-step = <2>; 1279 bus-width = <4>; 1280 status = "disabled"; 1281 }; 1282 1283 qspi0: spi@30bb0000 { 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; 1287 reg = <0x30bb0000 0x10000>, 1288 <0x08000000 0x10000000>; 1289 reg-names = "QuadSPI", "QuadSPI-memory"; 1290 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1291 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, 1292 <&clk IMX8MQ_CLK_QSPI_ROOT>; 1293 clock-names = "qspi_en", "qspi"; 1294 status = "disabled"; 1295 }; 1296 1297 sdma1: sdma@30bd0000 { 1298 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 1299 reg = <0x30bd0000 0x10000>; 1300 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1301 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, 1302 <&clk IMX8MQ_CLK_AHB>; 1303 clock-names = "ipg", "ahb"; 1304 #dma-cells = <3>; 1305 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1306 }; 1307 1308 fec1: ethernet@30be0000 { 1309 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1310 reg = <0x30be0000 0x10000>; 1311 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1315 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, 1316 <&clk IMX8MQ_CLK_ENET1_ROOT>, 1317 <&clk IMX8MQ_CLK_ENET_TIMER>, 1318 <&clk IMX8MQ_CLK_ENET_REF>, 1319 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1320 clock-names = "ipg", "ahb", "ptp", 1321 "enet_clk_ref", "enet_out"; 1322 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, 1323 <&clk IMX8MQ_CLK_ENET_TIMER>, 1324 <&clk IMX8MQ_CLK_ENET_REF>, 1325 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1326 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1327 <&clk IMX8MQ_SYS2_PLL_100M>, 1328 <&clk IMX8MQ_SYS2_PLL_125M>, 1329 <&clk IMX8MQ_SYS2_PLL_50M>; 1330 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1331 fsl,num-tx-queues = <3>; 1332 fsl,num-rx-queues = <3>; 1333 nvmem-cells = <&fec_mac_address>; 1334 nvmem-cell-names = "mac-address"; 1335 fsl,stop-mode = <&iomuxc_gpr 0x10 3>; 1336 status = "disabled"; 1337 }; 1338 }; 1339 1340 noc: interconnect@32700000 { 1341 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; 1342 reg = <0x32700000 0x100000>; 1343 clocks = <&clk IMX8MQ_CLK_NOC>; 1344 fsl,ddrc = <&ddrc>; 1345 #interconnect-cells = <1>; 1346 operating-points-v2 = <&noc_opp_table>; 1347 1348 noc_opp_table: opp-table { 1349 compatible = "operating-points-v2"; 1350 1351 opp-133M { 1352 opp-hz = /bits/ 64 <133333333>; 1353 }; 1354 1355 opp-400M { 1356 opp-hz = /bits/ 64 <400000000>; 1357 }; 1358 1359 opp-800M { 1360 opp-hz = /bits/ 64 <800000000>; 1361 }; 1362 }; 1363 }; 1364 1365 bus@32c00000 { /* AIPS4 */ 1366 compatible = "fsl,aips-bus", "simple-bus"; 1367 reg = <0x32c00000 0x400000>; 1368 #address-cells = <1>; 1369 #size-cells = <1>; 1370 ranges = <0x32c00000 0x32c00000 0x400000>; 1371 1372 irqsteer: interrupt-controller@32e2d000 { 1373 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; 1374 reg = <0x32e2d000 0x1000>; 1375 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1376 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 1377 clock-names = "ipg"; 1378 fsl,channel = <0>; 1379 fsl,num-irqs = <64>; 1380 interrupt-controller; 1381 #interrupt-cells = <1>; 1382 }; 1383 }; 1384 1385 gpu: gpu@38000000 { 1386 compatible = "vivante,gc"; 1387 reg = <0x38000000 0x40000>; 1388 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1389 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 1390 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 1391 <&clk IMX8MQ_CLK_GPU_AXI>, 1392 <&clk IMX8MQ_CLK_GPU_AHB>; 1393 clock-names = "core", "shader", "bus", "reg"; 1394 #cooling-cells = <2>; 1395 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, 1396 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, 1397 <&clk IMX8MQ_CLK_GPU_AXI>, 1398 <&clk IMX8MQ_CLK_GPU_AHB>, 1399 <&clk IMX8MQ_GPU_PLL_BYPASS>; 1400 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, 1401 <&clk IMX8MQ_GPU_PLL_OUT>, 1402 <&clk IMX8MQ_GPU_PLL_OUT>, 1403 <&clk IMX8MQ_GPU_PLL_OUT>, 1404 <&clk IMX8MQ_GPU_PLL>; 1405 assigned-clock-rates = <800000000>, <800000000>, 1406 <800000000>, <800000000>, <0>; 1407 power-domains = <&pgc_gpu>; 1408 }; 1409 1410 usb_dwc3_0: usb@38100000 { 1411 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1412 reg = <0x38100000 0x10000>; 1413 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, 1414 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1415 <&clk IMX8MQ_CLK_32K>; 1416 clock-names = "bus_early", "ref", "suspend"; 1417 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1418 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1419 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1420 <&clk IMX8MQ_SYS1_PLL_100M>; 1421 assigned-clock-rates = <500000000>, <100000000>; 1422 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1423 phys = <&usb3_phy0>, <&usb3_phy0>; 1424 phy-names = "usb2-phy", "usb3-phy"; 1425 power-domains = <&pgc_otg1>; 1426 usb3-resume-missing-cas; 1427 status = "disabled"; 1428 }; 1429 1430 usb3_phy0: usb-phy@381f0040 { 1431 compatible = "fsl,imx8mq-usb-phy"; 1432 reg = <0x381f0040 0x40>; 1433 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 1434 clock-names = "phy"; 1435 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1436 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1437 assigned-clock-rates = <100000000>; 1438 #phy-cells = <0>; 1439 status = "disabled"; 1440 }; 1441 1442 usb_dwc3_1: usb@38200000 { 1443 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1444 reg = <0x38200000 0x10000>; 1445 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, 1446 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1447 <&clk IMX8MQ_CLK_32K>; 1448 clock-names = "bus_early", "ref", "suspend"; 1449 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1450 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1451 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1452 <&clk IMX8MQ_SYS1_PLL_100M>; 1453 assigned-clock-rates = <500000000>, <100000000>; 1454 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1455 phys = <&usb3_phy1>, <&usb3_phy1>; 1456 phy-names = "usb2-phy", "usb3-phy"; 1457 power-domains = <&pgc_otg2>; 1458 usb3-resume-missing-cas; 1459 status = "disabled"; 1460 }; 1461 1462 usb3_phy1: usb-phy@382f0040 { 1463 compatible = "fsl,imx8mq-usb-phy"; 1464 reg = <0x382f0040 0x40>; 1465 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; 1466 clock-names = "phy"; 1467 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1468 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1469 assigned-clock-rates = <100000000>; 1470 #phy-cells = <0>; 1471 status = "disabled"; 1472 }; 1473 1474 vpu_g1: video-codec@38300000 { 1475 compatible = "nxp,imx8mq-vpu-g1"; 1476 reg = <0x38300000 0x10000>; 1477 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1478 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; 1479 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; 1480 }; 1481 1482 vpu_g2: video-codec@38310000 { 1483 compatible = "nxp,imx8mq-vpu-g2"; 1484 reg = <0x38310000 0x10000>; 1485 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1486 clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1487 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; 1488 }; 1489 1490 vpu_blk_ctrl: blk-ctrl@38320000 { 1491 compatible = "fsl,imx8mq-vpu-blk-ctrl"; 1492 reg = <0x38320000 0x100>; 1493 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; 1494 power-domain-names = "bus", "g1", "g2"; 1495 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 1496 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1497 clock-names = "g1", "g2"; 1498 #power-domain-cells = <1>; 1499 }; 1500 1501 pcie0: pcie@33800000 { 1502 compatible = "fsl,imx8mq-pcie"; 1503 reg = <0x33800000 0x400000>, 1504 <0x1ff00000 0x80000>; 1505 reg-names = "dbi", "config"; 1506 #address-cells = <3>; 1507 #size-cells = <2>; 1508 device_type = "pci"; 1509 bus-range = <0x00 0xff>; 1510 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1511 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1512 num-lanes = <1>; 1513 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1514 interrupt-names = "msi"; 1515 #interrupt-cells = <1>; 1516 interrupt-map-mask = <0 0 0 0x7>; 1517 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1518 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1519 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1520 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1521 fsl,max-link-speed = <2>; 1522 linux,pci-domain = <0>; 1523 power-domains = <&pgc_pcie>; 1524 resets = <&src IMX8MQ_RESET_PCIEPHY>, 1525 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1526 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1527 reset-names = "pciephy", "apps", "turnoff"; 1528 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, 1529 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1530 <&clk IMX8MQ_CLK_PCIE1_AUX>; 1531 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1532 <&clk IMX8MQ_SYS2_PLL_100M>, 1533 <&clk IMX8MQ_SYS1_PLL_80M>; 1534 assigned-clock-rates = <250000000>, <100000000>, 1535 <10000000>; 1536 status = "disabled"; 1537 }; 1538 1539 pcie1: pcie@33c00000 { 1540 compatible = "fsl,imx8mq-pcie"; 1541 reg = <0x33c00000 0x400000>, 1542 <0x27f00000 0x80000>; 1543 reg-names = "dbi", "config"; 1544 #address-cells = <3>; 1545 #size-cells = <2>; 1546 device_type = "pci"; 1547 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ 1548 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1549 num-lanes = <1>; 1550 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1551 interrupt-names = "msi"; 1552 #interrupt-cells = <1>; 1553 interrupt-map-mask = <0 0 0 0x7>; 1554 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1555 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1556 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1557 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1558 fsl,max-link-speed = <2>; 1559 linux,pci-domain = <1>; 1560 power-domains = <&pgc_pcie>; 1561 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1562 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1563 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1564 reset-names = "pciephy", "apps", "turnoff"; 1565 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, 1566 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1567 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1568 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1569 <&clk IMX8MQ_SYS2_PLL_100M>, 1570 <&clk IMX8MQ_SYS1_PLL_80M>; 1571 assigned-clock-rates = <250000000>, <100000000>, 1572 <10000000>; 1573 status = "disabled"; 1574 }; 1575 1576 gic: interrupt-controller@38800000 { 1577 compatible = "arm,gic-v3"; 1578 reg = <0x38800000 0x10000>, /* GIC Dist */ 1579 <0x38880000 0xc0000>, /* GICR */ 1580 <0x31000000 0x2000>, /* GICC */ 1581 <0x31010000 0x2000>, /* GICV */ 1582 <0x31020000 0x2000>; /* GICH */ 1583 #interrupt-cells = <3>; 1584 interrupt-controller; 1585 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1586 interrupt-parent = <&gic>; 1587 }; 1588 1589 ddrc: memory-controller@3d400000 { 1590 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; 1591 reg = <0x3d400000 0x400000>; 1592 clock-names = "core", "pll", "alt", "apb"; 1593 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, 1594 <&clk IMX8MQ_DRAM_PLL_OUT>, 1595 <&clk IMX8MQ_CLK_DRAM_ALT>, 1596 <&clk IMX8MQ_CLK_DRAM_APB>; 1597 status = "disabled"; 1598 }; 1599 1600 ddr-pmu@3d800000 { 1601 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1602 reg = <0x3d800000 0x400000>; 1603 interrupt-parent = <&gic>; 1604 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1605 }; 1606 }; 1607}; 1608