1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7#include <dt-bindings/clock/imx8mq-clock.h> 8#include <dt-bindings/power/imx8mq-power.h> 9#include <dt-bindings/reset/imx8mq-reset.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "dt-bindings/input/input.h" 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/interconnect/imx8mq.h> 15#include "imx8mq-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gpc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ethernet0 = &fec1; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 mmc0 = &usdhc1; 35 mmc1 = &usdhc2; 36 serial0 = &uart1; 37 serial1 = &uart2; 38 serial2 = &uart3; 39 serial3 = &uart4; 40 spi0 = &ecspi1; 41 spi1 = &ecspi2; 42 spi2 = &ecspi3; 43 }; 44 45 ckil: clock-ckil { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <32768>; 49 clock-output-names = "ckil"; 50 }; 51 52 osc_25m: clock-osc-25m { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 clock-output-names = "osc_25m"; 57 }; 58 59 osc_27m: clock-osc-27m { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <27000000>; 63 clock-output-names = "osc_27m"; 64 }; 65 66 hdmi_phy_27m: clock-hdmi-phy-27m { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <27000000>; 70 clock-output-names = "hdmi_phy_27m"; 71 }; 72 73 clk_ext1: clock-ext1 { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <133000000>; 77 clock-output-names = "clk_ext1"; 78 }; 79 80 clk_ext2: clock-ext2 { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <133000000>; 84 clock-output-names = "clk_ext2"; 85 }; 86 87 clk_ext3: clock-ext3 { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <133000000>; 91 clock-output-names = "clk_ext3"; 92 }; 93 94 clk_ext4: clock-ext4 { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <133000000>; 98 clock-output-names = "clk_ext4"; 99 }; 100 101 cpus { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 105 A53_0: cpu@0 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0>; 109 clock-latency = <61036>; /* two CLK32 periods */ 110 clocks = <&clk IMX8MQ_CLK_ARM>; 111 enable-method = "psci"; 112 i-cache-size = <0x8000>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <256>; 115 d-cache-size = <0x8000>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <128>; 118 next-level-cache = <&A53_L2>; 119 operating-points-v2 = <&a53_opp_table>; 120 #cooling-cells = <2>; 121 nvmem-cells = <&cpu_speed_grade>; 122 nvmem-cell-names = "speed_grade"; 123 }; 124 125 A53_1: cpu@1 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53"; 128 reg = <0x1>; 129 clock-latency = <61036>; /* two CLK32 periods */ 130 clocks = <&clk IMX8MQ_CLK_ARM>; 131 enable-method = "psci"; 132 i-cache-size = <0x8000>; 133 i-cache-line-size = <64>; 134 i-cache-sets = <256>; 135 d-cache-size = <0x8000>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <128>; 138 next-level-cache = <&A53_L2>; 139 operating-points-v2 = <&a53_opp_table>; 140 #cooling-cells = <2>; 141 }; 142 143 A53_2: cpu@2 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a53"; 146 reg = <0x2>; 147 clock-latency = <61036>; /* two CLK32 periods */ 148 clocks = <&clk IMX8MQ_CLK_ARM>; 149 enable-method = "psci"; 150 i-cache-size = <0x8000>; 151 i-cache-line-size = <64>; 152 i-cache-sets = <256>; 153 d-cache-size = <0x8000>; 154 d-cache-line-size = <64>; 155 d-cache-sets = <128>; 156 next-level-cache = <&A53_L2>; 157 operating-points-v2 = <&a53_opp_table>; 158 #cooling-cells = <2>; 159 }; 160 161 A53_3: cpu@3 { 162 device_type = "cpu"; 163 compatible = "arm,cortex-a53"; 164 reg = <0x3>; 165 clock-latency = <61036>; /* two CLK32 periods */ 166 clocks = <&clk IMX8MQ_CLK_ARM>; 167 enable-method = "psci"; 168 i-cache-size = <0x8000>; 169 i-cache-line-size = <64>; 170 i-cache-sets = <256>; 171 d-cache-size = <0x8000>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 next-level-cache = <&A53_L2>; 175 operating-points-v2 = <&a53_opp_table>; 176 #cooling-cells = <2>; 177 }; 178 179 A53_L2: l2-cache0 { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-unified; 183 cache-size = <0x100000>; 184 cache-line-size = <64>; 185 cache-sets = <1024>; 186 }; 187 }; 188 189 a53_opp_table: opp-table { 190 compatible = "operating-points-v2"; 191 opp-shared; 192 193 opp-800000000 { 194 opp-hz = /bits/ 64 <800000000>; 195 opp-microvolt = <900000>; 196 /* Industrial only */ 197 opp-supported-hw = <0xf>, <0x4>; 198 clock-latency-ns = <150000>; 199 opp-suspend; 200 }; 201 202 opp-1000000000 { 203 opp-hz = /bits/ 64 <1000000000>; 204 opp-microvolt = <900000>; 205 /* Consumer only */ 206 opp-supported-hw = <0xe>, <0x3>; 207 clock-latency-ns = <150000>; 208 opp-suspend; 209 }; 210 211 opp-1300000000 { 212 opp-hz = /bits/ 64 <1300000000>; 213 opp-microvolt = <1000000>; 214 opp-supported-hw = <0xc>, <0x4>; 215 clock-latency-ns = <150000>; 216 opp-suspend; 217 }; 218 219 opp-1500000000 { 220 opp-hz = /bits/ 64 <1500000000>; 221 opp-microvolt = <1000000>; 222 opp-supported-hw = <0x8>, <0x3>; 223 clock-latency-ns = <150000>; 224 opp-suspend; 225 }; 226 }; 227 228 pmu { 229 compatible = "arm,cortex-a53-pmu"; 230 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-parent = <&gic>; 232 }; 233 234 psci { 235 compatible = "arm,psci-1.0"; 236 method = "smc"; 237 }; 238 239 thermal-zones { 240 cpu_thermal: cpu-thermal { 241 polling-delay-passive = <250>; 242 polling-delay = <2000>; 243 thermal-sensors = <&tmu 0>; 244 245 trips { 246 cpu_alert: cpu-alert { 247 temperature = <80000>; 248 hysteresis = <2000>; 249 type = "passive"; 250 }; 251 252 cpu-crit { 253 temperature = <90000>; 254 hysteresis = <2000>; 255 type = "critical"; 256 }; 257 }; 258 259 cooling-maps { 260 map0 { 261 trip = <&cpu_alert>; 262 cooling-device = 263 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 264 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 265 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 266 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 267 }; 268 }; 269 }; 270 271 gpu-thermal { 272 polling-delay-passive = <250>; 273 polling-delay = <2000>; 274 thermal-sensors = <&tmu 1>; 275 276 trips { 277 gpu_alert: gpu-alert { 278 temperature = <80000>; 279 hysteresis = <2000>; 280 type = "passive"; 281 }; 282 283 gpu-crit { 284 temperature = <90000>; 285 hysteresis = <2000>; 286 type = "critical"; 287 }; 288 }; 289 290 cooling-maps { 291 map0 { 292 trip = <&gpu_alert>; 293 cooling-device = 294 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 295 }; 296 }; 297 }; 298 299 vpu-thermal { 300 polling-delay-passive = <250>; 301 polling-delay = <2000>; 302 thermal-sensors = <&tmu 2>; 303 304 trips { 305 vpu-crit { 306 temperature = <90000>; 307 hysteresis = <2000>; 308 type = "critical"; 309 }; 310 }; 311 }; 312 }; 313 314 timer { 315 compatible = "arm,armv8-timer"; 316 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 317 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 318 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 319 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 320 interrupt-parent = <&gic>; 321 arm,no-tick-in-suspend; 322 }; 323 324 soc: soc@0 { 325 compatible = "fsl,imx8mq-soc", "simple-bus"; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 ranges = <0x0 0x0 0x0 0x3e000000>; 329 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 330 nvmem-cells = <&imx8mq_uid>; 331 nvmem-cell-names = "soc_unique_id"; 332 333 aips1: bus@30000000 { /* AIPS1 */ 334 compatible = "fsl,aips-bus", "simple-bus"; 335 reg = <0x30000000 0x400000>; 336 #address-cells = <1>; 337 #size-cells = <1>; 338 ranges = <0x30000000 0x30000000 0x400000>; 339 340 sai1: sai@30010000 { 341 #sound-dai-cells = <0>; 342 compatible = "fsl,imx8mq-sai"; 343 reg = <0x30010000 0x10000>; 344 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, 346 <&clk IMX8MQ_CLK_SAI1_ROOT>, 347 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 348 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 349 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 }; 353 354 sai6: sai@30030000 { 355 #sound-dai-cells = <0>; 356 compatible = "fsl,imx8mq-sai"; 357 reg = <0x30030000 0x10000>; 358 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, 360 <&clk IMX8MQ_CLK_SAI6_ROOT>, 361 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 362 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 363 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; 364 dma-names = "rx", "tx"; 365 status = "disabled"; 366 }; 367 368 sai5: sai@30040000 { 369 #sound-dai-cells = <0>; 370 compatible = "fsl,imx8mq-sai"; 371 reg = <0x30040000 0x10000>; 372 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, 374 <&clk IMX8MQ_CLK_SAI5_ROOT>, 375 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 376 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 377 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; 378 dma-names = "rx", "tx"; 379 status = "disabled"; 380 }; 381 382 sai4: sai@30050000 { 383 #sound-dai-cells = <0>; 384 compatible = "fsl,imx8mq-sai"; 385 reg = <0x30050000 0x10000>; 386 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, 388 <&clk IMX8MQ_CLK_SAI4_ROOT>, 389 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 390 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 391 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; 392 dma-names = "rx", "tx"; 393 status = "disabled"; 394 }; 395 396 gpio1: gpio@30200000 { 397 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 398 reg = <0x30200000 0x10000>; 399 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 gpio-ranges = <&iomuxc 0 10 30>; 407 }; 408 409 gpio2: gpio@30210000 { 410 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 411 reg = <0x30210000 0x10000>; 412 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; 415 gpio-controller; 416 #gpio-cells = <2>; 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 gpio-ranges = <&iomuxc 0 40 21>; 420 }; 421 422 gpio3: gpio@30220000 { 423 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 424 reg = <0x30220000 0x10000>; 425 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; 428 gpio-controller; 429 #gpio-cells = <2>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 gpio-ranges = <&iomuxc 0 61 26>; 433 }; 434 435 gpio4: gpio@30230000 { 436 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 437 reg = <0x30230000 0x10000>; 438 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 gpio-ranges = <&iomuxc 0 87 32>; 446 }; 447 448 gpio5: gpio@30240000 { 449 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 450 reg = <0x30240000 0x10000>; 451 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; 454 gpio-controller; 455 #gpio-cells = <2>; 456 interrupt-controller; 457 #interrupt-cells = <2>; 458 gpio-ranges = <&iomuxc 0 119 30>; 459 }; 460 461 tmu: tmu@30260000 { 462 compatible = "fsl,imx8mq-tmu"; 463 reg = <0x30260000 0x10000>; 464 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; 466 little-endian; 467 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 468 fsl,tmu-calibration = <0x00000000 0x00000023>, 469 <0x00000001 0x00000029>, 470 <0x00000002 0x0000002f>, 471 <0x00000003 0x00000035>, 472 <0x00000004 0x0000003d>, 473 <0x00000005 0x00000043>, 474 <0x00000006 0x0000004b>, 475 <0x00000007 0x00000051>, 476 <0x00000008 0x00000057>, 477 <0x00000009 0x0000005f>, 478 <0x0000000a 0x00000067>, 479 <0x0000000b 0x0000006f>, 480 481 <0x00010000 0x0000001b>, 482 <0x00010001 0x00000023>, 483 <0x00010002 0x0000002b>, 484 <0x00010003 0x00000033>, 485 <0x00010004 0x0000003b>, 486 <0x00010005 0x00000043>, 487 <0x00010006 0x0000004b>, 488 <0x00010007 0x00000055>, 489 <0x00010008 0x0000005d>, 490 <0x00010009 0x00000067>, 491 <0x0001000a 0x00000070>, 492 493 <0x00020000 0x00000017>, 494 <0x00020001 0x00000023>, 495 <0x00020002 0x0000002d>, 496 <0x00020003 0x00000037>, 497 <0x00020004 0x00000041>, 498 <0x00020005 0x0000004b>, 499 <0x00020006 0x00000057>, 500 <0x00020007 0x00000063>, 501 <0x00020008 0x0000006f>, 502 503 <0x00030000 0x00000015>, 504 <0x00030001 0x00000021>, 505 <0x00030002 0x0000002d>, 506 <0x00030003 0x00000039>, 507 <0x00030004 0x00000045>, 508 <0x00030005 0x00000053>, 509 <0x00030006 0x0000005f>, 510 <0x00030007 0x00000071>; 511 #thermal-sensor-cells = <1>; 512 }; 513 514 wdog1: watchdog@30280000 { 515 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 516 reg = <0x30280000 0x10000>; 517 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; 519 status = "disabled"; 520 }; 521 522 wdog2: watchdog@30290000 { 523 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 524 reg = <0x30290000 0x10000>; 525 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; 527 status = "disabled"; 528 }; 529 530 wdog3: watchdog@302a0000 { 531 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 532 reg = <0x302a0000 0x10000>; 533 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; 535 status = "disabled"; 536 }; 537 538 sdma2: dma-controller@302c0000 { 539 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 540 reg = <0x302c0000 0x10000>; 541 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, 543 <&clk IMX8MQ_CLK_SDMA2_ROOT>; 544 clock-names = "ipg", "ahb"; 545 #dma-cells = <3>; 546 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 547 }; 548 549 lcdif: lcd-controller@30320000 { 550 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif"; 551 reg = <0x30320000 0x10000>; 552 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 554 clock-names = "pix"; 555 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 556 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 557 <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 558 <&clk IMX8MQ_VIDEO_PLL1>; 559 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 560 <&clk IMX8MQ_VIDEO_PLL1>, 561 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 562 assigned-clock-rates = <0>, <0>, <0>, <594000000>; 563 status = "disabled"; 564 565 port { 566 lcdif_mipi_dsi: endpoint { 567 remote-endpoint = <&mipi_dsi_lcdif_in>; 568 }; 569 }; 570 }; 571 572 iomuxc: pinctrl@30330000 { 573 compatible = "fsl,imx8mq-iomuxc"; 574 reg = <0x30330000 0x10000>; 575 }; 576 577 iomuxc_gpr: syscon@30340000 { 578 compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd"; 579 reg = <0x30340000 0x10000>; 580 581 mux: mux-controller { 582 compatible = "mmio-mux"; 583 #mux-control-cells = <1>; 584 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ 585 }; 586 }; 587 588 ocotp: efuse@30350000 { 589 compatible = "fsl,imx8mq-ocotp", "syscon"; 590 reg = <0x30350000 0x10000>; 591 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 592 #address-cells = <1>; 593 #size-cells = <1>; 594 595 /* 596 * The register address below maps to the MX8M 597 * Fusemap Description Table entries this way. 598 * Assuming 599 * reg = <ADDR SIZE>; 600 * then 601 * Fuse Address = (ADDR * 4) + 0x400 602 * Note that if SIZE is greater than 4, then 603 * each subsequent fuse is located at offset 604 * +0x10 in Fusemap Description Table (e.g. 605 * reg = <0x4 0x8> describes fuses 0x410 and 606 * 0x420). 607 */ 608 imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */ 609 reg = <0x4 0x8>; 610 }; 611 612 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 613 reg = <0x10 4>; 614 }; 615 616 fec_mac_address: mac-address@90 { /* 0x640 */ 617 reg = <0x90 6>; 618 }; 619 }; 620 621 anatop: clock-controller@30360000 { 622 compatible = "fsl,imx8mq-anatop"; 623 reg = <0x30360000 0x10000>; 624 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 625 #clock-cells = <1>; 626 }; 627 628 snvs: snvs@30370000 { 629 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 630 reg = <0x30370000 0x10000>; 631 632 snvs_rtc: snvs-rtc-lp{ 633 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 634 regmap =<&snvs>; 635 offset = <0x34>; 636 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 639 clock-names = "snvs-rtc"; 640 }; 641 642 snvs_pwrkey: snvs-powerkey { 643 compatible = "fsl,sec-v4.0-pwrkey"; 644 regmap = <&snvs>; 645 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 647 clock-names = "snvs-pwrkey"; 648 linux,keycode = <KEY_POWER>; 649 wakeup-source; 650 status = "disabled"; 651 }; 652 }; 653 654 clk: clock-controller@30380000 { 655 compatible = "fsl,imx8mq-ccm"; 656 reg = <0x30380000 0x10000>; 657 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 659 #clock-cells = <1>; 660 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, 661 <&clk_ext1>, <&clk_ext2>, 662 <&clk_ext3>, <&clk_ext4>; 663 clock-names = "ckil", "osc_25m", "osc_27m", 664 "clk_ext1", "clk_ext2", 665 "clk_ext3", "clk_ext4"; 666 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, 667 <&clk IMX8MQ_CLK_A53_CORE>, 668 <&clk IMX8MQ_CLK_NOC>, 669 <&clk IMX8MQ_CLK_AUDIO_AHB>, 670 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, 671 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, 672 <&clk IMX8MQ_AUDIO_PLL1>, 673 <&clk IMX8MQ_AUDIO_PLL2>; 674 assigned-clock-rates = <0>, <0>, 675 <800000000>, 676 <0>, 677 <0>, 678 <0>, 679 <786432000>, 680 <722534400>; 681 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, 682 <&clk IMX8MQ_ARM_PLL_OUT>, 683 <0>, 684 <&clk IMX8MQ_SYS2_PLL_500M>, 685 <&clk IMX8MQ_AUDIO_PLL1>, 686 <&clk IMX8MQ_AUDIO_PLL2>; 687 }; 688 689 src: reset-controller@30390000 { 690 compatible = "fsl,imx8mq-src", "syscon"; 691 reg = <0x30390000 0x10000>; 692 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 693 #reset-cells = <1>; 694 }; 695 696 gpc: gpc@303a0000 { 697 compatible = "fsl,imx8mq-gpc"; 698 reg = <0x303a0000 0x10000>; 699 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 700 interrupt-parent = <&gic>; 701 interrupt-controller; 702 #interrupt-cells = <3>; 703 704 pgc { 705 #address-cells = <1>; 706 #size-cells = <0>; 707 708 pgc_mipi: power-domain@0 { 709 #power-domain-cells = <0>; 710 reg = <IMX8M_POWER_DOMAIN_MIPI>; 711 }; 712 713 /* 714 * As per comment in ATF source code: 715 * 716 * PCIE1 and PCIE2 share the 717 * same reset signal, if we 718 * power down PCIE2, PCIE1 719 * will be held in reset too. 720 * 721 * So instead of creating two 722 * separate power domains for 723 * PCIE1 and PCIE2 we create a 724 * link between both and use 725 * it as a shared PCIE power 726 * domain. 727 */ 728 pgc_pcie: power-domain@1 { 729 #power-domain-cells = <0>; 730 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 731 power-domains = <&pgc_pcie2>; 732 }; 733 734 pgc_otg1: power-domain@2 { 735 #power-domain-cells = <0>; 736 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; 737 }; 738 739 pgc_otg2: power-domain@3 { 740 #power-domain-cells = <0>; 741 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; 742 }; 743 744 pgc_ddr1: power-domain@4 { 745 #power-domain-cells = <0>; 746 reg = <IMX8M_POWER_DOMAIN_DDR1>; 747 }; 748 749 pgc_gpu: power-domain@5 { 750 #power-domain-cells = <0>; 751 reg = <IMX8M_POWER_DOMAIN_GPU>; 752 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 753 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 754 <&clk IMX8MQ_CLK_GPU_AXI>, 755 <&clk IMX8MQ_CLK_GPU_AHB>; 756 }; 757 758 pgc_vpu: power-domain@6 { 759 #power-domain-cells = <0>; 760 reg = <IMX8M_POWER_DOMAIN_VPU>; 761 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, 762 <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 763 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 764 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, 765 <&clk IMX8MQ_CLK_VPU_G2>, 766 <&clk IMX8MQ_CLK_VPU_BUS>, 767 <&clk IMX8MQ_VPU_PLL_BYPASS>; 768 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, 769 <&clk IMX8MQ_VPU_PLL_OUT>, 770 <&clk IMX8MQ_SYS1_PLL_800M>, 771 <&clk IMX8MQ_VPU_PLL>; 772 assigned-clock-rates = <600000000>, 773 <600000000>, 774 <800000000>, 775 <0>; 776 }; 777 778 pgc_disp: power-domain@7 { 779 #power-domain-cells = <0>; 780 reg = <IMX8M_POWER_DOMAIN_DISP>; 781 }; 782 783 pgc_mipi_csi1: power-domain@8 { 784 #power-domain-cells = <0>; 785 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; 786 }; 787 788 pgc_mipi_csi2: power-domain@9 { 789 #power-domain-cells = <0>; 790 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; 791 }; 792 793 pgc_pcie2: power-domain@a { 794 #power-domain-cells = <0>; 795 reg = <IMX8M_POWER_DOMAIN_PCIE2>; 796 }; 797 }; 798 }; 799 }; 800 801 aips2: bus@30400000 { /* AIPS2 */ 802 compatible = "fsl,aips-bus", "simple-bus"; 803 reg = <0x30400000 0x400000>; 804 #address-cells = <1>; 805 #size-cells = <1>; 806 ranges = <0x30400000 0x30400000 0x400000>; 807 808 pwm1: pwm@30660000 { 809 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 810 reg = <0x30660000 0x10000>; 811 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, 813 <&clk IMX8MQ_CLK_PWM1_ROOT>; 814 clock-names = "ipg", "per"; 815 #pwm-cells = <3>; 816 status = "disabled"; 817 }; 818 819 pwm2: pwm@30670000 { 820 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 821 reg = <0x30670000 0x10000>; 822 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, 824 <&clk IMX8MQ_CLK_PWM2_ROOT>; 825 clock-names = "ipg", "per"; 826 #pwm-cells = <3>; 827 status = "disabled"; 828 }; 829 830 pwm3: pwm@30680000 { 831 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 832 reg = <0x30680000 0x10000>; 833 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 834 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, 835 <&clk IMX8MQ_CLK_PWM3_ROOT>; 836 clock-names = "ipg", "per"; 837 #pwm-cells = <3>; 838 status = "disabled"; 839 }; 840 841 pwm4: pwm@30690000 { 842 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 843 reg = <0x30690000 0x10000>; 844 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, 846 <&clk IMX8MQ_CLK_PWM4_ROOT>; 847 clock-names = "ipg", "per"; 848 #pwm-cells = <3>; 849 status = "disabled"; 850 }; 851 852 system_counter: timer@306a0000 { 853 compatible = "nxp,sysctr-timer"; 854 reg = <0x306a0000 0x20000>; 855 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&osc_25m>; 857 clock-names = "per"; 858 }; 859 }; 860 861 aips3: bus@30800000 { /* AIPS3 */ 862 compatible = "fsl,aips-bus", "simple-bus"; 863 reg = <0x30800000 0x400000>; 864 #address-cells = <1>; 865 #size-cells = <1>; 866 ranges = <0x30800000 0x30800000 0x400000>, 867 <0x08000000 0x08000000 0x10000000>; 868 869 spdif1: spdif@30810000 { 870 compatible = "fsl,imx35-spdif"; 871 reg = <0x30810000 0x10000>; 872 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 874 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 875 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ 876 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 877 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 878 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 879 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 880 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 881 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 882 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 883 clock-names = "core", "rxtx0", 884 "rxtx1", "rxtx2", 885 "rxtx3", "rxtx4", 886 "rxtx5", "rxtx6", 887 "rxtx7", "spba"; 888 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; 889 dma-names = "rx", "tx"; 890 status = "disabled"; 891 }; 892 893 ecspi1: spi@30820000 { 894 #address-cells = <1>; 895 #size-cells = <0>; 896 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 897 reg = <0x30820000 0x10000>; 898 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, 900 <&clk IMX8MQ_CLK_ECSPI1_ROOT>; 901 clock-names = "ipg", "per"; 902 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 903 dma-names = "rx", "tx"; 904 status = "disabled"; 905 }; 906 907 ecspi2: spi@30830000 { 908 #address-cells = <1>; 909 #size-cells = <0>; 910 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 911 reg = <0x30830000 0x10000>; 912 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, 914 <&clk IMX8MQ_CLK_ECSPI2_ROOT>; 915 clock-names = "ipg", "per"; 916 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 917 dma-names = "rx", "tx"; 918 status = "disabled"; 919 }; 920 921 ecspi3: spi@30840000 { 922 #address-cells = <1>; 923 #size-cells = <0>; 924 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 925 reg = <0x30840000 0x10000>; 926 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, 928 <&clk IMX8MQ_CLK_ECSPI3_ROOT>; 929 clock-names = "ipg", "per"; 930 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 931 dma-names = "rx", "tx"; 932 status = "disabled"; 933 }; 934 935 uart1: serial@30860000 { 936 compatible = "fsl,imx8mq-uart", 937 "fsl,imx6q-uart"; 938 reg = <0x30860000 0x10000>; 939 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, 941 <&clk IMX8MQ_CLK_UART1_ROOT>; 942 clock-names = "ipg", "per"; 943 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 944 dma-names = "rx", "tx"; 945 status = "disabled"; 946 }; 947 948 uart3: serial@30880000 { 949 compatible = "fsl,imx8mq-uart", 950 "fsl,imx6q-uart"; 951 reg = <0x30880000 0x10000>; 952 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 953 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, 954 <&clk IMX8MQ_CLK_UART3_ROOT>; 955 clock-names = "ipg", "per"; 956 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 957 dma-names = "rx", "tx"; 958 status = "disabled"; 959 }; 960 961 uart2: serial@30890000 { 962 compatible = "fsl,imx8mq-uart", 963 "fsl,imx6q-uart"; 964 reg = <0x30890000 0x10000>; 965 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, 967 <&clk IMX8MQ_CLK_UART2_ROOT>; 968 clock-names = "ipg", "per"; 969 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 970 dma-names = "rx", "tx"; 971 status = "disabled"; 972 }; 973 974 spdif2: spdif@308a0000 { 975 compatible = "fsl,imx35-spdif"; 976 reg = <0x308a0000 0x10000>; 977 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 979 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 980 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ 981 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 982 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 983 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 984 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 985 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 986 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 987 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 988 clock-names = "core", "rxtx0", 989 "rxtx1", "rxtx2", 990 "rxtx3", "rxtx4", 991 "rxtx5", "rxtx6", 992 "rxtx7", "spba"; 993 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; 994 dma-names = "rx", "tx"; 995 status = "disabled"; 996 }; 997 998 sai2: sai@308b0000 { 999 #sound-dai-cells = <0>; 1000 compatible = "fsl,imx8mq-sai"; 1001 reg = <0x308b0000 0x10000>; 1002 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1003 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, 1004 <&clk IMX8MQ_CLK_SAI2_ROOT>, 1005 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 1006 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1007 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; 1008 dma-names = "rx", "tx"; 1009 status = "disabled"; 1010 }; 1011 1012 sai3: sai@308c0000 { 1013 #sound-dai-cells = <0>; 1014 compatible = "fsl,imx8mq-sai"; 1015 reg = <0x308c0000 0x10000>; 1016 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, 1018 <&clk IMX8MQ_CLK_SAI3_ROOT>, 1019 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 1020 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1021 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; 1022 dma-names = "rx", "tx"; 1023 status = "disabled"; 1024 }; 1025 1026 crypto: crypto@30900000 { 1027 compatible = "fsl,sec-v4.0"; 1028 #address-cells = <1>; 1029 #size-cells = <1>; 1030 reg = <0x30900000 0x40000>; 1031 ranges = <0 0x30900000 0x40000>; 1032 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&clk IMX8MQ_CLK_AHB>, 1034 <&clk IMX8MQ_CLK_IPG_ROOT>; 1035 clock-names = "aclk", "ipg"; 1036 1037 sec_jr0: jr@1000 { 1038 compatible = "fsl,sec-v4.0-job-ring"; 1039 reg = <0x1000 0x1000>; 1040 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1041 status = "disabled"; 1042 }; 1043 1044 sec_jr1: jr@2000 { 1045 compatible = "fsl,sec-v4.0-job-ring"; 1046 reg = <0x2000 0x1000>; 1047 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1048 }; 1049 1050 sec_jr2: jr@3000 { 1051 compatible = "fsl,sec-v4.0-job-ring"; 1052 reg = <0x3000 0x1000>; 1053 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1054 }; 1055 }; 1056 1057 mipi_dsi: mipi-dsi@30a00000 { 1058 compatible = "fsl,imx8mq-nwl-dsi"; 1059 reg = <0x30a00000 0x300>; 1060 clocks = <&clk IMX8MQ_CLK_DSI_CORE>, 1061 <&clk IMX8MQ_CLK_DSI_AHB>, 1062 <&clk IMX8MQ_CLK_DSI_IPG_DIV>, 1063 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1064 <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 1065 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; 1066 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, 1067 <&clk IMX8MQ_CLK_DSI_CORE>, 1068 <&clk IMX8MQ_CLK_DSI_IPG_DIV>; 1069 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, 1070 <&clk IMX8MQ_SYS1_PLL_266M>; 1071 assigned-clock-rates = <80000000>, <266000000>, <20000000>; 1072 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1073 mux-controls = <&mux 0>; 1074 power-domains = <&pgc_mipi>; 1075 phys = <&dphy>; 1076 phy-names = "dphy"; 1077 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, 1078 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, 1079 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, 1080 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; 1081 reset-names = "byte", "dpi", "esc", "pclk"; 1082 status = "disabled"; 1083 1084 ports { 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 1088 port@0 { 1089 reg = <0>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 mipi_dsi_lcdif_in: endpoint@0 { 1093 reg = <0>; 1094 remote-endpoint = <&lcdif_mipi_dsi>; 1095 }; 1096 }; 1097 }; 1098 }; 1099 1100 dphy: dphy@30a00300 { 1101 compatible = "fsl,imx8mq-mipi-dphy"; 1102 reg = <0x30a00300 0x100>; 1103 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 1104 clock-names = "phy_ref"; 1105 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 1106 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 1107 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1108 <&clk IMX8MQ_VIDEO_PLL1>; 1109 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 1110 <&clk IMX8MQ_VIDEO_PLL1>, 1111 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 1112 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; 1113 #phy-cells = <0>; 1114 power-domains = <&pgc_mipi>; 1115 status = "disabled"; 1116 }; 1117 1118 i2c1: i2c@30a20000 { 1119 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1120 reg = <0x30a20000 0x10000>; 1121 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 i2c2: i2c@30a30000 { 1129 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1130 reg = <0x30a30000 0x10000>; 1131 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 status = "disabled"; 1136 }; 1137 1138 i2c3: i2c@30a40000 { 1139 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1140 reg = <0x30a40000 0x10000>; 1141 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 status = "disabled"; 1146 }; 1147 1148 i2c4: i2c@30a50000 { 1149 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1150 reg = <0x30a50000 0x10000>; 1151 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 uart4: serial@30a60000 { 1159 compatible = "fsl,imx8mq-uart", 1160 "fsl,imx6q-uart"; 1161 reg = <0x30a60000 0x10000>; 1162 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, 1164 <&clk IMX8MQ_CLK_UART4_ROOT>; 1165 clock-names = "ipg", "per"; 1166 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1167 dma-names = "rx", "tx"; 1168 status = "disabled"; 1169 }; 1170 1171 mipi_csi1: csi@30a70000 { 1172 compatible = "fsl,imx8mq-mipi-csi2"; 1173 reg = <0x30a70000 0x1000>; 1174 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1175 <&clk IMX8MQ_CLK_CSI1_ESC>, 1176 <&clk IMX8MQ_CLK_CSI1_PHY_REF>; 1177 clock-names = "core", "esc", "ui"; 1178 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1179 <&clk IMX8MQ_CLK_CSI1_PHY_REF>, 1180 <&clk IMX8MQ_CLK_CSI1_ESC>; 1181 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1182 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1183 <&clk IMX8MQ_SYS2_PLL_1000M>, 1184 <&clk IMX8MQ_SYS1_PLL_800M>; 1185 power-domains = <&pgc_mipi_csi1>; 1186 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, 1187 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, 1188 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; 1189 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; 1190 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; 1191 interconnect-names = "dram"; 1192 status = "disabled"; 1193 1194 ports { 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 1198 port@1 { 1199 reg = <1>; 1200 1201 csi1_mipi_ep: endpoint { 1202 remote-endpoint = <&csi1_ep>; 1203 }; 1204 }; 1205 }; 1206 }; 1207 1208 csi1: csi@30a90000 { 1209 compatible = "fsl,imx8mq-csi"; 1210 reg = <0x30a90000 0x10000>; 1211 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; 1213 clock-names = "mclk"; 1214 status = "disabled"; 1215 1216 port { 1217 csi1_ep: endpoint { 1218 remote-endpoint = <&csi1_mipi_ep>; 1219 }; 1220 }; 1221 }; 1222 1223 mipi_csi2: csi@30b60000 { 1224 compatible = "fsl,imx8mq-mipi-csi2"; 1225 reg = <0x30b60000 0x1000>; 1226 clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1227 <&clk IMX8MQ_CLK_CSI2_ESC>, 1228 <&clk IMX8MQ_CLK_CSI2_PHY_REF>; 1229 clock-names = "core", "esc", "ui"; 1230 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1231 <&clk IMX8MQ_CLK_CSI2_PHY_REF>, 1232 <&clk IMX8MQ_CLK_CSI2_ESC>; 1233 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1234 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1235 <&clk IMX8MQ_SYS2_PLL_1000M>, 1236 <&clk IMX8MQ_SYS1_PLL_800M>; 1237 power-domains = <&pgc_mipi_csi2>; 1238 resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, 1239 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, 1240 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; 1241 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; 1242 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; 1243 interconnect-names = "dram"; 1244 status = "disabled"; 1245 1246 ports { 1247 #address-cells = <1>; 1248 #size-cells = <0>; 1249 1250 port@1 { 1251 reg = <1>; 1252 1253 csi2_mipi_ep: endpoint { 1254 remote-endpoint = <&csi2_ep>; 1255 }; 1256 }; 1257 }; 1258 }; 1259 1260 csi2: csi@30b80000 { 1261 compatible = "fsl,imx8mq-csi"; 1262 reg = <0x30b80000 0x10000>; 1263 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; 1265 clock-names = "mclk"; 1266 status = "disabled"; 1267 1268 port { 1269 csi2_ep: endpoint { 1270 remote-endpoint = <&csi2_mipi_ep>; 1271 }; 1272 }; 1273 }; 1274 1275 mu: mailbox@30aa0000 { 1276 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; 1277 reg = <0x30aa0000 0x10000>; 1278 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1279 clocks = <&clk IMX8MQ_CLK_MU_ROOT>; 1280 #mbox-cells = <2>; 1281 }; 1282 1283 usdhc1: mmc@30b40000 { 1284 compatible = "fsl,imx8mq-usdhc", 1285 "fsl,imx7d-usdhc"; 1286 reg = <0x30b40000 0x10000>; 1287 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1289 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1290 <&clk IMX8MQ_CLK_USDHC1_ROOT>; 1291 clock-names = "ipg", "ahb", "per"; 1292 fsl,tuning-start-tap = <20>; 1293 fsl,tuning-step = <2>; 1294 bus-width = <4>; 1295 status = "disabled"; 1296 }; 1297 1298 usdhc2: mmc@30b50000 { 1299 compatible = "fsl,imx8mq-usdhc", 1300 "fsl,imx7d-usdhc"; 1301 reg = <0x30b50000 0x10000>; 1302 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1304 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1305 <&clk IMX8MQ_CLK_USDHC2_ROOT>; 1306 clock-names = "ipg", "ahb", "per"; 1307 fsl,tuning-start-tap = <20>; 1308 fsl,tuning-step = <2>; 1309 bus-width = <4>; 1310 status = "disabled"; 1311 }; 1312 1313 qspi0: spi@30bb0000 { 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; 1317 reg = <0x30bb0000 0x10000>, 1318 <0x08000000 0x10000000>; 1319 reg-names = "QuadSPI", "QuadSPI-memory"; 1320 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1321 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, 1322 <&clk IMX8MQ_CLK_QSPI_ROOT>; 1323 clock-names = "qspi_en", "qspi"; 1324 status = "disabled"; 1325 }; 1326 1327 sdma1: dma-controller@30bd0000 { 1328 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 1329 reg = <0x30bd0000 0x10000>; 1330 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1331 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, 1332 <&clk IMX8MQ_CLK_AHB>; 1333 clock-names = "ipg", "ahb"; 1334 #dma-cells = <3>; 1335 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1336 }; 1337 1338 fec1: ethernet@30be0000 { 1339 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1340 reg = <0x30be0000 0x10000>; 1341 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1345 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, 1346 <&clk IMX8MQ_CLK_ENET1_ROOT>, 1347 <&clk IMX8MQ_CLK_ENET_TIMER>, 1348 <&clk IMX8MQ_CLK_ENET_REF>, 1349 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1350 clock-names = "ipg", "ahb", "ptp", 1351 "enet_clk_ref", "enet_out"; 1352 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, 1353 <&clk IMX8MQ_CLK_ENET_TIMER>, 1354 <&clk IMX8MQ_CLK_ENET_REF>, 1355 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1356 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1357 <&clk IMX8MQ_SYS2_PLL_100M>, 1358 <&clk IMX8MQ_SYS2_PLL_125M>, 1359 <&clk IMX8MQ_SYS2_PLL_50M>; 1360 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1361 fsl,num-tx-queues = <3>; 1362 fsl,num-rx-queues = <3>; 1363 nvmem-cells = <&fec_mac_address>; 1364 nvmem-cell-names = "mac-address"; 1365 fsl,stop-mode = <&iomuxc_gpr 0x10 3>; 1366 status = "disabled"; 1367 }; 1368 }; 1369 1370 noc: interconnect@32700000 { 1371 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; 1372 reg = <0x32700000 0x100000>; 1373 clocks = <&clk IMX8MQ_CLK_NOC>; 1374 fsl,ddrc = <&ddrc>; 1375 #interconnect-cells = <1>; 1376 operating-points-v2 = <&noc_opp_table>; 1377 1378 noc_opp_table: opp-table { 1379 compatible = "operating-points-v2"; 1380 1381 opp-133000000 { 1382 opp-hz = /bits/ 64 <133333333>; 1383 }; 1384 1385 opp-400000000 { 1386 opp-hz = /bits/ 64 <400000000>; 1387 }; 1388 1389 opp-800000000 { 1390 opp-hz = /bits/ 64 <800000000>; 1391 }; 1392 }; 1393 }; 1394 1395 aips4: bus@32c00000 { /* AIPS4 */ 1396 compatible = "fsl,aips-bus", "simple-bus"; 1397 reg = <0x32c00000 0x400000>; 1398 #address-cells = <1>; 1399 #size-cells = <1>; 1400 ranges = <0x32c00000 0x32c00000 0x400000>; 1401 1402 irqsteer: interrupt-controller@32e2d000 { 1403 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; 1404 reg = <0x32e2d000 0x1000>; 1405 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 1407 clock-names = "ipg"; 1408 fsl,channel = <0>; 1409 fsl,num-irqs = <64>; 1410 interrupt-controller; 1411 #interrupt-cells = <1>; 1412 }; 1413 }; 1414 1415 gpu: gpu@38000000 { 1416 compatible = "vivante,gc"; 1417 reg = <0x38000000 0x40000>; 1418 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1419 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 1420 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 1421 <&clk IMX8MQ_CLK_GPU_AXI>, 1422 <&clk IMX8MQ_CLK_GPU_AHB>; 1423 clock-names = "core", "shader", "bus", "reg"; 1424 #cooling-cells = <2>; 1425 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, 1426 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, 1427 <&clk IMX8MQ_CLK_GPU_AXI>, 1428 <&clk IMX8MQ_CLK_GPU_AHB>, 1429 <&clk IMX8MQ_GPU_PLL_BYPASS>; 1430 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, 1431 <&clk IMX8MQ_GPU_PLL_OUT>, 1432 <&clk IMX8MQ_GPU_PLL_OUT>, 1433 <&clk IMX8MQ_GPU_PLL_OUT>, 1434 <&clk IMX8MQ_GPU_PLL>; 1435 assigned-clock-rates = <800000000>, <800000000>, 1436 <800000000>, <800000000>, <0>; 1437 power-domains = <&pgc_gpu>; 1438 }; 1439 1440 usb_dwc3_0: usb@38100000 { 1441 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1442 reg = <0x38100000 0x10000>; 1443 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, 1444 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1445 <&clk IMX8MQ_CLK_32K>; 1446 clock-names = "bus_early", "ref", "suspend"; 1447 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1448 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1449 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1450 <&clk IMX8MQ_SYS1_PLL_100M>; 1451 assigned-clock-rates = <500000000>, <100000000>; 1452 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1453 phys = <&usb3_phy0>, <&usb3_phy0>; 1454 phy-names = "usb2-phy", "usb3-phy"; 1455 power-domains = <&pgc_otg1>; 1456 status = "disabled"; 1457 }; 1458 1459 usb3_phy0: usb-phy@381f0040 { 1460 compatible = "fsl,imx8mq-usb-phy"; 1461 reg = <0x381f0040 0x40>; 1462 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 1463 clock-names = "phy"; 1464 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1465 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1466 assigned-clock-rates = <100000000>; 1467 #phy-cells = <0>; 1468 status = "disabled"; 1469 }; 1470 1471 usb_dwc3_1: usb@38200000 { 1472 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1473 reg = <0x38200000 0x10000>; 1474 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, 1475 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1476 <&clk IMX8MQ_CLK_32K>; 1477 clock-names = "bus_early", "ref", "suspend"; 1478 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1479 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1480 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1481 <&clk IMX8MQ_SYS1_PLL_100M>; 1482 assigned-clock-rates = <500000000>, <100000000>; 1483 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1484 phys = <&usb3_phy1>, <&usb3_phy1>; 1485 phy-names = "usb2-phy", "usb3-phy"; 1486 power-domains = <&pgc_otg2>; 1487 status = "disabled"; 1488 }; 1489 1490 usb3_phy1: usb-phy@382f0040 { 1491 compatible = "fsl,imx8mq-usb-phy"; 1492 reg = <0x382f0040 0x40>; 1493 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; 1494 clock-names = "phy"; 1495 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1496 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1497 assigned-clock-rates = <100000000>; 1498 #phy-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 vpu_g1: video-codec@38300000 { 1503 compatible = "nxp,imx8mq-vpu-g1"; 1504 reg = <0x38300000 0x10000>; 1505 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1506 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; 1507 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; 1508 }; 1509 1510 vpu_g2: video-codec@38310000 { 1511 compatible = "nxp,imx8mq-vpu-g2"; 1512 reg = <0x38310000 0x10000>; 1513 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1514 clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1515 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; 1516 }; 1517 1518 vpu_blk_ctrl: blk-ctrl@38320000 { 1519 compatible = "fsl,imx8mq-vpu-blk-ctrl"; 1520 reg = <0x38320000 0x100>; 1521 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; 1522 power-domain-names = "bus", "g1", "g2"; 1523 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 1524 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1525 clock-names = "g1", "g2"; 1526 #power-domain-cells = <1>; 1527 }; 1528 1529 pcie0: pcie@33800000 { 1530 compatible = "fsl,imx8mq-pcie"; 1531 reg = <0x33800000 0x400000>, 1532 <0x1ff00000 0x80000>; 1533 reg-names = "dbi", "config"; 1534 #address-cells = <3>; 1535 #size-cells = <2>; 1536 device_type = "pci"; 1537 bus-range = <0x00 0xff>; 1538 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1539 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1540 num-lanes = <1>; 1541 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1542 interrupt-names = "msi"; 1543 #interrupt-cells = <1>; 1544 interrupt-map-mask = <0 0 0 0x7>; 1545 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1546 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1547 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1548 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1549 fsl,max-link-speed = <2>; 1550 linux,pci-domain = <0>; 1551 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 1552 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1553 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1554 <&clk IMX8MQ_CLK_PCIE1_AUX>; 1555 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1556 power-domains = <&pgc_pcie>; 1557 resets = <&src IMX8MQ_RESET_PCIEPHY>, 1558 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1559 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1560 reset-names = "pciephy", "apps", "turnoff"; 1561 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, 1562 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1563 <&clk IMX8MQ_CLK_PCIE1_AUX>; 1564 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1565 <&clk IMX8MQ_SYS2_PLL_100M>, 1566 <&clk IMX8MQ_SYS1_PLL_80M>; 1567 assigned-clock-rates = <250000000>, <100000000>, 1568 <10000000>; 1569 status = "disabled"; 1570 }; 1571 1572 pcie1: pcie@33c00000 { 1573 compatible = "fsl,imx8mq-pcie"; 1574 reg = <0x33c00000 0x400000>, 1575 <0x27f00000 0x80000>; 1576 reg-names = "dbi", "config"; 1577 #address-cells = <3>; 1578 #size-cells = <2>; 1579 device_type = "pci"; 1580 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ 1581 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1582 num-lanes = <1>; 1583 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1584 interrupt-names = "msi"; 1585 #interrupt-cells = <1>; 1586 interrupt-map-mask = <0 0 0 0x7>; 1587 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1588 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1589 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1590 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1591 fsl,max-link-speed = <2>; 1592 linux,pci-domain = <1>; 1593 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 1594 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1595 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1596 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1597 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1598 power-domains = <&pgc_pcie>; 1599 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1600 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1601 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1602 reset-names = "pciephy", "apps", "turnoff"; 1603 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, 1604 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1605 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1606 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1607 <&clk IMX8MQ_SYS2_PLL_100M>, 1608 <&clk IMX8MQ_SYS1_PLL_80M>; 1609 assigned-clock-rates = <250000000>, <100000000>, 1610 <10000000>; 1611 status = "disabled"; 1612 }; 1613 1614 pcie1_ep: pcie-ep@33c00000 { 1615 compatible = "fsl,imx8mq-pcie-ep"; 1616 reg = <0x33c00000 0x000400000>, 1617 <0x20000000 0x08000000>; 1618 reg-names = "dbi", "addr_space"; 1619 num-lanes = <1>; 1620 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1621 interrupt-names = "dma"; 1622 fsl,max-link-speed = <2>; 1623 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 1624 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1625 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1626 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1627 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1628 power-domains = <&pgc_pcie>; 1629 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1630 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1631 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1632 reset-names = "pciephy", "apps", "turnoff"; 1633 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, 1634 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1635 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1636 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1637 <&clk IMX8MQ_SYS2_PLL_100M>, 1638 <&clk IMX8MQ_SYS1_PLL_80M>; 1639 assigned-clock-rates = <250000000>, <100000000>, 1640 <10000000>; 1641 num-ib-windows = <4>; 1642 num-ob-windows = <4>; 1643 status = "disabled"; 1644 }; 1645 1646 gic: interrupt-controller@38800000 { 1647 compatible = "arm,gic-v3"; 1648 reg = <0x38800000 0x10000>, /* GIC Dist */ 1649 <0x38880000 0xc0000>, /* GICR */ 1650 <0x31000000 0x2000>, /* GICC */ 1651 <0x31010000 0x2000>, /* GICV */ 1652 <0x31020000 0x2000>; /* GICH */ 1653 #interrupt-cells = <3>; 1654 interrupt-controller; 1655 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1656 interrupt-parent = <&gic>; 1657 }; 1658 1659 ddrc: memory-controller@3d400000 { 1660 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; 1661 reg = <0x3d400000 0x400000>; 1662 clock-names = "core", "pll", "alt", "apb"; 1663 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, 1664 <&clk IMX8MQ_DRAM_PLL_OUT>, 1665 <&clk IMX8MQ_CLK_DRAM_ALT>, 1666 <&clk IMX8MQ_CLK_DRAM_APB>; 1667 status = "disabled"; 1668 }; 1669 1670 ddr-pmu@3d800000 { 1671 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1672 reg = <0x3d800000 0x400000>; 1673 interrupt-parent = <&gic>; 1674 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1675 }; 1676 }; 1677}; 1678