1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2019 Zodiac Inflight Innovations
4 */
5
6#include "imx8mq.dtsi"
7
8/ {
9	aliases {
10		mdio-gpio0 = &mdio0;
11		rtc0 = &ds1341;
12	};
13
14	chosen {
15		stdout-path = &uart1;
16	};
17
18	mdio0: bitbang-mdio {
19		compatible = "virtual,mdio-gpio";
20		pinctrl-names = "default";
21		pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
22		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
23			<&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		phy0: ethernet-phy@0 {
28			reg = <0>;
29			reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
30		};
31	};
32
33	pcie0_refclk: clock-pcie0-refclk {
34		compatible = "fixed-clock";
35		#clock-cells = <0>;
36		clock-frequency = <100000000>;
37	};
38
39	pcie1_refclk: clock-pcie1-refclk {
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		clock-frequency = <100000000>;
43	};
44
45	reg_12p0_main: regulator-12p0-main {
46		compatible = "regulator-fixed";
47		regulator-name = "12V_MAIN";
48		regulator-min-microvolt = <5000000>;
49		regulator-max-microvolt = <5000000>;
50		regulator-always-on;
51	};
52
53	reg_5p0_main: regulator-5p0-main {
54		compatible = "regulator-fixed";
55		vin-supply = <&reg_12p0_main>;
56		regulator-name = "5V_MAIN";
57		regulator-min-microvolt = <5000000>;
58		regulator-max-microvolt = <5000000>;
59		regulator-always-on;
60	};
61
62	reg_3p3_main: regulator-3p3-main {
63		compatible = "regulator-fixed";
64		vin-supply = <&reg_12p0_main>;
65		regulator-name = "3V3V_MAIN";
66		regulator-min-microvolt = <3300000>;
67		regulator-max-microvolt = <3300000>;
68		regulator-always-on;
69	};
70
71	reg_5p0_user_usb: regulator-5p0-user-usb {
72		compatible = "regulator-fixed";
73		pinctrl-names = "default";
74		pinctrl-0 = <&pinctrl_reg_user_usb>;
75		vin-supply = <&reg_5p0_main>;
76		regulator-name = "5V_USER_USB";
77		regulator-min-microvolt = <5000000>;
78		regulator-max-microvolt = <5000000>;
79		gpio = <&gpio3 12 GPIO_ACTIVE_LOW>;
80		startup-delay-us = <1000>;
81	};
82
83	reg_usdhc2_vmmc: regulator-vsd-3v3 {
84		pinctrl-names = "default";
85		pinctrl-0 = <&pinctrl_reg_usdhc2>;
86		compatible = "regulator-fixed";
87		vin-supply = <&reg_3p3_main>;
88		regulator-name = "3V3_SD";
89		regulator-min-microvolt = <3300000>;
90		regulator-max-microvolt = <3300000>;
91		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
92		enable-active-high;
93	};
94
95	reg_arm: regulator-arm {
96		pinctrl-names = "default";
97		pinctrl-0 = <&pinctrl_reg_arm>;
98		compatible = "regulator-gpio";
99		vin-supply = <&reg_12p0_main>;
100		regulator-name = "0V9_ARM";
101		regulator-min-microvolt = <900000>;
102		regulator-max-microvolt = <1000000>;
103		gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
104		states = <1000000 0x0
105		           900000 0x1>;
106		regulator-always-on;
107	};
108};
109
110&A53_0 {
111	cpu-supply = <&reg_arm>;
112};
113
114&A53_1 {
115	cpu-supply = <&reg_arm>;
116};
117
118&A53_2 {
119	cpu-supply = <&reg_arm>;
120};
121
122&A53_3 {
123	cpu-supply = <&reg_arm>;
124};
125
126&fec1 {
127	pinctrl-names = "default";
128	pinctrl-0 = <&pinctrl_fec1>;
129
130	phy-handle = <&phy0>;
131	phy-mode = "rmii";
132	status = "okay";
133
134	mdio {
135		#address-cells = <1>;
136		#size-cells = <0>;
137		status = "okay";
138
139		switch: switch@0 {
140			compatible = "marvell,mv88e6085";
141			pinctrl-0 = <&pinctrl_switch_irq>;
142			pinctrl-names = "default";
143			reg = <0>;
144			dsa,member = <0 0>;
145			eeprom-length = <512>;
146			interrupt-parent = <&gpio1>;
147			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
148			interrupt-controller;
149			#interrupt-cells = <2>;
150
151			ports {
152				#address-cells = <1>;
153				#size-cells = <0>;
154
155				port@0 {
156					reg = <0>;
157					label = "gigabit_proc";
158					phy-handle = <&switchphy0>;
159				};
160
161				port@1 {
162					reg = <1>;
163					label = "netaux";
164					phy-handle = <&switchphy1>;
165				};
166
167				port@2 {
168					reg = <2>;
169					label = "cpu";
170					ethernet = <&fec1>;
171
172					fixed-link {
173						speed = <100>;
174						full-duplex;
175					};
176				};
177
178				port@3 {
179					reg = <3>;
180					label = "netright";
181					phy-handle = <&switchphy3>;
182				};
183
184				port@4 {
185					reg = <4>;
186					label = "netleft";
187					phy-handle = <&switchphy4>;
188				};
189			};
190
191			mdio {
192				#address-cells = <1>;
193				#size-cells = <0>;
194
195				switchphy0: switchphy@0 {
196					reg = <0>;
197					interrupt-parent = <&switch>;
198					interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
199				};
200
201				switchphy1: switchphy@1 {
202					reg = <1>;
203					interrupt-parent = <&switch>;
204					interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
205				};
206
207				switchphy2: switchphy@2 {
208					reg = <2>;
209					interrupt-parent = <&switch>;
210					interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
211				};
212
213				switchphy3: switchphy@3 {
214					reg = <3>;
215					interrupt-parent = <&switch>;
216					interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
217				};
218
219				switchphy4: switchphy@4 {
220					reg = <4>;
221					interrupt-parent = <&switch>;
222					interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
223				};
224			};
225		};
226	};
227};
228
229&gpio3 {
230	pinctrl-names = "default";
231	pinctrl-0 = <&pinctrl_gpio3_hog>;
232
233	usb-emulation {
234		gpio-hog;
235		gpios = <10 GPIO_ACTIVE_HIGH>;
236		output-low;
237		line-name = "usb-emulation";
238	};
239
240	usb-mode1 {
241		gpio-hog;
242		gpios = <11 GPIO_ACTIVE_HIGH>;
243		output-high;
244		line-name = "usb-mode1";
245	};
246
247	usb-mode2 {
248		gpio-hog;
249		gpios = <13 GPIO_ACTIVE_HIGH>;
250		output-high;
251		line-name = "usb-mode2";
252	};
253};
254
255&i2c1 {
256	clock-frequency = <400000>;
257	pinctrl-names = "default";
258	pinctrl-0 = <&pinctrl_i2c1>;
259	status = "okay";
260};
261
262&i2c2 {
263	clock-frequency = <400000>;
264	pinctrl-names = "default";
265	pinctrl-0 = <&pinctrl_i2c2>;
266	status = "okay";
267
268	pmic@8 {
269		compatible = "fsl,pfuze100";
270		reg = <0x8>;
271
272		regulators {
273			sw1a_reg: sw1ab {
274				regulator-min-microvolt = <825000>;
275				regulator-max-microvolt = <1100000>;
276			};
277
278			sw1c_reg: sw1c {
279				regulator-min-microvolt = <825000>;
280				regulator-max-microvolt = <1100000>;
281			};
282
283			sw2_reg: sw2 {
284				regulator-min-microvolt = <1100000>;
285				regulator-max-microvolt = <1100000>;
286				regulator-always-on;
287			};
288
289			sw3a_reg: sw3ab {
290				regulator-min-microvolt = <825000>;
291				regulator-max-microvolt = <1100000>;
292				regulator-always-on;
293			};
294
295			sw4_reg: sw4 {
296				regulator-min-microvolt = <1800000>;
297				regulator-max-microvolt = <1800000>;
298				regulator-always-on;
299			};
300
301			swbst_reg: swbst {
302				regulator-min-microvolt = <5000000>;
303				regulator-max-microvolt = <5150000>;
304			};
305
306			snvs_reg: vsnvs {
307				regulator-min-microvolt = <1000000>;
308				regulator-max-microvolt = <3000000>;
309				regulator-always-on;
310			};
311
312			vref_reg: vrefddr {
313				regulator-always-on;
314			};
315
316			vgen1_reg: vgen1 {
317				regulator-min-microvolt = <800000>;
318				regulator-max-microvolt = <1550000>;
319			};
320
321			vgen2_reg: vgen2 {
322				regulator-min-microvolt = <850000>;
323				regulator-max-microvolt = <975000>;
324				regulator-always-on;
325			};
326
327			vgen3_reg: vgen3 {
328				regulator-min-microvolt = <1675000>;
329				regulator-max-microvolt = <1975000>;
330				regulator-always-on;
331			};
332
333			vgen4_reg: vgen4 {
334				regulator-min-microvolt = <1625000>;
335				regulator-max-microvolt = <1875000>;
336				regulator-always-on;
337			};
338
339			vgen5_reg: vgen5 {
340				regulator-min-microvolt = <3075000>;
341				regulator-max-microvolt = <3625000>;
342				regulator-always-on;
343			};
344
345			vgen6_reg: vgen6 {
346				regulator-min-microvolt = <1800000>;
347				regulator-max-microvolt = <3300000>;
348			};
349		};
350	};
351
352	eeprom@54 {
353		compatible = "atmel,24c128";
354		reg = <0x54>;
355	};
356
357	ds1341: rtc@68 {
358		compatible = "dallas,ds1341";
359		reg = <0x68>;
360	};
361};
362
363&i2c3 {
364	clock-frequency = <100000>;
365	pinctrl-names = "default";
366	pinctrl-0 = <&pinctrl_i2c3>;
367	status = "okay";
368
369	usbhub: usbhub@2c {
370		compatible ="microchip,usb2513b";
371		pinctrl-names = "default";
372		pinctrl-0 = <&pinctrl_usbhub>;
373		reg = <0x2c>;
374		reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
375	};
376};
377
378&i2c4 {
379	clock-frequency = <400000>;
380	pinctrl-names = "default";
381	pinctrl-0 = <&pinctrl_i2c4>;
382	status = "okay";
383};
384
385&uart1 {
386	pinctrl-names = "default";
387	pinctrl-0 = <&pinctrl_uart1>;
388	status = "okay";
389};
390
391&uart2 {
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_uart2>;
394	status = "okay";
395
396	rave-sp {
397		compatible = "zii,rave-sp-rdu2";
398		current-speed = <1000000>;
399		#address-cells = <1>;
400		#size-cells = <1>;
401
402		watchdog {
403			compatible = "zii,rave-sp-watchdog";
404		};
405
406		backlight {
407			compatible = "zii,rave-sp-backlight";
408		};
409
410		pwrbutton {
411			compatible = "zii,rave-sp-pwrbutton";
412		};
413
414		eeprom@a3 {
415			compatible = "zii,rave-sp-eeprom";
416			reg = <0xa3 0x4000>;
417			zii,eeprom-name = "dds-eeprom";
418		};
419
420		eeprom@a4 {
421			compatible = "zii,rave-sp-eeprom";
422			reg = <0xa4 0x4000>;
423			#address-cells = <1>;
424			#size-cells = <1>;
425			zii,eeprom-name = "main-eeprom";
426		};
427	};
428};
429
430&usb3_phy0 {
431	vbus-supply = <&reg_5p0_user_usb>;
432	status = "okay";
433};
434
435&usb_dwc3_0 {
436	dr_mode = "host";
437	status = "okay";
438};
439
440&usb3_phy1 {
441	vbus-supply = <&reg_5p0_main>;
442	status = "okay";
443};
444
445&usb_dwc3_1 {
446	dr_mode = "host";
447	status = "okay";
448};
449
450&pcie0 {
451	pinctrl-names = "default";
452	pinctrl-0 = <&pinctrl_pcie0>;
453	reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
454	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
455	         <&clk IMX8MQ_CLK_PCIE1_AUX>,
456	         <&clk IMX8MQ_CLK_PCIE1_PHY>,
457	         <&pcie0_refclk>;
458	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
459	status = "okay";
460};
461
462&pcie1 {
463	pinctrl-names = "default";
464	pinctrl-0 = <&pinctrl_pcie1>;
465	reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
466	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
467	         <&clk IMX8MQ_CLK_PCIE2_AUX>,
468	         <&clk IMX8MQ_CLK_PCIE2_PHY>,
469	         <&pcie1_refclk>;
470	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
471	status = "okay";
472};
473
474&pgc_gpu {
475	power-supply = <&sw1a_reg>;
476};
477
478&pgc_vpu {
479	power-supply = <&sw1c_reg>;
480};
481
482&usdhc1 {
483	pinctrl-names = "default", "state_100mhz", "state_200mhz";
484	pinctrl-0 = <&pinctrl_usdhc1>;
485	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
486	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
487	vqmmc-supply = <&sw4_reg>;
488	bus-width = <8>;
489	non-removable;
490	no-sd;
491	no-sdio;
492	status = "okay";
493};
494
495&usdhc2 {
496	pinctrl-names = "default", "state_100mhz", "state_200mhz";
497	pinctrl-0 = <&pinctrl_usdhc2>;
498	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
499	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
500	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
501	vmmc-supply = <&reg_usdhc2_vmmc>;
502	status = "okay";
503};
504
505&snvs_rtc {
506	status = "disabled";
507};
508
509&iomuxc {
510	pinctrl_fec1: fec1grp {
511		fsl,pins = <
512			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
513			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
514			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
515			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
516			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
517			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
518			MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK		0x1f
519			MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER		0x91
520			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
521			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
522		>;
523	};
524
525	pinctrl_fec1_phy_reset: fec1phyresetgrp {
526		fsl,pins = <
527			MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29		0x11
528		>;
529	};
530
531	pinctrl_gpio3_hog: gpio3hoggrp {
532		fsl,pins = <
533			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x6
534			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x6
535			MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13		0x6
536		>;
537	};
538
539	pinctrl_i2c1: i2c1grp {
540		fsl,pins = <
541			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
542			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
543		>;
544	};
545
546	pinctrl_i2c2: i2c2grp {
547		fsl,pins = <
548			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
549			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
550		>;
551	};
552
553	pinctrl_i2c3: i2c3grp {
554		fsl,pins = <
555			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
556			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
557		>;
558	};
559
560	pinctrl_i2c4: i2c4grp {
561		fsl,pins = <
562			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x4000007f
563			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x4000007f
564		>;
565	};
566
567	pinctrl_mdio_bitbang: bitbangmdiogrp {
568		fsl,pins = <
569			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x44
570			MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x64
571		>;
572	};
573
574	pinctrl_pcie0: pcie0grp {
575		fsl,pins = <
576			MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B		0x66
577			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x6
578		>;
579	};
580
581	pinctrl_pcie1: pcie1grp {
582		fsl,pins = <
583			MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B		0x66
584			MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x6
585		>;
586	};
587
588	pinctrl_reg_arm: regarmgrp {
589		fsl,pins = <
590			MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19
591		>;
592	};
593
594	pinctrl_reg_usdhc2: regusdhc2grp {
595		fsl,pins = <
596			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
597		>;
598	};
599
600	pinctrl_reg_user_usb: reguserusbgrp {
601		fsl,pins = <
602			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x6
603		>;
604	};
605
606	pinctrl_switch_irq: switchgrp {
607		fsl,pins = <
608			MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x41
609		>;
610	};
611
612	pinctrl_ts: tsgrp {
613		fsl,pins = <
614			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x96
615			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x96
616		>;
617	};
618
619	pinctrl_uart1: uart1grp {
620		fsl,pins = <
621			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
622			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
623		>;
624	};
625
626	pinctrl_uart2: uart2grp {
627		fsl,pins = <
628			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
629			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
630		>;
631	};
632
633	pinctrl_usbhub: usbhubgrp {
634		fsl,pins = <
635			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x41
636		>;
637	};
638
639	pinctrl_usdhc1: usdhc1grp {
640		fsl,pins = <
641			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
642			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
643			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
644			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
645			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
646			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
647			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
648			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
649			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
650			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
651			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
652			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
653		>;
654	};
655
656	pinctrl_usdhc1_100mhz: usdhc1-100grp {
657		fsl,pins = <
658			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
659			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
660			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
661			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
662			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
663			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
664			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
665			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
666			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
667			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
668			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
669			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
670		>;
671	};
672
673	pinctrl_usdhc1_200mhz: usdhc1-200grp {
674		fsl,pins = <
675			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
676			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
677			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
678			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
679			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
680			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
681			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
682			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
683			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
684			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
685			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
686			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
687		>;
688	};
689
690	pinctrl_usdhc2: usdhc2grp {
691		fsl,pins = <
692			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
693			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
694			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
695			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
696			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
697			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
698			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
699		>;
700	};
701
702	pinctrl_usdhc2_100mhz: usdhc2-100grp {
703		fsl,pins = <
704			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
705			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
706			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
707			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
708			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
709			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
710			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
711		>;
712	};
713
714	pinctrl_usdhc2_200mhz: usdhc2-200grp {
715		fsl,pins = <
716			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
717			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
718			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
719			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
720			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
721			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
722			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
723		>;
724	};
725};
726