1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2019 Zodiac Inflight Innovations
4 */
5
6#include "imx8mq.dtsi"
7
8/ {
9	aliases {
10		mdio-gpio0 = &mdio0;
11		rtc0 = &ds1341;
12	};
13
14	chosen {
15		stdout-path = &uart1;
16	};
17
18	mdio0: bitbang-mdio {
19		compatible = "virtual,mdio-gpio";
20		pinctrl-names = "default";
21		pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
22		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
23			<&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		phy0: ethernet-phy@0 {
28			reg = <0>;
29			reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
30		};
31	};
32
33	pcie0_refclk: clock-pcie0-refclk {
34		compatible = "fixed-clock";
35		#clock-cells = <0>;
36		clock-frequency = <100000000>;
37	};
38
39	pcie1_refclk: clock-pcie1-refclk {
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		clock-frequency = <100000000>;
43	};
44
45	reg_12p0_main: regulator-12p0-main {
46		compatible = "regulator-fixed";
47		regulator-name = "12V_MAIN";
48		regulator-min-microvolt = <5000000>;
49		regulator-max-microvolt = <5000000>;
50		regulator-always-on;
51	};
52
53	reg_5p0_main: regulator-5p0-main {
54		compatible = "regulator-fixed";
55		vin-supply = <&reg_12p0_main>;
56		regulator-name = "5V_MAIN";
57		regulator-min-microvolt = <5000000>;
58		regulator-max-microvolt = <5000000>;
59		regulator-always-on;
60	};
61
62	reg_3p3_main: regulator-3p3-main {
63		compatible = "regulator-fixed";
64		vin-supply = <&reg_12p0_main>;
65		regulator-name = "3V3_MAIN";
66		regulator-min-microvolt = <3300000>;
67		regulator-max-microvolt = <3300000>;
68		regulator-always-on;
69	};
70
71	reg_gen_3p3: regulator-gen-3p3 {
72		compatible = "regulator-fixed";
73		vin-supply = <&reg_3p3_main>;
74		regulator-name = "GEN_3V3";
75		regulator-min-microvolt = <3300000>;
76		regulator-max-microvolt = <3300000>;
77		regulator-always-on;
78	};
79
80	reg_usdhc2_vmmc: regulator-vsd-3v3 {
81		pinctrl-names = "default";
82		pinctrl-0 = <&pinctrl_reg_usdhc2>;
83		compatible = "regulator-fixed";
84		vin-supply = <&reg_gen_3p3>;
85		regulator-name = "3V3_SD";
86		regulator-min-microvolt = <3300000>;
87		regulator-max-microvolt = <3300000>;
88		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
89		enable-active-high;
90	};
91
92	reg_arm: regulator-arm {
93		pinctrl-names = "default";
94		pinctrl-0 = <&pinctrl_reg_arm>;
95		compatible = "regulator-gpio";
96		vin-supply = <&reg_12p0_main>;
97		regulator-name = "0V9_ARM";
98		regulator-min-microvolt = <900000>;
99		regulator-max-microvolt = <1000000>;
100		gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
101		states = <1000000 0x0
102		           900000 0x1>;
103		regulator-always-on;
104	};
105};
106
107&A53_0 {
108	cpu-supply = <&reg_arm>;
109};
110
111&A53_1 {
112	cpu-supply = <&reg_arm>;
113};
114
115&A53_2 {
116	cpu-supply = <&reg_arm>;
117};
118
119&A53_3 {
120	cpu-supply = <&reg_arm>;
121};
122
123&fec1 {
124	pinctrl-names = "default";
125	pinctrl-0 = <&pinctrl_fec1>;
126
127	phy-handle = <&phy0>;
128	phy-mode = "rmii";
129	status = "okay";
130
131	mdio {
132		#address-cells = <1>;
133		#size-cells = <0>;
134		status = "okay";
135
136		switch: switch@0 {
137			compatible = "marvell,mv88e6085";
138			pinctrl-0 = <&pinctrl_switch_irq>;
139			pinctrl-names = "default";
140			reg = <0>;
141			dsa,member = <0 0>;
142			eeprom-length = <512>;
143			interrupt-parent = <&gpio1>;
144			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
145			interrupt-controller;
146			#interrupt-cells = <2>;
147
148			ports {
149				#address-cells = <1>;
150				#size-cells = <0>;
151
152				port@0 {
153					reg = <0>;
154					label = "gigabit_proc";
155					phy-handle = <&switchphy0>;
156				};
157
158				port@1 {
159					reg = <1>;
160					label = "netaux";
161					phy-handle = <&switchphy1>;
162				};
163
164				port@2 {
165					reg = <2>;
166					label = "cpu";
167					ethernet = <&fec1>;
168
169					fixed-link {
170						speed = <100>;
171						full-duplex;
172					};
173				};
174
175				port@3 {
176					reg = <3>;
177					label = "netright";
178					phy-handle = <&switchphy3>;
179				};
180
181				port@4 {
182					reg = <4>;
183					label = "netleft";
184					phy-handle = <&switchphy4>;
185				};
186			};
187
188			mdio {
189				#address-cells = <1>;
190				#size-cells = <0>;
191
192				switchphy0: switchphy@0 {
193					reg = <0>;
194					interrupt-parent = <&switch>;
195					interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
196				};
197
198				switchphy1: switchphy@1 {
199					reg = <1>;
200					interrupt-parent = <&switch>;
201					interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
202				};
203
204				switchphy2: switchphy@2 {
205					reg = <2>;
206					interrupt-parent = <&switch>;
207					interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
208				};
209
210				switchphy3: switchphy@3 {
211					reg = <3>;
212					interrupt-parent = <&switch>;
213					interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
214				};
215
216				switchphy4: switchphy@4 {
217					reg = <4>;
218					interrupt-parent = <&switch>;
219					interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
220				};
221			};
222		};
223	};
224};
225
226&gpio3 {
227	pinctrl-names = "default";
228	pinctrl-0 = <&pinctrl_gpio3_hog>;
229
230	usb-emulation {
231		gpio-hog;
232		gpios = <10 GPIO_ACTIVE_HIGH>;
233		output-low;
234		line-name = "usb-emulation";
235	};
236
237	usb-mode1 {
238		gpio-hog;
239		gpios = <11 GPIO_ACTIVE_HIGH>;
240		output-high;
241		line-name = "usb-mode1";
242	};
243
244	usb-pwr {
245		gpio-hog;
246		gpios = <12 GPIO_ACTIVE_LOW>;
247		output-high;
248		line-name = "usb-pwr-ctrl-en-n";
249	};
250
251	usb-mode2 {
252		gpio-hog;
253		gpios = <13 GPIO_ACTIVE_HIGH>;
254		output-high;
255		line-name = "usb-mode2";
256	};
257};
258
259&i2c1 {
260	clock-frequency = <400000>;
261	pinctrl-names = "default";
262	pinctrl-0 = <&pinctrl_i2c1>;
263	status = "okay";
264
265	ucs1002: charger@32 {
266		compatible = "microchip,ucs1002";
267		pinctrl-names = "default";
268		pinctrl-0 = <&pinctrl_ucs1002>;
269		reg = <0x32>;
270		interrupt-parent = <&gpio3>;
271		interrupts = <17 IRQ_TYPE_EDGE_BOTH>,
272		             <18 IRQ_TYPE_EDGE_BOTH>;
273		interrupt-names = "a_det", "alert";
274	};
275};
276
277&i2c2 {
278	clock-frequency = <400000>;
279	pinctrl-names = "default";
280	pinctrl-0 = <&pinctrl_i2c2>;
281	status = "okay";
282
283	pmic@8 {
284		compatible = "fsl,pfuze100";
285		reg = <0x8>;
286
287		regulators {
288			sw1a_reg: sw1ab {
289				regulator-min-microvolt = <825000>;
290				regulator-max-microvolt = <1100000>;
291			};
292
293			sw1c_reg: sw1c {
294				regulator-min-microvolt = <825000>;
295				regulator-max-microvolt = <1100000>;
296			};
297
298			sw2_reg: sw2 {
299				regulator-min-microvolt = <1100000>;
300				regulator-max-microvolt = <1100000>;
301				regulator-always-on;
302			};
303
304			sw3a_reg: sw3ab {
305				regulator-min-microvolt = <825000>;
306				regulator-max-microvolt = <1100000>;
307				regulator-always-on;
308			};
309
310			sw4_reg: sw4 {
311				regulator-min-microvolt = <1800000>;
312				regulator-max-microvolt = <1800000>;
313				regulator-always-on;
314			};
315
316			swbst_reg: swbst {
317				regulator-min-microvolt = <5000000>;
318				regulator-max-microvolt = <5150000>;
319			};
320
321			snvs_reg: vsnvs {
322				regulator-min-microvolt = <1000000>;
323				regulator-max-microvolt = <3000000>;
324				regulator-always-on;
325			};
326
327			vref_reg: vrefddr {
328				regulator-always-on;
329			};
330
331			vgen1_reg: vgen1 {
332				regulator-min-microvolt = <800000>;
333				regulator-max-microvolt = <1550000>;
334			};
335
336			vgen2_reg: vgen2 {
337				regulator-min-microvolt = <850000>;
338				regulator-max-microvolt = <975000>;
339				regulator-always-on;
340			};
341
342			vgen3_reg: vgen3 {
343				regulator-min-microvolt = <1675000>;
344				regulator-max-microvolt = <1975000>;
345				regulator-always-on;
346			};
347
348			vgen4_reg: vgen4 {
349				regulator-min-microvolt = <1625000>;
350				regulator-max-microvolt = <1875000>;
351				regulator-always-on;
352			};
353
354			vgen5_reg: vgen5 {
355				regulator-min-microvolt = <3075000>;
356				regulator-max-microvolt = <3625000>;
357				regulator-always-on;
358			};
359
360			vgen6_reg: vgen6 {
361				regulator-min-microvolt = <1800000>;
362				regulator-max-microvolt = <3300000>;
363			};
364		};
365	};
366
367	eeprom@54 {
368		compatible = "atmel,24c128";
369		reg = <0x54>;
370	};
371
372	ds1341: rtc@68 {
373		compatible = "dallas,ds1341";
374		reg = <0x68>;
375	};
376};
377
378&i2c3 {
379	clock-frequency = <100000>;
380	pinctrl-names = "default";
381	pinctrl-0 = <&pinctrl_i2c3>;
382	status = "okay";
383
384	usbhub: usbhub@2c {
385		compatible ="microchip,usb2513b";
386		pinctrl-names = "default";
387		pinctrl-0 = <&pinctrl_usbhub>;
388		reg = <0x2c>;
389		reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
390	};
391};
392
393&i2c4 {
394	clock-frequency = <400000>;
395	pinctrl-names = "default";
396	pinctrl-0 = <&pinctrl_i2c4>;
397	status = "okay";
398};
399
400&uart1 {
401	pinctrl-names = "default";
402	pinctrl-0 = <&pinctrl_uart1>;
403	status = "okay";
404};
405
406&uart2 {
407	pinctrl-names = "default";
408	pinctrl-0 = <&pinctrl_uart2>;
409	status = "okay";
410
411	rave-sp {
412		compatible = "zii,rave-sp-rdu2";
413		current-speed = <1000000>;
414		#address-cells = <1>;
415		#size-cells = <1>;
416
417		watchdog {
418			compatible = "zii,rave-sp-watchdog";
419		};
420
421		backlight {
422			compatible = "zii,rave-sp-backlight";
423		};
424
425		pwrbutton {
426			compatible = "zii,rave-sp-pwrbutton";
427		};
428
429		eeprom@a3 {
430			compatible = "zii,rave-sp-eeprom";
431			reg = <0xa3 0x4000>;
432			zii,eeprom-name = "dds-eeprom";
433		};
434
435		eeprom@a4 {
436			compatible = "zii,rave-sp-eeprom";
437			reg = <0xa4 0x4000>;
438			#address-cells = <1>;
439			#size-cells = <1>;
440			zii,eeprom-name = "main-eeprom";
441		};
442	};
443};
444
445&usb3_phy0 {
446	vbus-supply = <&ucs1002>;
447	status = "okay";
448};
449
450&usb_dwc3_0 {
451	dr_mode = "host";
452	status = "okay";
453};
454
455&usb3_phy1 {
456	vbus-supply = <&reg_5p0_main>;
457	status = "okay";
458};
459
460&usb_dwc3_1 {
461	dr_mode = "host";
462	status = "okay";
463};
464
465&pcie0 {
466	pinctrl-names = "default";
467	pinctrl-0 = <&pinctrl_pcie0>;
468	reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
469	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
470	         <&clk IMX8MQ_CLK_PCIE1_AUX>,
471	         <&clk IMX8MQ_CLK_PCIE1_PHY>,
472	         <&pcie0_refclk>;
473	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
474	status = "okay";
475};
476
477&pcie1 {
478	pinctrl-names = "default";
479	pinctrl-0 = <&pinctrl_pcie1>;
480	reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
481	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
482	         <&clk IMX8MQ_CLK_PCIE2_AUX>,
483	         <&clk IMX8MQ_CLK_PCIE2_PHY>,
484	         <&pcie1_refclk>;
485	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
486	status = "okay";
487};
488
489&pgc_gpu {
490	power-supply = <&sw1a_reg>;
491};
492
493&pgc_vpu {
494	power-supply = <&sw1c_reg>;
495};
496
497&usdhc1 {
498	pinctrl-names = "default", "state_100mhz", "state_200mhz";
499	pinctrl-0 = <&pinctrl_usdhc1>;
500	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
501	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
502	vqmmc-supply = <&sw4_reg>;
503	bus-width = <8>;
504	non-removable;
505	no-sd;
506	no-sdio;
507	status = "okay";
508};
509
510&usdhc2 {
511	pinctrl-names = "default", "state_100mhz", "state_200mhz";
512	pinctrl-0 = <&pinctrl_usdhc2>;
513	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
514	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
515	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
516	vmmc-supply = <&reg_usdhc2_vmmc>;
517	status = "okay";
518};
519
520&snvs_rtc {
521	status = "disabled";
522};
523
524&iomuxc {
525	pinctrl_fec1: fec1grp {
526		fsl,pins = <
527			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
528			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
529			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
530			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
531			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
532			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
533			MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK		0x1f
534			MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER		0x91
535			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
536			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
537		>;
538	};
539
540	pinctrl_fec1_phy_reset: fec1phyresetgrp {
541		fsl,pins = <
542			MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29		0x11
543		>;
544	};
545
546	pinctrl_gpio3_hog: gpio3hoggrp {
547		fsl,pins = <
548			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x6
549			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x6
550			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x6
551			MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13		0x6
552		>;
553	};
554
555	pinctrl_i2c1: i2c1grp {
556		fsl,pins = <
557			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
558			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
559		>;
560	};
561
562	pinctrl_i2c2: i2c2grp {
563		fsl,pins = <
564			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
565			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
566		>;
567	};
568
569	pinctrl_i2c3: i2c3grp {
570		fsl,pins = <
571			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
572			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
573		>;
574	};
575
576	pinctrl_i2c4: i2c4grp {
577		fsl,pins = <
578			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x4000007f
579			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x4000007f
580		>;
581	};
582
583	pinctrl_mdio_bitbang: bitbangmdiogrp {
584		fsl,pins = <
585			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x44
586			MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x64
587		>;
588	};
589
590	pinctrl_pcie0: pcie0grp {
591		fsl,pins = <
592			MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B		0x66
593			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x6
594		>;
595	};
596
597	pinctrl_pcie1: pcie1grp {
598		fsl,pins = <
599			MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B		0x66
600			MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x6
601		>;
602	};
603
604	pinctrl_reg_arm: regarmgrp {
605		fsl,pins = <
606			MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19
607		>;
608	};
609
610	pinctrl_reg_usdhc2: regusdhc2grp {
611		fsl,pins = <
612			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
613		>;
614	};
615
616	pinctrl_switch_irq: switchgrp {
617		fsl,pins = <
618			MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15		0x41
619		>;
620	};
621
622	pinctrl_ts: tsgrp {
623		fsl,pins = <
624			MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11		0x96
625			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x96
626		>;
627	};
628
629	pinctrl_uart1: uart1grp {
630		fsl,pins = <
631			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
632			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
633		>;
634	};
635
636	pinctrl_uart2: uart2grp {
637		fsl,pins = <
638			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
639			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
640		>;
641	};
642
643	pinctrl_ucs1002: ucs1002grp {
644		fsl,pins = <
645			MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x41
646			MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18		0x41
647		>;
648	};
649
650	pinctrl_usbhub: usbhubgrp {
651		fsl,pins = <
652			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25		0x41
653		>;
654	};
655
656	pinctrl_usdhc1: usdhc1grp {
657		fsl,pins = <
658			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
659			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
660			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
661			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
662			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
663			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
664			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
665			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
666			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
667			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
668			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
669			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
670		>;
671	};
672
673	pinctrl_usdhc1_100mhz: usdhc1-100grp {
674		fsl,pins = <
675			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
676			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
677			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
678			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
679			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
680			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
681			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
682			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
683			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
684			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
685			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
686			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
687		>;
688	};
689
690	pinctrl_usdhc1_200mhz: usdhc1-200grp {
691		fsl,pins = <
692			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
693			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
694			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
695			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
696			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
697			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
698			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
699			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
700			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
701			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
702			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
703			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
704		>;
705	};
706
707	pinctrl_usdhc2: usdhc2grp {
708		fsl,pins = <
709			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
710			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
711			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
712			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
713			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
714			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
715			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
716		>;
717	};
718
719	pinctrl_usdhc2_100mhz: usdhc2-100grp {
720		fsl,pins = <
721			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
722			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
723			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
724			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
725			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
726			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
727			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
728		>;
729	};
730
731	pinctrl_usdhc2_200mhz: usdhc2-200grp {
732		fsl,pins = <
733			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
734			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
735			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
736			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
737			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
738			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
739			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
740		>;
741	};
742};
743