1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright 2019-2021 TQ-Systems GmbH
4 */
5
6#include "imx8mq.dtsi"
7
8/ {
9	model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ";
10	compatible = "tq,imx8mq-tqma8mq", "fsl,imx8mq";
11
12	memory@40000000 {
13		device_type = "memory";
14		/*  our minimum RAM config will be 1024 MiB */
15		reg = <0x00000000 0x40000000 0 0x40000000>;
16	};
17
18	/* e-MMC IO, needed for HS modes */
19	reg_vcc1v8: regulator-vcc1v8 {
20		compatible = "regulator-fixed";
21		regulator-name = "TQMA8MX_VCC1V8";
22		regulator-min-microvolt = <1800000>;
23		regulator-max-microvolt = <1800000>;
24	};
25
26	reg_vcc3v3: regulator-vcc3v3 {
27		compatible = "regulator-fixed";
28		regulator-name = "TQMA8MX_VCC3V3";
29		regulator-min-microvolt = <3300000>;
30		regulator-max-microvolt = <3300000>;
31	};
32
33	reg_vdd_arm: regulator-vdd-arm {
34		compatible = "regulator-gpio";
35		pinctrl-names = "default";
36		pinctrl-0 = <&pinctrl_dvfs>;
37		regulator-min-microvolt = <900000>;
38		regulator-max-microvolt = <1000000>;
39		regulator-name = "TQMa8Mx_DVFS";
40		regulator-type = "voltage";
41		regulator-settling-time-us = <150000>;
42		gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
43		states = <900000 0x1 1000000 0x0>;
44	};
45
46	reserved-memory {
47		#address-cells = <2>;
48		#size-cells = <2>;
49		ranges;
50
51		/* global autoconfigured region for contiguous allocations */
52		linux,cma {
53			compatible = "shared-dma-pool";
54			reusable;
55			/* 640 MiB */
56			size = <0 0x28000000>;
57			/*  1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
58			alloc-ranges = <0 0x40000000 0 0x78000000>;
59			linux,cma-default;
60		};
61	};
62};
63
64&A53_0 {
65	cpu-supply = <&reg_vdd_arm>;
66};
67
68&A53_1 {
69	cpu-supply = <&reg_vdd_arm>;
70};
71
72&A53_2 {
73	cpu-supply = <&reg_vdd_arm>;
74};
75
76&A53_3 {
77	cpu-supply = <&reg_vdd_arm>;
78};
79
80&gpu {
81	status = "okay";
82};
83
84&pgc_gpu {
85	power-supply = <&sw1a_reg>;
86};
87
88&pgc_vpu {
89	power-supply = <&sw1c_reg>;
90};
91
92&i2c1 {
93	clock-frequency = <100000>;
94	pinctrl-names = "default", "gpio";
95	pinctrl-0 = <&pinctrl_i2c1>;
96	pinctrl-1 = <&pinctrl_i2c1_gpio>;
97	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
98	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
99	status = "okay";
100
101	pfuze100: pmic@8 {
102		compatible = "fsl,pfuze100";
103		fsl,pfuze-support-disable-sw;
104		reg = <0x8>;
105
106		regulators {
107			/* VDD_GPU */
108			sw1a_reg: sw1ab {
109				regulator-min-microvolt = <825000>;
110				regulator-max-microvolt = <1100000>;
111			};
112
113			/* VDD_VPU */
114			sw1c_reg: sw1c {
115				regulator-min-microvolt = <825000>;
116				regulator-max-microvolt = <1100000>;
117			};
118
119			/* NVCC_DRAM */
120			sw2_reg: sw2 {
121				regulator-min-microvolt = <1100000>;
122				regulator-max-microvolt = <1100000>;
123				regulator-always-on;
124			};
125
126			/* VDD_DRAM */
127			sw3a_reg: sw3ab {
128				regulator-min-microvolt = <825000>;
129				regulator-max-microvolt = <1100000>;
130				regulator-always-on;
131			};
132
133			/* 1.8 V for QSPI NOR, e-MMC IO, must not be changed */
134			nvcc_1v8_reg: sw4 {
135				regulator-min-microvolt = <1800000>;
136				regulator-max-microvolt = <1800000>;
137				regulator-always-on;
138			};
139
140			swbst_reg: swbst {
141				regulator-min-microvolt = <5000000>;
142				regulator-max-microvolt = <5150000>;
143			};
144
145			snvs_reg: vsnvs {
146				regulator-min-microvolt = <1000000>;
147				regulator-max-microvolt = <3000000>;
148				regulator-always-on;
149			};
150
151			vref_reg: vrefddr {
152				regulator-always-on;
153			};
154
155			/* not used */
156			vgen1_reg: vgen1 {
157				regulator-min-microvolt = <800000>;
158				regulator-max-microvolt = <1550000>;
159			};
160
161			/* VDD_PHY_0V9 */
162			vgen2_reg: vgen2 {
163				regulator-min-microvolt = <850000>;
164				regulator-max-microvolt = <975000>;
165				regulator-always-on;
166			};
167
168			/* VDD_PHY_1V8 */
169			vgen3_reg: vgen3 {
170				regulator-min-microvolt = <1675000>;
171				regulator-max-microvolt = <1975000>;
172				regulator-always-on;
173			};
174
175			/* VDDA_1V8 */
176			vgen4_reg: vgen4 {
177				regulator-min-microvolt = <1625000>;
178				regulator-max-microvolt = <1875000>;
179				regulator-always-on;
180			};
181
182			/* VDD_PHY_3V3 */
183			vgen5_reg: vgen5 {
184				regulator-min-microvolt = <3075000>;
185				regulator-max-microvolt = <3625000>;
186				regulator-always-on;
187			};
188
189			/* not used */
190			vgen6_reg: vgen6 {
191				regulator-min-microvolt = <1800000>;
192				regulator-max-microvolt = <3300000>;
193			};
194		};
195	};
196
197	sensor0: temperature-sensor-eeprom@1b {
198		compatible = "nxp,se97", "jedec,jc-42.4-temp";
199		reg = <0x1b>;
200	};
201
202	pcf85063: rtc@51 {
203		compatible = "nxp,pcf85063a";
204		reg = <0x51>;
205		pinctrl-names = "default";
206		pinctrl-0 = <&pinctrl_rtc>;
207		interrupt-parent = <&gpio1>;
208		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
209		quartz-load-femtofarads = <7000>;
210
211		clock {
212			compatible = "fixed-clock";
213			#clock-cells = <0>;
214			clock-frequency = <32768>;
215		};
216	};
217
218	eeprom1: eeprom@53 {
219		compatible = "nxp,se97b", "atmel,24c02";
220		reg = <0x53>;
221		pagesize = <16>;
222		read-only;
223	};
224
225	eeprom0: eeprom@57 {
226		compatible = "atmel,24c64";
227		reg = <0x57>;
228		pagesize = <32>;
229	};
230};
231
232&pcie0 {
233	/* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
234	vph-supply = <&vgen5_reg>;
235};
236
237&pcie1 {
238	/* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
239	vph-supply = <&vgen5_reg>;
240};
241
242&qspi0 {
243	pinctrl-names = "default";
244	pinctrl-0 = <&pinctrl_qspi>;
245	assigned-clocks = <&clk IMX8MQ_CLK_QSPI>;
246	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>;
247	status = "okay";
248
249	flash0: flash@0 {
250		compatible = "jedec,spi-nor";
251		reg = <0>;
252		#address-cells = <1>;
253		#size-cells = <1>;
254		spi-max-frequency = <84000000>;
255		spi-tx-bus-width = <1>;
256		spi-rx-bus-width = <4>;
257	};
258};
259
260&usdhc1 {
261	pinctrl-names = "default", "state_100mhz", "state_200mhz";
262	pinctrl-0 = <&pinctrl_usdhc1>;
263	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
264	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
265	bus-width = <8>;
266	non-removable;
267	no-sd;
268	no-sdio;
269	vmmc-supply = <&reg_vcc3v3>;
270	vqmmc-supply = <&reg_vcc1v8>;
271	status = "okay";
272};
273
274/* Attention: wdog reset forcing POR needs baseboard support */
275&wdog1 {
276	status = "okay";
277};
278
279&iomuxc {
280	pinctrl_dvfs: dvfsgrp {
281		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x16>;
282	};
283
284	pinctrl_i2c1: i2c1grp {
285		fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000007f>,
286			   <MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000007f>;
287	};
288
289	pinctrl_i2c1_gpio: i2c1gpiogrp {
290		fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14		0x40000074>,
291			   <MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15		0x40000074>;
292	};
293
294	pinctrl_qspi: qspigrp {
295		fsl,pins = <MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x97>,
296			   <MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82>,
297			   <MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x97>,
298			   <MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x97>,
299			   <MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x97>,
300			   <MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x97>;
301	};
302
303	pinctrl_rtc: rtcgrp {
304		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x41>;
305	};
306
307	pinctrl_usdhc1: usdhc1grp {
308		fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x83>,
309			   <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc3>,
310			   <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3>,
311			   <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3>,
312			   <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3>,
313			   <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3>,
314			   <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3>,
315			   <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3>,
316			   <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3>,
317			   <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3>,
318			   <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x83>,
319			   <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1>;
320	};
321
322	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
323		fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x85>,
324			   <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc5>,
325			   <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5>,
326			   <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5>,
327			   <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5>,
328			   <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5>,
329			   <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5>,
330			   <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5>,
331			   <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5>,
332			   <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5>,
333			   <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x85>,
334			   <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1>;
335	};
336
337	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
338		fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK		0x87>,
339			   <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD		0xc7>,
340			   <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7>,
341			   <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7>,
342			   <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7>,
343			   <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7>,
344			   <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7>,
345			   <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7>,
346			   <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7>,
347			   <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7>,
348			   <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE	0x87>,
349			   <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B	0xc1>;
350	};
351
352	pinctrl_wdog: wdoggrp {
353		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6>;
354	};
355};
356