1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
4 */
5
6#include "imx8mq.dtsi"
7
8/ {
9	reg_vdd_3v3: regulator-vdd-3v3 {
10		compatible = "regulator-fixed";
11		regulator-always-on;
12		regulator-name = "vdd_3v3";
13		regulator-min-microvolt = <3300000>;
14		regulator-max-microvolt = <3300000>;
15	};
16};
17
18&fec1 {
19	pinctrl-names = "default";
20	pinctrl-0 = <&pinctrl_fec1>;
21	phy-mode = "rgmii-id";
22	phy-handle = <&ethphy0>;
23	phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
24	phy-reset-duration = <2>;
25	fsl,magic-packet;
26	status = "okay";
27
28	mdio {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		ethphy0: ethernet-phy@4 {
33			compatible = "ethernet-phy-ieee802.3-c22";
34			reg = <4>;
35		};
36	};
37};
38
39&i2c1 {
40	pinctrl-names = "default";
41	pinctrl-0 = <&pinctrl_i2c1>;
42	clock-frequency = <400000>;
43	status = "okay";
44
45	pmic: pmic@8 {
46		compatible = "fsl,pfuze100";
47		reg = <0x08>;
48
49		regulators {
50			sw1a_reg: sw1ab {
51				regulator-min-microvolt = <300000>;
52				regulator-max-microvolt = <1875000>;
53			};
54
55			sw1c_reg: sw1c {
56				regulator-min-microvolt = <300000>;
57				regulator-max-microvolt = <1875000>;
58			};
59
60			sw2_reg: sw2 {
61				regulator-min-microvolt = <800000>;
62				regulator-max-microvolt = <3300000>;
63				regulator-always-on;
64			};
65
66			sw3a_reg: sw3ab {
67				regulator-min-microvolt = <400000>;
68				regulator-max-microvolt = <1975000>;
69				regulator-always-on;
70			};
71
72			sw4_reg: sw4 {
73				regulator-min-microvolt = <800000>;
74				regulator-max-microvolt = <3300000>;
75				regulator-always-on;
76			};
77
78			swbst_reg: swbst {
79				regulator-min-microvolt = <5000000>;
80				regulator-max-microvolt = <5150000>;
81			};
82
83			snvs_reg: vsnvs {
84				regulator-min-microvolt = <1000000>;
85				regulator-max-microvolt = <3000000>;
86				regulator-always-on;
87			};
88
89			vref_reg: vrefddr {
90				regulator-always-on;
91			};
92
93			vgen1_reg: vgen1 {
94				regulator-min-microvolt = <800000>;
95				regulator-max-microvolt = <1550000>;
96			};
97
98			vgen2_reg: vgen2 {
99				regulator-min-microvolt = <800000>;
100				regulator-max-microvolt = <1550000>;
101				regulator-always-on;
102			};
103
104			vgen3_reg: vgen3 {
105				regulator-min-microvolt = <1800000>;
106				regulator-max-microvolt = <3300000>;
107				regulator-always-on;
108			};
109
110			vgen4_reg: vgen4 {
111				regulator-min-microvolt = <1800000>;
112				regulator-max-microvolt = <3300000>;
113				regulator-always-on;
114			};
115
116			vgen5_reg: vgen5 {
117				regulator-min-microvolt = <1800000>;
118				regulator-max-microvolt = <3300000>;
119				regulator-always-on;
120			};
121
122			vgen6_reg: vgen6 {
123				regulator-min-microvolt = <1800000>;
124				regulator-max-microvolt = <3300000>;
125			};
126		};
127	};
128};
129
130&pgc_gpu{
131	power-supply = <&sw1a_reg>;
132};
133
134&pgc_vpu {
135	power-supply = <&sw1c_reg>;
136};
137
138&qspi0 {
139	pinctrl-names = "default";
140	pinctrl-0 = <&pinctrl_qspi>;
141	status = "okay";
142
143	/* SPI flash; not assembled by default */
144	spi_flash: flash@0 {
145		#address-cells = <1>;
146		#size-cells = <1>;
147		reg = <0>;
148		compatible = "micron,n25q256a", "jedec,spi-nor";
149		spi-max-frequency = <29000000>;
150		status = "disabled";
151	};
152};
153
154&uart1 { /* console */
155	pinctrl-names = "default";
156	pinctrl-0 = <&pinctrl_uart1>;
157	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
158	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
159	assigned-clock-rates = <25000000>;
160	status = "okay";
161};
162
163&uart4 { /* ublox BT */
164	pinctrl-names = "default";
165	pinctrl-0 = <&pinctrl_uart4>;
166	assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
167	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
168	assigned-clock-rates = <80000000>;
169	status = "okay";
170};
171
172&usdhc1 {
173	pinctrl-names = "default", "state_100mhz", "state_200mhz";
174	pinctrl-0 = <&pinctrl_usdhc1>;
175	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
176	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
177	bus-width = <8>;
178	non-removable;
179	status = "okay";
180};
181
182&wdog1 {
183	pinctrl-names = "default";
184	pinctrl-0 = <&pinctrl_wdog>;
185	fsl,ext-reset-output;
186	status = "okay";
187};
188
189&iomuxc {
190	pinctrl_fec1: fec1grp {
191		fsl,pins = <
192			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
193			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
194			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
195			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
196			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
197			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
198			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
199			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
200			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
201			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
202			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
203			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
204			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
205			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
206			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
207		>;
208	};
209
210	pinctrl_i2c1: i2c1grp {
211		fsl,pins = <
212			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
213			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
214		>;
215	};
216
217	pinctrl_pcie0: pcie0grp {
218		fsl,pins = <
219			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B	0x74
220			MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x16
221			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x16
222		>;
223	};
224
225	pinctrl_qspi: qspigrp {
226		fsl,pins = <
227			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
228			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
229			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
230			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
231			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
232			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
233
234		>;
235	};
236
237	pinctrl_uart1: uart1grp {
238		fsl,pins = <
239			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
240			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
241			MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2		0x19
242		>;
243	};
244
245	pinctrl_uart4: uart4grp {
246		fsl,pins = <
247			MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX		0x49
248			MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX		0x49
249			MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1			0x19
250		>;
251	};
252
253	pinctrl_usdhc1: usdhc1grp {
254		fsl,pins = <
255			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
256			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
257			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
258			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
259			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
260			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
261			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
262			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
263			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
264			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
265			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
266			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
267		>;
268	};
269
270	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
271		fsl,pins = <
272			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
273			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
274			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
275			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
276			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
277			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
278			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
279			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
280			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
281			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
282			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
283			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
284		>;
285	};
286
287	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
288		fsl,pins = <
289			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
290			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
291			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
292			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
293			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
294			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
295			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
296			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
297			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
298			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
299			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
300			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
301		>;
302	};
303
304	pinctrl_wdog: wdoggrp {
305		fsl,pins = <
306			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
307		>;
308	};
309};
310