1356c2722SRichard Hu// SPDX-License-Identifier: GPL-2.0+ 2356c2722SRichard Hu/* 3356c2722SRichard Hu * Copyright 2018 Wandboard, Org. 4356c2722SRichard Hu * Copyright 2017 NXP 5356c2722SRichard Hu * 6356c2722SRichard Hu * Author: Richard Hu <hakahu@gmail.com> 7356c2722SRichard Hu */ 8356c2722SRichard Hu 9356c2722SRichard Hu/dts-v1/; 10356c2722SRichard Hu 11356c2722SRichard Hu#include "imx8mq.dtsi" 12356c2722SRichard Hu 13356c2722SRichard Hu/ { 14356c2722SRichard Hu model = "TechNexion PICO-PI-8M"; 15356c2722SRichard Hu compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq"; 16356c2722SRichard Hu 17356c2722SRichard Hu chosen { 18356c2722SRichard Hu stdout-path = &uart1; 19356c2722SRichard Hu }; 20356c2722SRichard Hu 21356c2722SRichard Hu pmic_osc: clock-pmic { 22356c2722SRichard Hu compatible = "fixed-clock"; 23356c2722SRichard Hu #clock-cells = <0>; 24356c2722SRichard Hu clock-frequency = <32768>; 25356c2722SRichard Hu clock-output-names = "pmic_osc"; 26356c2722SRichard Hu }; 27356c2722SRichard Hu 28356c2722SRichard Hu reg_usb_otg_vbus: regulator-usb-otg-vbus { 29356c2722SRichard Hu pinctrl-names = "default"; 30356c2722SRichard Hu pinctrl-0 = <&pinctrl_otg_vbus>; 31356c2722SRichard Hu compatible = "regulator-fixed"; 32356c2722SRichard Hu regulator-name = "usb_otg_vbus"; 33356c2722SRichard Hu regulator-min-microvolt = <5000000>; 34356c2722SRichard Hu regulator-max-microvolt = <5000000>; 35356c2722SRichard Hu gpio = <&gpio3 14 GPIO_ACTIVE_LOW>; 36356c2722SRichard Hu }; 37356c2722SRichard Hu}; 38356c2722SRichard Hu 39356c2722SRichard Hu&fec1 { 40356c2722SRichard Hu pinctrl-names = "default"; 41356c2722SRichard Hu pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>; 42356c2722SRichard Hu phy-mode = "rgmii-id"; 43356c2722SRichard Hu phy-handle = <ðphy0>; 44356c2722SRichard Hu fsl,magic-packet; 45356c2722SRichard Hu status = "okay"; 46356c2722SRichard Hu 47356c2722SRichard Hu mdio { 48356c2722SRichard Hu #address-cells = <1>; 49356c2722SRichard Hu #size-cells = <0>; 50356c2722SRichard Hu 51356c2722SRichard Hu ethphy0: ethernet-phy@1 { 52356c2722SRichard Hu compatible = "ethernet-phy-ieee802.3-c22"; 53356c2722SRichard Hu reg = <1>; 54356c2722SRichard Hu }; 55356c2722SRichard Hu }; 56356c2722SRichard Hu}; 57356c2722SRichard Hu 58356c2722SRichard Hu&i2c1 { 59356c2722SRichard Hu clock-frequency = <100000>; 60356c2722SRichard Hu pinctrl-names = "default"; 61356c2722SRichard Hu pinctrl-0 = <&pinctrl_i2c1>; 62356c2722SRichard Hu status = "okay"; 63356c2722SRichard Hu 64356c2722SRichard Hu pmic: pmic@4b { 65356c2722SRichard Hu reg = <0x4b>; 66356c2722SRichard Hu compatible = "rohm,bd71837"; 67356c2722SRichard Hu pinctrl-names = "default"; 68356c2722SRichard Hu pinctrl-0 = <&pinctrl_pmic>; 69356c2722SRichard Hu clocks = <&pmic_osc>; 70356c2722SRichard Hu clock-names = "osc"; 71356c2722SRichard Hu clock-output-names = "pmic_clk"; 72356c2722SRichard Hu interrupt-parent = <&gpio1>; 73356c2722SRichard Hu interrupts = <3 GPIO_ACTIVE_LOW>; 74356c2722SRichard Hu interrupt-names = "irq"; 75356c2722SRichard Hu 76356c2722SRichard Hu regulators { 77356c2722SRichard Hu buck1: BUCK1 { 78356c2722SRichard Hu regulator-name = "buck1"; 79356c2722SRichard Hu regulator-min-microvolt = <700000>; 80356c2722SRichard Hu regulator-max-microvolt = <1300000>; 81356c2722SRichard Hu regulator-boot-on; 82356c2722SRichard Hu regulator-ramp-delay = <1250>; 83356c2722SRichard Hu rohm,dvs-run-voltage = <900000>; 84356c2722SRichard Hu rohm,dvs-idle-voltage = <850000>; 85356c2722SRichard Hu rohm,dvs-suspend-voltage = <800000>; 86356c2722SRichard Hu }; 87356c2722SRichard Hu 88356c2722SRichard Hu buck2: BUCK2 { 89356c2722SRichard Hu regulator-name = "buck2"; 90356c2722SRichard Hu regulator-min-microvolt = <700000>; 91356c2722SRichard Hu regulator-max-microvolt = <1300000>; 92356c2722SRichard Hu regulator-boot-on; 93356c2722SRichard Hu regulator-ramp-delay = <1250>; 94356c2722SRichard Hu rohm,dvs-run-voltage = <1000000>; 95356c2722SRichard Hu rohm,dvs-idle-voltage = <900000>; 96356c2722SRichard Hu }; 97356c2722SRichard Hu 98356c2722SRichard Hu buck3: BUCK3 { 99356c2722SRichard Hu regulator-name = "buck3"; 100356c2722SRichard Hu regulator-min-microvolt = <700000>; 101356c2722SRichard Hu regulator-max-microvolt = <1300000>; 102356c2722SRichard Hu regulator-boot-on; 103356c2722SRichard Hu rohm,dvs-run-voltage = <1000000>; 104356c2722SRichard Hu }; 105356c2722SRichard Hu 106356c2722SRichard Hu buck4: BUCK4 { 107356c2722SRichard Hu regulator-name = "buck4"; 108356c2722SRichard Hu regulator-min-microvolt = <700000>; 109356c2722SRichard Hu regulator-max-microvolt = <1300000>; 110356c2722SRichard Hu regulator-boot-on; 111356c2722SRichard Hu rohm,dvs-run-voltage = <1000000>; 112356c2722SRichard Hu }; 113356c2722SRichard Hu 114356c2722SRichard Hu buck5: BUCK5 { 115356c2722SRichard Hu regulator-name = "buck5"; 116356c2722SRichard Hu regulator-min-microvolt = <700000>; 117356c2722SRichard Hu regulator-max-microvolt = <1350000>; 118356c2722SRichard Hu regulator-boot-on; 119356c2722SRichard Hu }; 120356c2722SRichard Hu 121356c2722SRichard Hu buck6: BUCK6 { 122356c2722SRichard Hu regulator-name = "buck6"; 123356c2722SRichard Hu regulator-min-microvolt = <3000000>; 124356c2722SRichard Hu regulator-max-microvolt = <3300000>; 125356c2722SRichard Hu regulator-boot-on; 126356c2722SRichard Hu }; 127356c2722SRichard Hu 128356c2722SRichard Hu buck7: BUCK7 { 129356c2722SRichard Hu regulator-name = "buck7"; 130356c2722SRichard Hu regulator-min-microvolt = <1605000>; 131356c2722SRichard Hu regulator-max-microvolt = <1995000>; 132356c2722SRichard Hu regulator-boot-on; 133356c2722SRichard Hu }; 134356c2722SRichard Hu 135356c2722SRichard Hu buck8: BUCK8 { 136356c2722SRichard Hu regulator-name = "buck8"; 137356c2722SRichard Hu regulator-min-microvolt = <800000>; 138356c2722SRichard Hu regulator-max-microvolt = <1400000>; 139356c2722SRichard Hu regulator-boot-on; 140356c2722SRichard Hu }; 141356c2722SRichard Hu 142356c2722SRichard Hu ldo1: LDO1 { 143356c2722SRichard Hu regulator-name = "ldo1"; 144356c2722SRichard Hu regulator-min-microvolt = <3000000>; 145356c2722SRichard Hu regulator-max-microvolt = <3300000>; 146356c2722SRichard Hu regulator-boot-on; 147356c2722SRichard Hu regulator-always-on; 148356c2722SRichard Hu }; 149356c2722SRichard Hu 150356c2722SRichard Hu ldo2: LDO2 { 151356c2722SRichard Hu regulator-name = "ldo2"; 152356c2722SRichard Hu regulator-min-microvolt = <900000>; 153356c2722SRichard Hu regulator-max-microvolt = <900000>; 154356c2722SRichard Hu regulator-boot-on; 155356c2722SRichard Hu regulator-always-on; 156356c2722SRichard Hu }; 157356c2722SRichard Hu 158356c2722SRichard Hu ldo3: LDO3 { 159356c2722SRichard Hu regulator-name = "ldo3"; 160356c2722SRichard Hu regulator-min-microvolt = <1800000>; 161356c2722SRichard Hu regulator-max-microvolt = <3300000>; 162356c2722SRichard Hu regulator-boot-on; 163356c2722SRichard Hu }; 164356c2722SRichard Hu 165356c2722SRichard Hu ldo4: LDO4 { 166356c2722SRichard Hu regulator-name = "ldo4"; 167356c2722SRichard Hu regulator-min-microvolt = <900000>; 168356c2722SRichard Hu regulator-max-microvolt = <1800000>; 169356c2722SRichard Hu regulator-boot-on; 170356c2722SRichard Hu }; 171356c2722SRichard Hu 172356c2722SRichard Hu ldo5: LDO5 { 173356c2722SRichard Hu regulator-name = "ldo5"; 174356c2722SRichard Hu regulator-min-microvolt = <1800000>; 175356c2722SRichard Hu regulator-max-microvolt = <3300000>; 176356c2722SRichard Hu regulator-boot-on; 177356c2722SRichard Hu }; 178356c2722SRichard Hu 179356c2722SRichard Hu ldo6: LDO6 { 180356c2722SRichard Hu regulator-name = "ldo6"; 181356c2722SRichard Hu regulator-min-microvolt = <900000>; 182356c2722SRichard Hu regulator-max-microvolt = <1800000>; 183356c2722SRichard Hu regulator-boot-on; 184356c2722SRichard Hu }; 185356c2722SRichard Hu 186356c2722SRichard Hu ldo7: LDO7 { 187356c2722SRichard Hu regulator-name = "ldo7"; 188356c2722SRichard Hu regulator-min-microvolt = <1800000>; 189356c2722SRichard Hu regulator-max-microvolt = <3300000>; 190356c2722SRichard Hu regulator-boot-on; 191356c2722SRichard Hu }; 192356c2722SRichard Hu }; 193356c2722SRichard Hu }; 194356c2722SRichard Hu}; 195356c2722SRichard Hu 196356c2722SRichard Hu&i2c2 { 197356c2722SRichard Hu clock-frequency = <100000>; 198356c2722SRichard Hu pinctrl-names = "default"; 199356c2722SRichard Hu pinctrl-0 = <&pinctrl_i2c2>; 200356c2722SRichard Hu status = "okay"; 201356c2722SRichard Hu}; 202356c2722SRichard Hu 203356c2722SRichard Hu&uart1 { /* console */ 204356c2722SRichard Hu pinctrl-names = "default"; 205356c2722SRichard Hu pinctrl-0 = <&pinctrl_uart1>; 206356c2722SRichard Hu status = "okay"; 207356c2722SRichard Hu}; 208356c2722SRichard Hu 209356c2722SRichard Hu&usdhc1 { 210e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 211e045f044SAnson Huang assigned-clock-rates = <400000000>; 212356c2722SRichard Hu pinctrl-names = "default", "state_100mhz", "state_200mhz"; 213356c2722SRichard Hu pinctrl-0 = <&pinctrl_usdhc1>; 214356c2722SRichard Hu pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 215356c2722SRichard Hu pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 216356c2722SRichard Hu bus-width = <8>; 217356c2722SRichard Hu non-removable; 218356c2722SRichard Hu status = "okay"; 219356c2722SRichard Hu}; 220356c2722SRichard Hu 221356c2722SRichard Hu&usdhc2 { 222e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 223e045f044SAnson Huang assigned-clock-rates = <200000000>; 224356c2722SRichard Hu pinctrl-names = "default", "state_100mhz", "state_200mhz"; 225356c2722SRichard Hu pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 226356c2722SRichard Hu pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 227356c2722SRichard Hu pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 228356c2722SRichard Hu bus-width = <4>; 229356c2722SRichard Hu cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 230356c2722SRichard Hu status = "okay"; 231356c2722SRichard Hu}; 232356c2722SRichard Hu 233356c2722SRichard Hu&usb3_phy0 { 234356c2722SRichard Hu status = "okay"; 235356c2722SRichard Hu}; 236356c2722SRichard Hu 237356c2722SRichard Hu&usb3_phy1 { 238356c2722SRichard Hu status = "okay"; 239356c2722SRichard Hu}; 240356c2722SRichard Hu 241356c2722SRichard Hu&usb_dwc3_1 { 242356c2722SRichard Hu dr_mode = "host"; 243356c2722SRichard Hu status = "okay"; 244356c2722SRichard Hu}; 245356c2722SRichard Hu 246356c2722SRichard Hu&wdog1 { 247356c2722SRichard Hu pinctrl-names = "default"; 248356c2722SRichard Hu pinctrl-0 = <&pinctrl_wdog>; 249356c2722SRichard Hu fsl,ext-reset-output; 250356c2722SRichard Hu status = "okay"; 251356c2722SRichard Hu}; 252356c2722SRichard Hu 253356c2722SRichard Hu&iomuxc { 254356c2722SRichard Hu pinctrl_enet_3v3: enet3v3grp { 255356c2722SRichard Hu fsl,pins = < 256356c2722SRichard Hu MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 257356c2722SRichard Hu >; 258356c2722SRichard Hu }; 259356c2722SRichard Hu 260356c2722SRichard Hu pinctrl_fec1: fec1grp { 261356c2722SRichard Hu fsl,pins = < 262356c2722SRichard Hu MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 263356c2722SRichard Hu MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 264356c2722SRichard Hu MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 265356c2722SRichard Hu MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 266356c2722SRichard Hu MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 267356c2722SRichard Hu MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 268356c2722SRichard Hu MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 269356c2722SRichard Hu MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 270356c2722SRichard Hu MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 271356c2722SRichard Hu MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 272356c2722SRichard Hu MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 273356c2722SRichard Hu MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 274356c2722SRichard Hu MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 275356c2722SRichard Hu MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 276356c2722SRichard Hu MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 277356c2722SRichard Hu >; 278356c2722SRichard Hu }; 279356c2722SRichard Hu 280356c2722SRichard Hu pinctrl_i2c1: i2c1grp { 281356c2722SRichard Hu fsl,pins = < 282356c2722SRichard Hu MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 283356c2722SRichard Hu MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 284356c2722SRichard Hu >; 285356c2722SRichard Hu }; 286356c2722SRichard Hu 287356c2722SRichard Hu pinctrl_i2c2: i2c2grp { 288356c2722SRichard Hu fsl,pins = < 289356c2722SRichard Hu MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f 290356c2722SRichard Hu MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f 291356c2722SRichard Hu >; 292356c2722SRichard Hu }; 293356c2722SRichard Hu 294356c2722SRichard Hu pinctrl_otg_vbus: otgvbusgrp { 295356c2722SRichard Hu fsl,pins = < 296356c2722SRichard Hu MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */ 297356c2722SRichard Hu >; 298356c2722SRichard Hu }; 299356c2722SRichard Hu 30002485f4aSKrzysztof Kozlowski pinctrl_pmic: pmicirqgrp { 301356c2722SRichard Hu fsl,pins = < 302356c2722SRichard Hu MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 303356c2722SRichard Hu >; 304356c2722SRichard Hu }; 305356c2722SRichard Hu 306356c2722SRichard Hu pinctrl_uart1: uart1grp { 307356c2722SRichard Hu fsl,pins = < 308356c2722SRichard Hu MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 309356c2722SRichard Hu MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 310356c2722SRichard Hu >; 311356c2722SRichard Hu }; 312356c2722SRichard Hu 313356c2722SRichard Hu pinctrl_uart2: uart2grp { 314356c2722SRichard Hu fsl,pins = < 315356c2722SRichard Hu MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 316356c2722SRichard Hu MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 317356c2722SRichard Hu MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 318356c2722SRichard Hu MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 319356c2722SRichard Hu >; 320356c2722SRichard Hu }; 321356c2722SRichard Hu 322356c2722SRichard Hu pinctrl_usdhc1: usdhc1grp { 323356c2722SRichard Hu fsl,pins = < 324356c2722SRichard Hu MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 325356c2722SRichard Hu MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 326356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 327356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 328356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 329356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 330356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 331356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 332356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 333356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 334356c2722SRichard Hu MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 335356c2722SRichard Hu >; 336356c2722SRichard Hu }; 337356c2722SRichard Hu 33802485f4aSKrzysztof Kozlowski pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 339356c2722SRichard Hu fsl,pins = < 340356c2722SRichard Hu MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 341356c2722SRichard Hu MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 342356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 343356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 344356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 345356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 346356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 347356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 348356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 349356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 350356c2722SRichard Hu MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 351356c2722SRichard Hu >; 352356c2722SRichard Hu }; 353356c2722SRichard Hu 35402485f4aSKrzysztof Kozlowski pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 355356c2722SRichard Hu fsl,pins = < 356356c2722SRichard Hu MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 357356c2722SRichard Hu MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 358356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 359356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 360356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 361356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 362356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 363356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 364356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 365356c2722SRichard Hu MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 366356c2722SRichard Hu MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 367356c2722SRichard Hu >; 368356c2722SRichard Hu }; 369356c2722SRichard Hu 37002485f4aSKrzysztof Kozlowski pinctrl_usdhc2_gpio: usdhc2gpiogrp { 371356c2722SRichard Hu fsl,pins = < 372356c2722SRichard Hu MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 373356c2722SRichard Hu >; 374356c2722SRichard Hu }; 375356c2722SRichard Hu 376356c2722SRichard Hu pinctrl_usdhc2: usdhc2grp { 377356c2722SRichard Hu fsl,pins = < 378356c2722SRichard Hu MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 379356c2722SRichard Hu MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 380356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 381356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 382356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 383356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 384356c2722SRichard Hu MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 385356c2722SRichard Hu >; 386356c2722SRichard Hu }; 387356c2722SRichard Hu 38802485f4aSKrzysztof Kozlowski pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 389356c2722SRichard Hu fsl,pins = < 390356c2722SRichard Hu MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 391356c2722SRichard Hu MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 392356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 393356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 394356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 395356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 396356c2722SRichard Hu MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 397356c2722SRichard Hu >; 398356c2722SRichard Hu }; 399356c2722SRichard Hu 40002485f4aSKrzysztof Kozlowski pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 401356c2722SRichard Hu fsl,pins = < 402356c2722SRichard Hu MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 403356c2722SRichard Hu MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 404356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 405356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 406356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 407356c2722SRichard Hu MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 408356c2722SRichard Hu MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 409356c2722SRichard Hu >; 410356c2722SRichard Hu }; 411356c2722SRichard Hu 412356c2722SRichard Hu pinctrl_wdog: wdoggrp { 413356c2722SRichard Hu fsl,pins = < 414356c2722SRichard Hu MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 415356c2722SRichard Hu >; 416356c2722SRichard Hu }; 417356c2722SRichard Hu}; 418