1356c2722SRichard Hu// SPDX-License-Identifier: GPL-2.0+
2356c2722SRichard Hu/*
3356c2722SRichard Hu * Copyright 2018 Wandboard, Org.
4356c2722SRichard Hu * Copyright 2017 NXP
5356c2722SRichard Hu *
6356c2722SRichard Hu * Author: Richard Hu <hakahu@gmail.com>
7356c2722SRichard Hu */
8356c2722SRichard Hu
9356c2722SRichard Hu/dts-v1/;
10356c2722SRichard Hu
11356c2722SRichard Hu#include "imx8mq.dtsi"
12d8fa4792SKrzysztof Kozlowski#include <dt-bindings/interrupt-controller/irq.h>
13356c2722SRichard Hu
14356c2722SRichard Hu/ {
15356c2722SRichard Hu	model = "TechNexion PICO-PI-8M";
16356c2722SRichard Hu	compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
17356c2722SRichard Hu
18356c2722SRichard Hu	chosen {
19356c2722SRichard Hu		stdout-path = &uart1;
20356c2722SRichard Hu	};
21356c2722SRichard Hu
22356c2722SRichard Hu	pmic_osc: clock-pmic {
23356c2722SRichard Hu		compatible = "fixed-clock";
24356c2722SRichard Hu		#clock-cells = <0>;
25356c2722SRichard Hu		clock-frequency = <32768>;
26356c2722SRichard Hu		clock-output-names = "pmic_osc";
27356c2722SRichard Hu	};
28356c2722SRichard Hu
29356c2722SRichard Hu	reg_usb_otg_vbus: regulator-usb-otg-vbus {
30356c2722SRichard Hu		pinctrl-names = "default";
31356c2722SRichard Hu		pinctrl-0 = <&pinctrl_otg_vbus>;
32356c2722SRichard Hu		compatible = "regulator-fixed";
33356c2722SRichard Hu		regulator-name = "usb_otg_vbus";
34356c2722SRichard Hu		regulator-min-microvolt = <5000000>;
35356c2722SRichard Hu		regulator-max-microvolt = <5000000>;
36356c2722SRichard Hu		gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
37356c2722SRichard Hu	};
38356c2722SRichard Hu};
39356c2722SRichard Hu
40356c2722SRichard Hu&fec1 {
41356c2722SRichard Hu	pinctrl-names = "default";
42356c2722SRichard Hu	pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
43356c2722SRichard Hu	phy-mode = "rgmii-id";
44356c2722SRichard Hu	phy-handle = <&ethphy0>;
45356c2722SRichard Hu	fsl,magic-packet;
46356c2722SRichard Hu	status = "okay";
47356c2722SRichard Hu
48356c2722SRichard Hu	mdio {
49356c2722SRichard Hu		#address-cells = <1>;
50356c2722SRichard Hu		#size-cells = <0>;
51356c2722SRichard Hu
52356c2722SRichard Hu		ethphy0: ethernet-phy@1 {
53356c2722SRichard Hu			compatible = "ethernet-phy-ieee802.3-c22";
54356c2722SRichard Hu			reg = <1>;
55356c2722SRichard Hu		};
56356c2722SRichard Hu	};
57356c2722SRichard Hu};
58356c2722SRichard Hu
59356c2722SRichard Hu&i2c1 {
60356c2722SRichard Hu	clock-frequency = <100000>;
61356c2722SRichard Hu	pinctrl-names = "default";
62356c2722SRichard Hu	pinctrl-0 = <&pinctrl_i2c1>;
63356c2722SRichard Hu	status = "okay";
64356c2722SRichard Hu
65356c2722SRichard Hu	pmic: pmic@4b {
66356c2722SRichard Hu		reg = <0x4b>;
67356c2722SRichard Hu		compatible = "rohm,bd71837";
68356c2722SRichard Hu		pinctrl-names = "default";
69356c2722SRichard Hu		pinctrl-0 = <&pinctrl_pmic>;
70356c2722SRichard Hu		clocks = <&pmic_osc>;
71356c2722SRichard Hu		clock-names = "osc";
72356c2722SRichard Hu		clock-output-names = "pmic_clk";
73356c2722SRichard Hu		interrupt-parent = <&gpio1>;
74d8fa4792SKrzysztof Kozlowski		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
75356c2722SRichard Hu		interrupt-names = "irq";
76356c2722SRichard Hu
77356c2722SRichard Hu		regulators {
78356c2722SRichard Hu			buck1: BUCK1 {
79356c2722SRichard Hu				regulator-name = "buck1";
80356c2722SRichard Hu				regulator-min-microvolt = <700000>;
81356c2722SRichard Hu				regulator-max-microvolt = <1300000>;
82356c2722SRichard Hu				regulator-boot-on;
83356c2722SRichard Hu				regulator-ramp-delay = <1250>;
84356c2722SRichard Hu				rohm,dvs-run-voltage = <900000>;
85356c2722SRichard Hu				rohm,dvs-idle-voltage = <850000>;
86356c2722SRichard Hu				rohm,dvs-suspend-voltage = <800000>;
87356c2722SRichard Hu			};
88356c2722SRichard Hu
89356c2722SRichard Hu			buck2: BUCK2 {
90356c2722SRichard Hu				regulator-name = "buck2";
91356c2722SRichard Hu				regulator-min-microvolt = <700000>;
92356c2722SRichard Hu				regulator-max-microvolt = <1300000>;
93356c2722SRichard Hu				regulator-boot-on;
94356c2722SRichard Hu				regulator-ramp-delay = <1250>;
95356c2722SRichard Hu				rohm,dvs-run-voltage = <1000000>;
96356c2722SRichard Hu				rohm,dvs-idle-voltage = <900000>;
97356c2722SRichard Hu			};
98356c2722SRichard Hu
99356c2722SRichard Hu			buck3: BUCK3 {
100356c2722SRichard Hu				regulator-name = "buck3";
101356c2722SRichard Hu				regulator-min-microvolt = <700000>;
102356c2722SRichard Hu				regulator-max-microvolt = <1300000>;
103356c2722SRichard Hu				regulator-boot-on;
104356c2722SRichard Hu				rohm,dvs-run-voltage = <1000000>;
105356c2722SRichard Hu			};
106356c2722SRichard Hu
107356c2722SRichard Hu			buck4: BUCK4 {
108356c2722SRichard Hu				regulator-name = "buck4";
109356c2722SRichard Hu				regulator-min-microvolt = <700000>;
110356c2722SRichard Hu				regulator-max-microvolt = <1300000>;
111356c2722SRichard Hu				regulator-boot-on;
112356c2722SRichard Hu				rohm,dvs-run-voltage = <1000000>;
113356c2722SRichard Hu			};
114356c2722SRichard Hu
115356c2722SRichard Hu			buck5: BUCK5 {
116356c2722SRichard Hu				regulator-name = "buck5";
117356c2722SRichard Hu				regulator-min-microvolt = <700000>;
118356c2722SRichard Hu				regulator-max-microvolt = <1350000>;
119356c2722SRichard Hu				regulator-boot-on;
120356c2722SRichard Hu			};
121356c2722SRichard Hu
122356c2722SRichard Hu			buck6: BUCK6 {
123356c2722SRichard Hu				regulator-name = "buck6";
124356c2722SRichard Hu				regulator-min-microvolt = <3000000>;
125356c2722SRichard Hu				regulator-max-microvolt = <3300000>;
126356c2722SRichard Hu				regulator-boot-on;
127356c2722SRichard Hu			};
128356c2722SRichard Hu
129356c2722SRichard Hu			buck7: BUCK7 {
130356c2722SRichard Hu				regulator-name = "buck7";
131356c2722SRichard Hu				regulator-min-microvolt = <1605000>;
132356c2722SRichard Hu				regulator-max-microvolt = <1995000>;
133356c2722SRichard Hu				regulator-boot-on;
134356c2722SRichard Hu			};
135356c2722SRichard Hu
136356c2722SRichard Hu			buck8: BUCK8 {
137356c2722SRichard Hu				regulator-name = "buck8";
138356c2722SRichard Hu				regulator-min-microvolt = <800000>;
139356c2722SRichard Hu				regulator-max-microvolt = <1400000>;
140356c2722SRichard Hu				regulator-boot-on;
141356c2722SRichard Hu			};
142356c2722SRichard Hu
143356c2722SRichard Hu			ldo1: LDO1 {
144356c2722SRichard Hu				regulator-name = "ldo1";
145356c2722SRichard Hu				regulator-min-microvolt = <3000000>;
146356c2722SRichard Hu				regulator-max-microvolt = <3300000>;
147356c2722SRichard Hu				regulator-boot-on;
148356c2722SRichard Hu				regulator-always-on;
149356c2722SRichard Hu			};
150356c2722SRichard Hu
151356c2722SRichard Hu			ldo2: LDO2 {
152356c2722SRichard Hu				regulator-name = "ldo2";
153356c2722SRichard Hu				regulator-min-microvolt = <900000>;
154356c2722SRichard Hu				regulator-max-microvolt = <900000>;
155356c2722SRichard Hu				regulator-boot-on;
156356c2722SRichard Hu				regulator-always-on;
157356c2722SRichard Hu			};
158356c2722SRichard Hu
159356c2722SRichard Hu			ldo3: LDO3 {
160356c2722SRichard Hu				regulator-name = "ldo3";
161356c2722SRichard Hu				regulator-min-microvolt = <1800000>;
162356c2722SRichard Hu				regulator-max-microvolt = <3300000>;
163356c2722SRichard Hu				regulator-boot-on;
164356c2722SRichard Hu			};
165356c2722SRichard Hu
166356c2722SRichard Hu			ldo4: LDO4 {
167356c2722SRichard Hu				regulator-name = "ldo4";
168356c2722SRichard Hu				regulator-min-microvolt = <900000>;
169356c2722SRichard Hu				regulator-max-microvolt = <1800000>;
170356c2722SRichard Hu				regulator-boot-on;
171356c2722SRichard Hu			};
172356c2722SRichard Hu
173356c2722SRichard Hu			ldo5: LDO5 {
174356c2722SRichard Hu				regulator-name = "ldo5";
175356c2722SRichard Hu				regulator-min-microvolt = <1800000>;
176356c2722SRichard Hu				regulator-max-microvolt = <3300000>;
177356c2722SRichard Hu				regulator-boot-on;
178356c2722SRichard Hu			};
179356c2722SRichard Hu
180356c2722SRichard Hu			ldo6: LDO6 {
181356c2722SRichard Hu				regulator-name = "ldo6";
182356c2722SRichard Hu				regulator-min-microvolt = <900000>;
183356c2722SRichard Hu				regulator-max-microvolt = <1800000>;
184356c2722SRichard Hu				regulator-boot-on;
185356c2722SRichard Hu			};
186356c2722SRichard Hu
187356c2722SRichard Hu			ldo7: LDO7 {
188356c2722SRichard Hu				regulator-name = "ldo7";
189356c2722SRichard Hu				regulator-min-microvolt = <1800000>;
190356c2722SRichard Hu				regulator-max-microvolt = <3300000>;
191356c2722SRichard Hu				regulator-boot-on;
192356c2722SRichard Hu			};
193356c2722SRichard Hu		};
194356c2722SRichard Hu	};
195356c2722SRichard Hu};
196356c2722SRichard Hu
197356c2722SRichard Hu&i2c2 {
198356c2722SRichard Hu	clock-frequency = <100000>;
199356c2722SRichard Hu	pinctrl-names = "default";
200356c2722SRichard Hu	pinctrl-0 = <&pinctrl_i2c2>;
201356c2722SRichard Hu	status = "okay";
202356c2722SRichard Hu};
203356c2722SRichard Hu
204356c2722SRichard Hu&uart1 { /* console */
205356c2722SRichard Hu	pinctrl-names = "default";
206356c2722SRichard Hu	pinctrl-0 = <&pinctrl_uart1>;
207356c2722SRichard Hu	status = "okay";
208356c2722SRichard Hu};
209356c2722SRichard Hu
210356c2722SRichard Hu&usdhc1 {
211e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
212e045f044SAnson Huang	assigned-clock-rates = <400000000>;
213356c2722SRichard Hu	pinctrl-names = "default", "state_100mhz", "state_200mhz";
214356c2722SRichard Hu	pinctrl-0 = <&pinctrl_usdhc1>;
215356c2722SRichard Hu	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
216356c2722SRichard Hu	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
217356c2722SRichard Hu	bus-width = <8>;
218356c2722SRichard Hu	non-removable;
219356c2722SRichard Hu	status = "okay";
220356c2722SRichard Hu};
221356c2722SRichard Hu
222356c2722SRichard Hu&usdhc2 {
223e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
224e045f044SAnson Huang	assigned-clock-rates = <200000000>;
225356c2722SRichard Hu	pinctrl-names = "default", "state_100mhz", "state_200mhz";
226356c2722SRichard Hu	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
227356c2722SRichard Hu	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
228356c2722SRichard Hu	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
229356c2722SRichard Hu	bus-width = <4>;
230356c2722SRichard Hu	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
231356c2722SRichard Hu	status = "okay";
232356c2722SRichard Hu};
233356c2722SRichard Hu
234356c2722SRichard Hu&usb3_phy0 {
235356c2722SRichard Hu	status = "okay";
236356c2722SRichard Hu};
237356c2722SRichard Hu
238356c2722SRichard Hu&usb3_phy1 {
239356c2722SRichard Hu	status = "okay";
240356c2722SRichard Hu};
241356c2722SRichard Hu
242356c2722SRichard Hu&usb_dwc3_1 {
243356c2722SRichard Hu	dr_mode = "host";
244356c2722SRichard Hu	status = "okay";
245356c2722SRichard Hu};
246356c2722SRichard Hu
247356c2722SRichard Hu&wdog1 {
248356c2722SRichard Hu	pinctrl-names = "default";
249356c2722SRichard Hu	pinctrl-0 = <&pinctrl_wdog>;
250356c2722SRichard Hu	fsl,ext-reset-output;
251356c2722SRichard Hu	status = "okay";
252356c2722SRichard Hu};
253356c2722SRichard Hu
254356c2722SRichard Hu&iomuxc {
255356c2722SRichard Hu	pinctrl_enet_3v3: enet3v3grp {
256356c2722SRichard Hu		fsl,pins = <
257356c2722SRichard Hu			MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x19
258356c2722SRichard Hu		>;
259356c2722SRichard Hu	};
260356c2722SRichard Hu
261356c2722SRichard Hu	pinctrl_fec1: fec1grp {
262356c2722SRichard Hu		fsl,pins = <
263356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
264356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
265356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
266356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
267356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
268356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
269356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
270356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
271356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
272356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
273356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
274356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
275356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
276356c2722SRichard Hu			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
277356c2722SRichard Hu			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
278356c2722SRichard Hu		>;
279356c2722SRichard Hu	};
280356c2722SRichard Hu
281356c2722SRichard Hu	pinctrl_i2c1: i2c1grp {
282356c2722SRichard Hu		fsl,pins = <
283356c2722SRichard Hu			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
284356c2722SRichard Hu			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
285356c2722SRichard Hu		>;
286356c2722SRichard Hu	};
287356c2722SRichard Hu
288356c2722SRichard Hu	pinctrl_i2c2: i2c2grp {
289356c2722SRichard Hu		fsl,pins = <
290356c2722SRichard Hu			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
291356c2722SRichard Hu			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
292356c2722SRichard Hu		>;
293356c2722SRichard Hu	};
294356c2722SRichard Hu
295356c2722SRichard Hu	pinctrl_otg_vbus: otgvbusgrp {
296356c2722SRichard Hu		fsl,pins = <
297356c2722SRichard Hu			MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14		0x19   /* USB OTG VBUS Enable */
298356c2722SRichard Hu		>;
299356c2722SRichard Hu	};
300356c2722SRichard Hu
30102485f4aSKrzysztof Kozlowski	pinctrl_pmic: pmicirqgrp {
302356c2722SRichard Hu		fsl,pins = <
303356c2722SRichard Hu			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
304356c2722SRichard Hu		>;
305356c2722SRichard Hu	};
306356c2722SRichard Hu
307356c2722SRichard Hu	pinctrl_uart1: uart1grp {
308356c2722SRichard Hu		fsl,pins = <
309356c2722SRichard Hu			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
310356c2722SRichard Hu			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
311356c2722SRichard Hu		>;
312356c2722SRichard Hu	};
313356c2722SRichard Hu
314356c2722SRichard Hu	pinctrl_uart2: uart2grp {
315356c2722SRichard Hu		fsl,pins = <
316356c2722SRichard Hu			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
317356c2722SRichard Hu			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
318356c2722SRichard Hu			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
319356c2722SRichard Hu			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
320356c2722SRichard Hu		>;
321356c2722SRichard Hu	};
322356c2722SRichard Hu
323356c2722SRichard Hu	pinctrl_usdhc1: usdhc1grp {
324356c2722SRichard Hu		fsl,pins = <
325356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
326356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
327356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
328356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
329356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
330356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
331356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
332356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
333356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
334356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
335356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
336356c2722SRichard Hu		>;
337356c2722SRichard Hu	};
338356c2722SRichard Hu
33902485f4aSKrzysztof Kozlowski	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
340356c2722SRichard Hu		fsl,pins = <
341356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
342356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
343356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
344356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
345356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
346356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
347356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
348356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
349356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
350356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
351356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85
352356c2722SRichard Hu		>;
353356c2722SRichard Hu	};
354356c2722SRichard Hu
35502485f4aSKrzysztof Kozlowski	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
356356c2722SRichard Hu		fsl,pins = <
357356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
358356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
359356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
360356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
361356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
362356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
363356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
364356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
365356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
366356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
367356c2722SRichard Hu			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87
368356c2722SRichard Hu		>;
369356c2722SRichard Hu	};
370356c2722SRichard Hu
37102485f4aSKrzysztof Kozlowski	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
372356c2722SRichard Hu		fsl,pins = <
373356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
374356c2722SRichard Hu		>;
375356c2722SRichard Hu	};
376356c2722SRichard Hu
377356c2722SRichard Hu	pinctrl_usdhc2: usdhc2grp {
378356c2722SRichard Hu		fsl,pins = <
379356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
380356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
381356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
382356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
383356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
384356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
385356c2722SRichard Hu			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
386356c2722SRichard Hu		>;
387356c2722SRichard Hu	};
388356c2722SRichard Hu
38902485f4aSKrzysztof Kozlowski	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
390356c2722SRichard Hu		fsl,pins = <
391356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
392356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
393356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
394356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
395356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
396356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
397356c2722SRichard Hu			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
398356c2722SRichard Hu		>;
399356c2722SRichard Hu	};
400356c2722SRichard Hu
40102485f4aSKrzysztof Kozlowski	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
402356c2722SRichard Hu		fsl,pins = <
403356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
404356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
405356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
406356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
407356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
408356c2722SRichard Hu			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
409356c2722SRichard Hu			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
410356c2722SRichard Hu		>;
411356c2722SRichard Hu	};
412356c2722SRichard Hu
413356c2722SRichard Hu	pinctrl_wdog: wdoggrp {
414356c2722SRichard Hu		fsl,pins = <
415356c2722SRichard Hu			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
416356c2722SRichard Hu		>;
417356c2722SRichard Hu	};
418356c2722SRichard Hu};
419