1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3/*
4 * Copyright 2019-2021 MNT Research GmbH
5 * Copyright 2021 Lucas Stach <dev@lynxeye.de>
6 */
7
8/dts-v1/;
9
10#include "imx8mq-nitrogen-som.dtsi"
11
12/ {
13	model = "MNT Reform 2";
14	compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
15	chassis-type = "laptop";
16
17	pcie1_refclk: clock-pcie1-refclk {
18		compatible = "fixed-clock";
19		#clock-cells = <0>;
20		clock-frequency = <100000000>;
21	};
22
23	reg_main_5v: regulator-main-5v {
24		compatible = "regulator-fixed";
25		regulator-name = "5V";
26		regulator-min-microvolt = <5000000>;
27		regulator-max-microvolt = <5000000>;
28	};
29
30	reg_main_3v3: regulator-main-3v3 {
31		compatible = "regulator-fixed";
32		regulator-name = "3V3";
33		regulator-min-microvolt = <3300000>;
34		regulator-max-microvolt = <3300000>;
35	};
36
37	reg_main_usb: regulator-main-usb {
38		compatible = "regulator-fixed";
39		regulator-name = "USB_PWR";
40		regulator-min-microvolt = <5000000>;
41		regulator-max-microvolt = <5000000>;
42		vin-supply = <&reg_main_5v>;
43	};
44
45	sound {
46		compatible = "fsl,imx-audio-wm8960";
47		audio-cpu = <&sai2>;
48		audio-codec = <&wm8960>;
49		audio-routing =
50			"Headphone Jack", "HP_L",
51			"Headphone Jack", "HP_R",
52			"Ext Spk", "SPK_LP",
53			"Ext Spk", "SPK_LN",
54			"Ext Spk", "SPK_RP",
55			"Ext Spk", "SPK_RN",
56			"LINPUT1", "Mic Jack",
57			"Mic Jack", "MICB",
58			"LINPUT2", "Line In Jack",
59			"RINPUT2", "Line In Jack";
60		model = "wm8960-audio";
61	};
62};
63
64&fec1 {
65	status = "okay";
66};
67
68&i2c3 {
69	pinctrl-names = "default";
70	pinctrl-0 = <&pinctrl_i2c3>;
71	status = "okay";
72
73	wm8960: codec@1a {
74		compatible = "wlf,wm8960";
75		reg = <0x1a>;
76		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
77		clock-names = "mclk";
78		#sound-dai-cells = <0>;
79	};
80
81	rtc@68 {
82		compatible = "nxp,pcf8523";
83		reg = <0x68>;
84	};
85};
86
87&pcie1 {
88	pinctrl-names = "default";
89	pinctrl-0 = <&pinctrl_pcie1>;
90	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
91	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
92		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
93		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
94		 <&pcie1_refclk>;
95	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
96	status = "okay";
97};
98
99&reg_1p8v {
100	vin-supply = <&reg_main_5v>;
101};
102
103&reg_snvs {
104	vin-supply = <&reg_main_5v>;
105};
106
107&reg_arm_dram {
108	vin-supply = <&reg_main_5v>;
109};
110
111&reg_dram_1p1v {
112	vin-supply = <&reg_main_5v>;
113};
114
115&reg_soc_gpu_vpu {
116	vin-supply = <&reg_main_5v>;
117};
118
119&sai2 {
120	pinctrl-names = "default";
121	pinctrl-0 = <&pinctrl_sai2>;
122	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
123	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
124	assigned-clock-rates = <25000000>;
125	fsl,sai-mclk-direction-output;
126	fsl,sai-asynchronous;
127	status = "okay";
128};
129
130&snvs_rtc {
131	status = "disabled";
132};
133
134&uart2 {
135	pinctrl-names = "default";
136	pinctrl-0 = <&pinctrl_uart2>;
137	status = "okay";
138};
139
140&usb3_phy0 {
141	vbus-supply = <&reg_main_usb>;
142	status = "okay";
143};
144
145&usb3_phy1 {
146	vbus-supply = <&reg_main_usb>;
147	status = "okay";
148};
149
150&usb_dwc3_0 {
151	dr_mode = "host";
152	status = "okay";
153};
154
155&usb_dwc3_1 {
156	dr_mode = "host";
157	status = "okay";
158};
159
160&usdhc2 {
161	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
162	assigned-clock-rates = <200000000>;
163	pinctrl-names = "default";
164	pinctrl-0 = <&pinctrl_usdhc2>;
165	vqmmc-supply = <&reg_main_3v3>;
166	vmmc-supply = <&reg_main_3v3>;
167	bus-width = <4>;
168	status = "okay";
169};
170
171&iomuxc {
172	pinctrl_i2c3: i2c3grp {
173		fsl,pins = <
174			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
175			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
176		>;
177	};
178
179	pinctrl_pcie1: pcie1grp {
180		fsl,pins = <
181			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16
182		>;
183	};
184
185	pinctrl_sai2: sai2grp {
186		fsl,pins = <
187			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6
188			MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC		0xd6
189			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6
190			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6
191			MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK		0xd6
192			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6
193			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6
194		>;
195	};
196
197	pinctrl_uart2: uart2grp {
198		fsl,pins = <
199			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45
200			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x45
201		>;
202	};
203
204	pinctrl_usdhc2: usdhc2grp {
205		fsl,pins = <
206			MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0
207			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
208			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
209			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
210			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
211			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
212			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
213		>;
214	};
215};
216