1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+
2eb4ea085SAngus Ainslie (Purism)/*
3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC
4eb4ea085SAngus Ainslie (Purism) */
5eb4ea085SAngus Ainslie (Purism)
6eb4ea085SAngus Ainslie (Purism)/dts-v1/;
7eb4ea085SAngus Ainslie (Purism)
8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h"
9d8fa4792SKrzysztof Kozlowski#include <dt-bindings/interrupt-controller/irq.h>
10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h"
11eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h"
12eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi"
13eb4ea085SAngus Ainslie (Purism)
14eb4ea085SAngus Ainslie (Purism)/ {
15eb4ea085SAngus Ainslie (Purism)	model = "Purism Librem 5 devkit";
16eb4ea085SAngus Ainslie (Purism)	compatible = "purism,librem5-devkit", "fsl,imx8mq";
17eb4ea085SAngus Ainslie (Purism)
18eb4ea085SAngus Ainslie (Purism)	backlight_dsi: backlight-dsi {
19eb4ea085SAngus Ainslie (Purism)		compatible = "pwm-backlight";
20eb4ea085SAngus Ainslie (Purism)		/* 200 Hz for the PAM2841 */
21eb4ea085SAngus Ainslie (Purism)		pwms = <&pwm1 0 5000000>;
22eb4ea085SAngus Ainslie (Purism)		brightness-levels = <0 100>;
23eb4ea085SAngus Ainslie (Purism)		num-interpolated-steps = <100>;
24eb4ea085SAngus Ainslie (Purism)		/* Default brightness level (index into the array defined by */
25eb4ea085SAngus Ainslie (Purism)		/* the "brightness-levels" property) */
26eb4ea085SAngus Ainslie (Purism)		default-brightness-level = <0>;
27eb4ea085SAngus Ainslie (Purism)		power-supply = <&reg_22v4_p>;
28eb4ea085SAngus Ainslie (Purism)	};
29eb4ea085SAngus Ainslie (Purism)
30eb4ea085SAngus Ainslie (Purism)	chosen {
31eb4ea085SAngus Ainslie (Purism)		stdout-path = &uart1;
32eb4ea085SAngus Ainslie (Purism)	};
33eb4ea085SAngus Ainslie (Purism)
34eb4ea085SAngus Ainslie (Purism)	gpio-keys {
35eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-keys";
36eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
37eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_keys>;
38eb4ea085SAngus Ainslie (Purism)
39eb4ea085SAngus Ainslie (Purism)		btn1 {
40eb4ea085SAngus Ainslie (Purism)			label = "VOL_UP";
41eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
42eb4ea085SAngus Ainslie (Purism)			wakeup-source;
43eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEUP>;
44eb4ea085SAngus Ainslie (Purism)		};
45eb4ea085SAngus Ainslie (Purism)
46eb4ea085SAngus Ainslie (Purism)		btn2 {
47eb4ea085SAngus Ainslie (Purism)			label = "VOL_DOWN";
48eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
49eb4ea085SAngus Ainslie (Purism)			wakeup-source;
50eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEDOWN>;
51eb4ea085SAngus Ainslie (Purism)		};
52eb4ea085SAngus Ainslie (Purism)
53eb4ea085SAngus Ainslie (Purism)		hp-det {
54eb4ea085SAngus Ainslie (Purism)			label = "HP_DET";
55eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
56eb4ea085SAngus Ainslie (Purism)			wakeup-source;
57eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_HP>;
58eb4ea085SAngus Ainslie (Purism)		};
593ef506b3SAngus Ainslie (Purism)
603ef506b3SAngus Ainslie (Purism)		wwan-wake {
613ef506b3SAngus Ainslie (Purism)			label = "WWAN_WAKE";
623ef506b3SAngus Ainslie (Purism)			gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
633ef506b3SAngus Ainslie (Purism)			interrupt-parent = <&gpio3>;
64d8fa4792SKrzysztof Kozlowski			interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
653ef506b3SAngus Ainslie (Purism)			wakeup-source;
663ef506b3SAngus Ainslie (Purism)			linux,code = <KEY_PHONE>;
673ef506b3SAngus Ainslie (Purism)		};
68eb4ea085SAngus Ainslie (Purism)	};
69eb4ea085SAngus Ainslie (Purism)
70eb4ea085SAngus Ainslie (Purism)	leds {
71eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-leds";
72eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
73eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_leds>;
74eb4ea085SAngus Ainslie (Purism)
75eb4ea085SAngus Ainslie (Purism)		led1 {
76eb4ea085SAngus Ainslie (Purism)			label = "LED 1";
77eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
78eb4ea085SAngus Ainslie (Purism)			default-state = "off";
79eb4ea085SAngus Ainslie (Purism)		};
80eb4ea085SAngus Ainslie (Purism)	};
81eb4ea085SAngus Ainslie (Purism)
82eb4ea085SAngus Ainslie (Purism)	pmic_osc: clock-pmic {
83eb4ea085SAngus Ainslie (Purism)		compatible = "fixed-clock";
84eb4ea085SAngus Ainslie (Purism)		#clock-cells = <0>;
85eb4ea085SAngus Ainslie (Purism)		clock-frequency = <32768>;
86eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_osc";
87eb4ea085SAngus Ainslie (Purism)	};
88eb4ea085SAngus Ainslie (Purism)
89eb4ea085SAngus Ainslie (Purism)	reg_1v8_p: regulator-1v8-p {
90eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
91eb4ea085SAngus Ainslie (Purism)		regulator-name = "1v8_p";
92eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <1800000>;
93eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <1800000>;
94eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
95eb4ea085SAngus Ainslie (Purism)	};
96eb4ea085SAngus Ainslie (Purism)
97eb4ea085SAngus Ainslie (Purism)	reg_2v8_p: regulator-2v8-p {
98eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
99eb4ea085SAngus Ainslie (Purism)		regulator-name = "2v8_p";
100eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <2800000>;
101eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <2800000>;
102eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
103eb4ea085SAngus Ainslie (Purism)	};
104eb4ea085SAngus Ainslie (Purism)
105eb4ea085SAngus Ainslie (Purism)	reg_3v3_p: regulator-3v3-p {
106eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
107eb4ea085SAngus Ainslie (Purism)		regulator-name = "3v3_p";
108eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
109eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
110eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
111eb4ea085SAngus Ainslie (Purism)
112eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
113eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
114eb4ea085SAngus Ainslie (Purism)		};
115eb4ea085SAngus Ainslie (Purism)	};
116eb4ea085SAngus Ainslie (Purism)
117eb4ea085SAngus Ainslie (Purism)	reg_5v_p: regulator-5v-p {
118eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
119eb4ea085SAngus Ainslie (Purism)		regulator-name = "5v_p";
120eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <5000000>;
121eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <5000000>;
122eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
123eb4ea085SAngus Ainslie (Purism)
124eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
125eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
126eb4ea085SAngus Ainslie (Purism)		};
127eb4ea085SAngus Ainslie (Purism)	};
128eb4ea085SAngus Ainslie (Purism)
129eb4ea085SAngus Ainslie (Purism)	reg_22v4_p: regulator-22v4-p  {
130eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
131eb4ea085SAngus Ainslie (Purism)		regulator-name = "22v4_P";
132eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <22400000>;
133eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <22400000>;
134eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
135eb4ea085SAngus Ainslie (Purism)	};
136eb4ea085SAngus Ainslie (Purism)
137eb4ea085SAngus Ainslie (Purism)	reg_pwr_en: regulator-pwr-en {
138eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
139eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
140eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pwr_en>;
141eb4ea085SAngus Ainslie (Purism)		regulator-name = "PWR_EN";
142eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
143eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
144eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
145eb4ea085SAngus Ainslie (Purism)		enable-active-high;
146eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
147eb4ea085SAngus Ainslie (Purism)	};
148eb4ea085SAngus Ainslie (Purism)
149eb4ea085SAngus Ainslie (Purism)	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
150eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
151eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
152eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_usdhc2_pwr>;
153eb4ea085SAngus Ainslie (Purism)		regulator-name = "VSD_3V3";
154eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
155eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
156eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
157eb4ea085SAngus Ainslie (Purism)		enable-active-high;
158eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
159eb4ea085SAngus Ainslie (Purism)	};
160eb4ea085SAngus Ainslie (Purism)
1617f7b7997SAngus Ainslie (Purism)	wwan_codec: sound-wwan-codec {
1627f7b7997SAngus Ainslie (Purism)		compatible = "option,gtm601";
1637f7b7997SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
1647f7b7997SAngus Ainslie (Purism)	};
1657f7b7997SAngus Ainslie (Purism)
166c53f0166SAngus Ainslie (Purism)	sound {
167c53f0166SAngus Ainslie (Purism)		compatible = "simple-audio-card";
168c53f0166SAngus Ainslie (Purism)		simple-audio-card,name = "sgtl5000";
169c53f0166SAngus Ainslie (Purism)		simple-audio-card,format = "i2s";
170c53f0166SAngus Ainslie (Purism)		simple-audio-card,widgets =
171c53f0166SAngus Ainslie (Purism)			"Microphone", "Microphone Jack",
172c53f0166SAngus Ainslie (Purism)			"Headphone", "Headphone Jack",
173c53f0166SAngus Ainslie (Purism)			"Speaker", "Speaker Ext",
174c53f0166SAngus Ainslie (Purism)			"Line", "Line In Jack";
175c53f0166SAngus Ainslie (Purism)		simple-audio-card,routing =
176c53f0166SAngus Ainslie (Purism)			"MIC_IN", "Microphone Jack",
177c53f0166SAngus Ainslie (Purism)			"Microphone Jack", "Mic Bias",
178c53f0166SAngus Ainslie (Purism)			"LINE_IN", "Line In Jack",
179c53f0166SAngus Ainslie (Purism)			"Headphone Jack", "HP_OUT",
180c53f0166SAngus Ainslie (Purism)			"Speaker Ext", "LINE_OUT";
181c53f0166SAngus Ainslie (Purism)
182c53f0166SAngus Ainslie (Purism)		simple-audio-card,cpu {
183c53f0166SAngus Ainslie (Purism)			sound-dai = <&sai2>;
184c53f0166SAngus Ainslie (Purism)		};
185c53f0166SAngus Ainslie (Purism)
186c53f0166SAngus Ainslie (Purism)		simple-audio-card,codec {
187c53f0166SAngus Ainslie (Purism)			sound-dai = <&sgtl5000>;
188c53f0166SAngus Ainslie (Purism)			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
189c53f0166SAngus Ainslie (Purism)			frame-master;
190c53f0166SAngus Ainslie (Purism)			bitclock-master;
191c53f0166SAngus Ainslie (Purism)		};
192c53f0166SAngus Ainslie (Purism)	};
193c53f0166SAngus Ainslie (Purism)
1947f7b7997SAngus Ainslie (Purism)	sound-wwan {
1957f7b7997SAngus Ainslie (Purism)		compatible = "simple-audio-card";
1967f7b7997SAngus Ainslie (Purism)		simple-audio-card,name = "SIMCom SIM7100";
1977f7b7997SAngus Ainslie (Purism)		simple-audio-card,format = "dsp_a";
1987f7b7997SAngus Ainslie (Purism)
1997f7b7997SAngus Ainslie (Purism)		simple-audio-card,cpu {
2007f7b7997SAngus Ainslie (Purism)			sound-dai = <&sai6>;
2017f7b7997SAngus Ainslie (Purism)		};
2027f7b7997SAngus Ainslie (Purism)
2037f7b7997SAngus Ainslie (Purism)		telephony_link_master: simple-audio-card,codec {
2047f7b7997SAngus Ainslie (Purism)			sound-dai = <&wwan_codec>;
2057f7b7997SAngus Ainslie (Purism)			frame-master;
2067f7b7997SAngus Ainslie (Purism)			bitclock-master;
2077f7b7997SAngus Ainslie (Purism)		};
2087f7b7997SAngus Ainslie (Purism)	};
2097f7b7997SAngus Ainslie (Purism)
210eb4ea085SAngus Ainslie (Purism)	vibrator {
211eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-vibrator";
212eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
213eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_haptic>;
214eb4ea085SAngus Ainslie (Purism)	        enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
215eb4ea085SAngus Ainslie (Purism)		vcc-supply = <&reg_3v3_p>;
216eb4ea085SAngus Ainslie (Purism)	};
217eb4ea085SAngus Ainslie (Purism)
218eb4ea085SAngus Ainslie (Purism)	wifi_pwr_en: regulator-wifi-en {
219eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
220eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
221eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
222eb4ea085SAngus Ainslie (Purism)		regulator-name = "WIFI_EN";
223eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
224eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
225eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
226eb4ea085SAngus Ainslie (Purism)		enable-active-high;
227eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
228eb4ea085SAngus Ainslie (Purism)	};
229eb4ea085SAngus Ainslie (Purism)};
230eb4ea085SAngus Ainslie (Purism)
231a2e47ba2SAngus Ainslie (Purism)&A53_0 {
232a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
233a2e47ba2SAngus Ainslie (Purism)};
234a2e47ba2SAngus Ainslie (Purism)
235a2e47ba2SAngus Ainslie (Purism)&A53_1 {
236a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
237a2e47ba2SAngus Ainslie (Purism)};
238a2e47ba2SAngus Ainslie (Purism)
239a2e47ba2SAngus Ainslie (Purism)&A53_2 {
240a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
241a2e47ba2SAngus Ainslie (Purism)};
242a2e47ba2SAngus Ainslie (Purism)
243a2e47ba2SAngus Ainslie (Purism)&A53_3 {
244a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
245a2e47ba2SAngus Ainslie (Purism)};
246a2e47ba2SAngus Ainslie (Purism)
247eb4ea085SAngus Ainslie (Purism)&clk {
248eb4ea085SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
249eb4ea085SAngus Ainslie (Purism)	assigned-clock-rates = <786432000>, <722534400>;
250eb4ea085SAngus Ainslie (Purism)};
251eb4ea085SAngus Ainslie (Purism)
2529d9005a5SGuido Günther&dphy {
2539d9005a5SGuido Günther	status = "okay";
2549d9005a5SGuido Günther};
2559d9005a5SGuido Günther
256eb4ea085SAngus Ainslie (Purism)&fec1 {
257eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
258eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_fec1>;
259eb4ea085SAngus Ainslie (Purism)	phy-mode = "rgmii-id";
260eb4ea085SAngus Ainslie (Purism)	phy-handle = <&ethphy0>;
261eb4ea085SAngus Ainslie (Purism)	fsl,magic-packet;
262eb4ea085SAngus Ainslie (Purism)	phy-supply = <&reg_3v3_p>;
263eb4ea085SAngus Ainslie (Purism)	status = "okay";
264eb4ea085SAngus Ainslie (Purism)
265eb4ea085SAngus Ainslie (Purism)	mdio {
266eb4ea085SAngus Ainslie (Purism)		#address-cells = <1>;
267eb4ea085SAngus Ainslie (Purism)		#size-cells = <0>;
268eb4ea085SAngus Ainslie (Purism)
269eb4ea085SAngus Ainslie (Purism)		ethphy0: ethernet-phy@1 {
270eb4ea085SAngus Ainslie (Purism)			compatible = "ethernet-phy-ieee802.3-c22";
271eb4ea085SAngus Ainslie (Purism)			reg = <1>;
272eb4ea085SAngus Ainslie (Purism)		};
273eb4ea085SAngus Ainslie (Purism)	};
274eb4ea085SAngus Ainslie (Purism)};
275eb4ea085SAngus Ainslie (Purism)
276eb4ea085SAngus Ainslie (Purism)&i2c1 {
277eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
278eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
279eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c1>;
280eb4ea085SAngus Ainslie (Purism)	status = "okay";
281eb4ea085SAngus Ainslie (Purism)
282eb4ea085SAngus Ainslie (Purism)	pmic: pmic@4b {
283eb4ea085SAngus Ainslie (Purism)		compatible = "rohm,bd71837";
284eb4ea085SAngus Ainslie (Purism)		reg = <0x4b>;
285eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
286eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pmic>;
287eb4ea085SAngus Ainslie (Purism)		clocks = <&pmic_osc>;
288eb4ea085SAngus Ainslie (Purism)		clock-names = "osc";
289a4a3550eSKrzysztof Kozlowski		#clock-cells = <0>;
290eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_clk";
291eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio1>;
292d8fa4792SKrzysztof Kozlowski		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
293eb4ea085SAngus Ainslie (Purism)		rohm,reset-snvs-powered;
294eb4ea085SAngus Ainslie (Purism)
295eb4ea085SAngus Ainslie (Purism)		regulators {
296eb4ea085SAngus Ainslie (Purism)			buck1_reg: BUCK1 {
297eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck1";
298eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
299eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
300eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
301edb93de4SGuido Günther				regulator-always-on;
302eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
303eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <900000>;
304eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <850000>;
305eb4ea085SAngus Ainslie (Purism)				rohm,dvs-suspend-voltage = <800000>;
306eb4ea085SAngus Ainslie (Purism)			};
307eb4ea085SAngus Ainslie (Purism)
308eb4ea085SAngus Ainslie (Purism)			buck2_reg: BUCK2 {
309eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck2";
310eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
311eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
312eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
313eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
314eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
315eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <900000>;
316eb4ea085SAngus Ainslie (Purism)			};
317eb4ea085SAngus Ainslie (Purism)
318eb4ea085SAngus Ainslie (Purism)			buck3_reg: BUCK3 {
319eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck3";
320eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
321eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
322eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
323edb93de4SGuido Günther				regulator-enable-ramp-delay = <200>;
32476eceb0fSGuido Günther				rohm,dvs-run-voltage = <900000>;
325eb4ea085SAngus Ainslie (Purism)			};
326eb4ea085SAngus Ainslie (Purism)
327eb4ea085SAngus Ainslie (Purism)			buck4_reg: BUCK4 {
328eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck4";
329eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
330eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
331eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
332eb4ea085SAngus Ainslie (Purism)			};
333eb4ea085SAngus Ainslie (Purism)
334eb4ea085SAngus Ainslie (Purism)			buck5_reg: BUCK5 {
335eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck5";
336eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
337eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1350000>;
338eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
339edb93de4SGuido Günther				regulator-always-on;
340eb4ea085SAngus Ainslie (Purism)			};
341eb4ea085SAngus Ainslie (Purism)
342eb4ea085SAngus Ainslie (Purism)			buck6_reg: BUCK6 {
343eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck6";
344eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
345eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
346eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
347edb93de4SGuido Günther				regulator-always-on;
348eb4ea085SAngus Ainslie (Purism)			};
349eb4ea085SAngus Ainslie (Purism)
350eb4ea085SAngus Ainslie (Purism)			buck7_reg: BUCK7 {
351eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck7";
352eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1605000>;
353eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1995000>;
354eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
355edb93de4SGuido Günther				regulator-always-on;
356eb4ea085SAngus Ainslie (Purism)			};
357eb4ea085SAngus Ainslie (Purism)
358eb4ea085SAngus Ainslie (Purism)			buck8_reg: BUCK8 {
359eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck8";
360eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <800000>;
361eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1400000>;
362eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
363edb93de4SGuido Günther				regulator-always-on;
364eb4ea085SAngus Ainslie (Purism)			};
365eb4ea085SAngus Ainslie (Purism)
366eb4ea085SAngus Ainslie (Purism)			ldo1_reg: LDO1 {
367eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo1";
368eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
369eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
370eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
371eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
372eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
373eb4ea085SAngus Ainslie (Purism)			};
374eb4ea085SAngus Ainslie (Purism)
375eb4ea085SAngus Ainslie (Purism)			ldo2_reg: LDO2 {
376eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo2";
377eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
378eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <900000>;
379eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
380eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
381eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
382eb4ea085SAngus Ainslie (Purism)			};
383eb4ea085SAngus Ainslie (Purism)
384eb4ea085SAngus Ainslie (Purism)			ldo3_reg: LDO3 {
385eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo3";
386eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
387eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
388eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
389edb93de4SGuido Günther				regulator-always-on;
390eb4ea085SAngus Ainslie (Purism)			};
391eb4ea085SAngus Ainslie (Purism)
392eb4ea085SAngus Ainslie (Purism)			ldo4_reg: LDO4 {
393eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo4";
394eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
395eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
396eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
397edb93de4SGuido Günther				regulator-always-on;
398eb4ea085SAngus Ainslie (Purism)			};
399eb4ea085SAngus Ainslie (Purism)
400eb4ea085SAngus Ainslie (Purism)			ldo5_reg: LDO5 {
401eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo5";
402eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
403eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
404edb93de4SGuido Günther				regulator-always-on;
405eb4ea085SAngus Ainslie (Purism)			};
406eb4ea085SAngus Ainslie (Purism)
407eb4ea085SAngus Ainslie (Purism)			ldo6_reg: LDO6 {
408eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo6";
409eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
410eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
411eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
412edb93de4SGuido Günther				regulator-always-on;
413eb4ea085SAngus Ainslie (Purism)			};
414eb4ea085SAngus Ainslie (Purism)
415eb4ea085SAngus Ainslie (Purism)			ldo7_reg: LDO7 {
416eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo7";
417eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
418eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
419eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
420edb93de4SGuido Günther				regulator-always-on;
421eb4ea085SAngus Ainslie (Purism)			};
422eb4ea085SAngus Ainslie (Purism)		};
423eb4ea085SAngus Ainslie (Purism)	};
424eb4ea085SAngus Ainslie (Purism)
4259251dad3SGuido Günther	typec_ptn5100: usb-typec@52 {
426eb4ea085SAngus Ainslie (Purism)		compatible = "nxp,ptn5110";
427eb4ea085SAngus Ainslie (Purism)		reg = <0x52>;
428eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
429eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_typec>;
430eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
431eb4ea085SAngus Ainslie (Purism)		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
432eb4ea085SAngus Ainslie (Purism)
433eb4ea085SAngus Ainslie (Purism)		connector {
434eb4ea085SAngus Ainslie (Purism)			compatible = "usb-c-connector";
435eb4ea085SAngus Ainslie (Purism)			label = "USB-C";
436eb4ea085SAngus Ainslie (Purism)			data-role = "dual";
437eb4ea085SAngus Ainslie (Purism)			power-role = "dual";
438eb4ea085SAngus Ainslie (Purism)			try-power-role = "sink";
439eb4ea085SAngus Ainslie (Purism)			source-pdos = <PDO_FIXED(5000, 2000,
440eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_USB_COMM |
441eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
442eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )>;
4435369d191SAngus Ainslie (Purism)			sink-pdos = <PDO_FIXED(5000, 3500, PDO_FIXED_USB_COMM |
444eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
445eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )
4465369d191SAngus Ainslie (Purism)			     PDO_VAR(5000, 5000, 3500)>;
447eb4ea085SAngus Ainslie (Purism)			op-sink-microwatt = <10000000>;
448eb4ea085SAngus Ainslie (Purism)
449eb4ea085SAngus Ainslie (Purism)			ports {
450eb4ea085SAngus Ainslie (Purism)				#address-cells = <1>;
451eb4ea085SAngus Ainslie (Purism)				#size-cells = <0>;
452eb4ea085SAngus Ainslie (Purism)
453eb4ea085SAngus Ainslie (Purism)				port@0 {
454eb4ea085SAngus Ainslie (Purism)					reg = <0>;
455eb4ea085SAngus Ainslie (Purism)
456eb4ea085SAngus Ainslie (Purism)					usb_con_hs: endpoint {
457eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_hs>;
458eb4ea085SAngus Ainslie (Purism)					};
459eb4ea085SAngus Ainslie (Purism)				};
460eb4ea085SAngus Ainslie (Purism)
461eb4ea085SAngus Ainslie (Purism)				port@1 {
462eb4ea085SAngus Ainslie (Purism)					reg = <1>;
463eb4ea085SAngus Ainslie (Purism)
464eb4ea085SAngus Ainslie (Purism)					usb_con_ss: endpoint {
465eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_ss>;
466eb4ea085SAngus Ainslie (Purism)					};
467eb4ea085SAngus Ainslie (Purism)				};
468eb4ea085SAngus Ainslie (Purism)			};
469eb4ea085SAngus Ainslie (Purism)		};
470eb4ea085SAngus Ainslie (Purism)	};
471eb4ea085SAngus Ainslie (Purism)
472eb4ea085SAngus Ainslie (Purism)	rtc@68 {
473eb4ea085SAngus Ainslie (Purism)		compatible = "microcrystal,rv4162";
474eb4ea085SAngus Ainslie (Purism)		reg = <0x68>;
475eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
476eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_rtc>;
477eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio4>;
478eb4ea085SAngus Ainslie (Purism)		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
479eb4ea085SAngus Ainslie (Purism)	};
480eb4ea085SAngus Ainslie (Purism)
481eb4ea085SAngus Ainslie (Purism)	charger@6b { /* bq25896 */
482eb4ea085SAngus Ainslie (Purism)		compatible = "ti,bq25890";
483eb4ea085SAngus Ainslie (Purism)		reg = <0x6b>;
484eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
485eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_charger>;
486eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
487eb4ea085SAngus Ainslie (Purism)		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
488eb4ea085SAngus Ainslie (Purism)		ti,battery-regulation-voltage = <4192000>; /* 4.192V */
489eb4ea085SAngus Ainslie (Purism)		ti,charge-current = <1600000>; /* 1.6A */
490eb4ea085SAngus Ainslie (Purism)		ti,termination-current = <66000>;  /* 66mA */
491eb4ea085SAngus Ainslie (Purism)		ti,precharge-current = <130000>; /* 130mA */
492eb4ea085SAngus Ainslie (Purism)		ti,minimum-sys-voltage = <3000000>; /* 3V */
493eb4ea085SAngus Ainslie (Purism)		ti,boost-voltage = <5000000>; /* 5V */
494eb4ea085SAngus Ainslie (Purism)		ti,boost-max-current = <50000>; /* 50mA */
495eb4ea085SAngus Ainslie (Purism)	};
496eb4ea085SAngus Ainslie (Purism)};
497eb4ea085SAngus Ainslie (Purism)
498eb4ea085SAngus Ainslie (Purism)&i2c3 {
499eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
500eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
501eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c3>;
502eb4ea085SAngus Ainslie (Purism)	status = "okay";
503eb4ea085SAngus Ainslie (Purism)
504eb4ea085SAngus Ainslie (Purism)	magnetometer@1e	{
505eb4ea085SAngus Ainslie (Purism)		compatible = "st,lsm9ds1-magn";
506eb4ea085SAngus Ainslie (Purism)		reg = <0x1e>;
507eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
508eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_imu>;
509eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
510106f7b3bSAngus Ainslie (Purism)		interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
511eb4ea085SAngus Ainslie (Purism)		vdd-supply = <&reg_3v3_p>;
512eb4ea085SAngus Ainslie (Purism)		vddio-supply = <&reg_3v3_p>;
513eb4ea085SAngus Ainslie (Purism)	};
514eb4ea085SAngus Ainslie (Purism)
515c53f0166SAngus Ainslie (Purism)	sgtl5000: audio-codec@a {
516c53f0166SAngus Ainslie (Purism)		compatible = "fsl,sgtl5000";
517c53f0166SAngus Ainslie (Purism)		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
518c53f0166SAngus Ainslie (Purism)		assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
519c53f0166SAngus Ainslie (Purism)		assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
520c53f0166SAngus Ainslie (Purism)		assigned-clock-rates = <24576000>;
521c53f0166SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
522c53f0166SAngus Ainslie (Purism)		reg = <0x0a>;
523c53f0166SAngus Ainslie (Purism)		VDDD-supply = <&reg_1v8_p>;
524c53f0166SAngus Ainslie (Purism)		VDDIO-supply = <&reg_3v3_p>;
525c53f0166SAngus Ainslie (Purism)		VDDA-supply = <&reg_3v3_p>;
526c53f0166SAngus Ainslie (Purism)	};
527c53f0166SAngus Ainslie (Purism)
528eb4ea085SAngus Ainslie (Purism)	touchscreen@5d {
529eb4ea085SAngus Ainslie (Purism)		compatible = "goodix,gt5688";
530eb4ea085SAngus Ainslie (Purism)		reg = <0x5d>;
531eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
532eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_ts>;
533eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
534eb4ea085SAngus Ainslie (Purism)		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
535eb4ea085SAngus Ainslie (Purism)		reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
536eb4ea085SAngus Ainslie (Purism)		irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
537eb4ea085SAngus Ainslie (Purism)		touchscreen-size-x = <720>;
538eb4ea085SAngus Ainslie (Purism)		touchscreen-size-y = <1440>;
539eb4ea085SAngus Ainslie (Purism)		AVDD28-supply = <&reg_2v8_p>;
540eb4ea085SAngus Ainslie (Purism)		VDDIO-supply = <&reg_1v8_p>;
541eb4ea085SAngus Ainslie (Purism)	};
542537c00e3SMartin Kepplinger
543ea38ca9aSGuido Günther	proximity-sensor@60 {
544ea38ca9aSGuido Günther		compatible = "vishay,vcnl4040";
545ea38ca9aSGuido Günther		reg = <0x60>;
546ea38ca9aSGuido Günther		pinctrl-0 = <&pinctrl_prox>;
547ea38ca9aSGuido Günther	};
548ea38ca9aSGuido Günther
549537c00e3SMartin Kepplinger	accel-gyro@6a {
550537c00e3SMartin Kepplinger		compatible = "st,lsm9ds1-imu";
551537c00e3SMartin Kepplinger		reg = <0x6a>;
552537c00e3SMartin Kepplinger		vdd-supply = <&reg_3v3_p>;
553537c00e3SMartin Kepplinger		vddio-supply = <&reg_3v3_p>;
554eef22bb1SMartin Kepplinger		mount-matrix =  "1",  "0",  "0",
555eef22bb1SMartin Kepplinger				"0",  "1",  "0",
556eef22bb1SMartin Kepplinger				"0",  "0", "-1";
557537c00e3SMartin Kepplinger	};
558eb4ea085SAngus Ainslie (Purism)};
559eb4ea085SAngus Ainslie (Purism)
560eb4ea085SAngus Ainslie (Purism)&iomuxc {
561eb4ea085SAngus Ainslie (Purism)	pinctrl_bl: blgrp {
562eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
563eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT	0x6 /* DSI_BL_PWM */
564eb4ea085SAngus Ainslie (Purism)		>;
565eb4ea085SAngus Ainslie (Purism)	};
566eb4ea085SAngus Ainslie (Purism)
567eb4ea085SAngus Ainslie (Purism)	pinctrl_bt: btgrp {
568eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
569eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11	0x16 /* nBT_DISABLE */
570eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7	0x10 /* BT_HOST_WAKE */
571eb4ea085SAngus Ainslie (Purism)		>;
572eb4ea085SAngus Ainslie (Purism)	};
573eb4ea085SAngus Ainslie (Purism)
574eb4ea085SAngus Ainslie (Purism)	pinctrl_charger: chargergrp {
575eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
576eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x80 /* CHRG_nINT */
577eb4ea085SAngus Ainslie (Purism)		>;
578eb4ea085SAngus Ainslie (Purism)	};
579eb4ea085SAngus Ainslie (Purism)
580eb4ea085SAngus Ainslie (Purism)	pinctrl_fec1: fec1grp {
581eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
582eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
583eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
584eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
585eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
586eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
587eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
588eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
589eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
590eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
591eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
592eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
593eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
594eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
595eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
596eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
597eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x1f
598eb4ea085SAngus Ainslie (Purism)		>;
599eb4ea085SAngus Ainslie (Purism)	};
600eb4ea085SAngus Ainslie (Purism)
601eb4ea085SAngus Ainslie (Purism)	pinctrl_ts: tsgrp {
602eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
603eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0		0x16  /* TOUCH INT */
604eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19  /* TOUCH RST */
605eb4ea085SAngus Ainslie (Purism)		>;
606eb4ea085SAngus Ainslie (Purism)	};
607eb4ea085SAngus Ainslie (Purism)
608eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_leds: gpioledgrp {
609eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
610eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16
611eb4ea085SAngus Ainslie (Purism)		>;
612eb4ea085SAngus Ainslie (Purism)	};
613eb4ea085SAngus Ainslie (Purism)
614eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_keys: gpiokeygrp {
615eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
616eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x16
617eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22	0x16
618eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x180  /* HP_DET */
6193ef506b3SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80   /* nWoWWAN */
620eb4ea085SAngus Ainslie (Purism)		>;
621eb4ea085SAngus Ainslie (Purism)	};
622eb4ea085SAngus Ainslie (Purism)
623eb4ea085SAngus Ainslie (Purism)	pinctrl_haptic: hapticgrp {
624eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
625eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4		0xc6   /* nHAPTIC */
626eb4ea085SAngus Ainslie (Purism)		>;
627eb4ea085SAngus Ainslie (Purism)	};
628eb4ea085SAngus Ainslie (Purism)
629eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c1: i2c1grp {
630eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
631eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000001f
632eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000001f
633eb4ea085SAngus Ainslie (Purism)		>;
634eb4ea085SAngus Ainslie (Purism)	};
635eb4ea085SAngus Ainslie (Purism)
636eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c3: i2c3grp {
637eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
638eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x4000001f
639eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x4000001f
640eb4ea085SAngus Ainslie (Purism)		>;
641eb4ea085SAngus Ainslie (Purism)	};
642eb4ea085SAngus Ainslie (Purism)
643eb4ea085SAngus Ainslie (Purism)	pinctrl_imu: imugrp {
644eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
645eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x8  /* IMU_INT */
646eb4ea085SAngus Ainslie (Purism)		>;
647eb4ea085SAngus Ainslie (Purism)	};
648eb4ea085SAngus Ainslie (Purism)
649eb4ea085SAngus Ainslie (Purism)	pinctrl_pmic: pmicgrp {
650eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
651eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x80  /* PMIC intr */
652eb4ea085SAngus Ainslie (Purism)		>;
653eb4ea085SAngus Ainslie (Purism)	};
654eb4ea085SAngus Ainslie (Purism)
655ea38ca9aSGuido Günther	pinctrl_prox: proxgrp {
656ea38ca9aSGuido Günther		fsl,pins = <
657ea38ca9aSGuido Günther			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x80  /* prox intr */
658ea38ca9aSGuido Günther		>;
659ea38ca9aSGuido Günther	};
660ea38ca9aSGuido Günther
661eb4ea085SAngus Ainslie (Purism)	pinctrl_pwr_en: pwrengrp {
662eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
663eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x06
664eb4ea085SAngus Ainslie (Purism)		>;
665eb4ea085SAngus Ainslie (Purism)	};
666eb4ea085SAngus Ainslie (Purism)
667eb4ea085SAngus Ainslie (Purism)	pinctrl_rtc: rtcgrp {
668eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
669eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29	0x80  /* RTC intr */
670eb4ea085SAngus Ainslie (Purism)		>;
671eb4ea085SAngus Ainslie (Purism)	};
672eb4ea085SAngus Ainslie (Purism)
673c53f0166SAngus Ainslie (Purism)	pinctrl_sai2: sai2grp {
674c53f0166SAngus Ainslie (Purism)		fsl,pins = <
675c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
676c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
677c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
678c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6
679c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
680c53f0166SAngus Ainslie (Purism)		>;
681c53f0166SAngus Ainslie (Purism)	};
682c53f0166SAngus Ainslie (Purism)
6837f7b7997SAngus Ainslie (Purism)	pinctrl_sai6: sai6grp {
6847f7b7997SAngus Ainslie (Purism)		fsl,pins = <
6857f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0	0xd6
6867f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC	0xd6
6877f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK     0xd6
6887f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0	0xd6
6897f7b7997SAngus Ainslie (Purism)		>;
6907f7b7997SAngus Ainslie (Purism)	};
6917f7b7997SAngus Ainslie (Purism)
692eb4ea085SAngus Ainslie (Purism)	pinctrl_typec: typecgrp {
693eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
694eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x16
695eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x80
696eb4ea085SAngus Ainslie (Purism)		>;
697eb4ea085SAngus Ainslie (Purism)	};
698eb4ea085SAngus Ainslie (Purism)
699eb4ea085SAngus Ainslie (Purism)	pinctrl_uart1: uart1grp {
700eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
701eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
702eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
703eb4ea085SAngus Ainslie (Purism)		>;
704eb4ea085SAngus Ainslie (Purism)	};
705eb4ea085SAngus Ainslie (Purism)
706eb4ea085SAngus Ainslie (Purism)	pinctrl_uart2: uart2grp {
707eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
708eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
709eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
710eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
711eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
712eb4ea085SAngus Ainslie (Purism)		>;
713eb4ea085SAngus Ainslie (Purism)	};
714eb4ea085SAngus Ainslie (Purism)
715eb4ea085SAngus Ainslie (Purism)	pinctrl_uart3: uart3grp {
716eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
717eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
718eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
719eb4ea085SAngus Ainslie (Purism)		>;
720eb4ea085SAngus Ainslie (Purism)	};
721eb4ea085SAngus Ainslie (Purism)
722eb4ea085SAngus Ainslie (Purism)	pinctrl_uart4: uart4grp {
723eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
724eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
725eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
726eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x49
727eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49
728eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x49
729eb4ea085SAngus Ainslie (Purism)		>;
730eb4ea085SAngus Ainslie (Purism)	};
731eb4ea085SAngus Ainslie (Purism)
732eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1: usdhc1grp {
733eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
734eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
735eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
736eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
737eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
738eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
739eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
740eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
741eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
742eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
743eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
744eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
745eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
746eb4ea085SAngus Ainslie (Purism)		>;
747eb4ea085SAngus Ainslie (Purism)	};
748eb4ea085SAngus Ainslie (Purism)
749ae560c43SKrzysztof Kozlowski	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
750eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
751eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
752eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
753eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
754eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
755eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
756eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
757eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
758eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
759eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
760eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
761eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
762eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
763eb4ea085SAngus Ainslie (Purism)		>;
764eb4ea085SAngus Ainslie (Purism)	};
765eb4ea085SAngus Ainslie (Purism)
766ae560c43SKrzysztof Kozlowski	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
767eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
768eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
769eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
770eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
771eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
772eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
773eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
774eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
775eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
776eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
777eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
778eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
779eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
780eb4ea085SAngus Ainslie (Purism)		>;
781eb4ea085SAngus Ainslie (Purism)	};
782eb4ea085SAngus Ainslie (Purism)
783ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_pwr: usdhc2pwrgrp {
784eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
785eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
786eb4ea085SAngus Ainslie (Purism)		>;
787eb4ea085SAngus Ainslie (Purism)	};
788eb4ea085SAngus Ainslie (Purism)
789ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
790eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
791eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */
792eb4ea085SAngus Ainslie (Purism)		>;
793eb4ea085SAngus Ainslie (Purism)	};
794eb4ea085SAngus Ainslie (Purism)
795eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2: usdhc2grp {
796eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
797eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
798eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
799eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
800eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
801eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
802eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
803eb4ea085SAngus Ainslie (Purism)		>;
804eb4ea085SAngus Ainslie (Purism)	};
805eb4ea085SAngus Ainslie (Purism)
806ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
807eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
808eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d
809eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd
810eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcd
811eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcd
812eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcd
813eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcd
814eb4ea085SAngus Ainslie (Purism)		>;
815eb4ea085SAngus Ainslie (Purism)	};
816eb4ea085SAngus Ainslie (Purism)
817ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
818eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
819eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f
820eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf
821eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcf
822eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcf
823eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcf
824eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcf
825eb4ea085SAngus Ainslie (Purism)		>;
826eb4ea085SAngus Ainslie (Purism)	};
827eb4ea085SAngus Ainslie (Purism)
828eb4ea085SAngus Ainslie (Purism)	pinctrl_wdog: wdoggrp {
829eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
830eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
831eb4ea085SAngus Ainslie (Purism)		>;
832eb4ea085SAngus Ainslie (Purism)	};
833eb4ea085SAngus Ainslie (Purism)
834eb4ea085SAngus Ainslie (Purism)	pinctrl_wifi_pwr_en: wifipwrengrp {
835eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
836eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5         0x06
837eb4ea085SAngus Ainslie (Purism)		>;
838eb4ea085SAngus Ainslie (Purism)	};
839eb4ea085SAngus Ainslie (Purism)
840eb4ea085SAngus Ainslie (Purism)	pinctrl_wwan: wwangrp {
841eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
842eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x09 /* nWWAN_DISABLE */
843eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80 /* nWoWWAN */
844eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9	0x19 /* WWAN_RESET */
845eb4ea085SAngus Ainslie (Purism)		>;
846eb4ea085SAngus Ainslie (Purism)	};
847eb4ea085SAngus Ainslie (Purism)};
848eb4ea085SAngus Ainslie (Purism)
849e8151ef3SGuido Günther&lcdif {
850e8151ef3SGuido Günther	status = "okay";
851e8151ef3SGuido Günther};
852e8151ef3SGuido Günther
853e8151ef3SGuido Günther&mipi_dsi {
854e8151ef3SGuido Günther	status = "okay";
855e8151ef3SGuido Günther	#address-cells = <1>;
856e8151ef3SGuido Günther	#size-cells = <0>;
857e8151ef3SGuido Günther
858e8151ef3SGuido Günther	panel@0 {
859e8151ef3SGuido Günther		compatible = "rocktech,jh057n00900";
860e8151ef3SGuido Günther		reg = <0>;
861e8151ef3SGuido Günther		backlight = <&backlight_dsi>;
862e8151ef3SGuido Günther		reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
863e8151ef3SGuido Günther		iovcc-supply = <&reg_1v8_p>;
864e8151ef3SGuido Günther		vcc-supply = <&reg_2v8_p>;
865e8151ef3SGuido Günther		port {
866e8151ef3SGuido Günther			panel_in: endpoint {
867e8151ef3SGuido Günther				remote-endpoint = <&mipi_dsi_out>;
868e8151ef3SGuido Günther			};
869e8151ef3SGuido Günther		};
870e8151ef3SGuido Günther	};
871e8151ef3SGuido Günther
872e8151ef3SGuido Günther	ports {
873e8151ef3SGuido Günther		port@1 {
874e8151ef3SGuido Günther			reg = <1>;
875e8151ef3SGuido Günther			mipi_dsi_out: endpoint {
876e8151ef3SGuido Günther				remote-endpoint = <&panel_in>;
877e8151ef3SGuido Günther			};
878e8151ef3SGuido Günther		};
879e8151ef3SGuido Günther	};
880e8151ef3SGuido Günther};
881e8151ef3SGuido Günther
882eb4ea085SAngus Ainslie (Purism)&pgc_gpu {
883eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck3_reg>;
884eb4ea085SAngus Ainslie (Purism)};
885eb4ea085SAngus Ainslie (Purism)
886eb4ea085SAngus Ainslie (Purism)&pgc_vpu {
887eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck4_reg>;
888eb4ea085SAngus Ainslie (Purism)};
889eb4ea085SAngus Ainslie (Purism)
890eb4ea085SAngus Ainslie (Purism)&pwm1 {
891eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
892eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_bl>;
893eb4ea085SAngus Ainslie (Purism)	status = "okay";
894eb4ea085SAngus Ainslie (Purism)};
895eb4ea085SAngus Ainslie (Purism)
89601407158SAngus Ainslie (Purism)&snvs_pwrkey {
89701407158SAngus Ainslie (Purism)	status = "okay";
89801407158SAngus Ainslie (Purism)};
899eb4ea085SAngus Ainslie (Purism)
900*ff38c1ddSGuido Günther&snvs_rtc {
901*ff38c1ddSGuido Günther	status = "disabled";
902*ff38c1ddSGuido Günther};
903*ff38c1ddSGuido Günther
904c53f0166SAngus Ainslie (Purism)&sai2 {
905c53f0166SAngus Ainslie (Purism)	pinctrl-names = "default";
906c53f0166SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai2>;
907c53f0166SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
908c53f0166SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
909c53f0166SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
910c53f0166SAngus Ainslie (Purism)	status = "okay";
911c53f0166SAngus Ainslie (Purism)};
912c53f0166SAngus Ainslie (Purism)
9137f7b7997SAngus Ainslie (Purism)&sai6 {
9147f7b7997SAngus Ainslie (Purism)	pinctrl-names = "default";
9157f7b7997SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai6>;
9167f7b7997SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI6>;
9177f7b7997SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
9187f7b7997SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
9197f7b7997SAngus Ainslie (Purism)	fsl,sai-synchronous-rx;
9207f7b7997SAngus Ainslie (Purism)	status = "okay";
9217f7b7997SAngus Ainslie (Purism)};
9227f7b7997SAngus Ainslie (Purism)
923eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */
924eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
925eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart1>;
926eb4ea085SAngus Ainslie (Purism)	status = "okay";
927eb4ea085SAngus Ainslie (Purism)};
928eb4ea085SAngus Ainslie (Purism)
929eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */
930eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
931eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart3>;
932eb4ea085SAngus Ainslie (Purism)	status = "okay";
933eb4ea085SAngus Ainslie (Purism)};
934eb4ea085SAngus Ainslie (Purism)
935eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */
936eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
937eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
938eb4ea085SAngus Ainslie (Purism)	uart-has-rtscts;
939eb4ea085SAngus Ainslie (Purism)	status = "okay";
940eb4ea085SAngus Ainslie (Purism)};
941eb4ea085SAngus Ainslie (Purism)
942eb4ea085SAngus Ainslie (Purism)&usb3_phy0 {
943dde061b8SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
944eb4ea085SAngus Ainslie (Purism)	status = "okay";
945eb4ea085SAngus Ainslie (Purism)};
946eb4ea085SAngus Ainslie (Purism)
947eb4ea085SAngus Ainslie (Purism)&usb3_phy1 {
948eb4ea085SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
949eb4ea085SAngus Ainslie (Purism)	status = "okay";
950eb4ea085SAngus Ainslie (Purism)};
951eb4ea085SAngus Ainslie (Purism)
952eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 {
953eb4ea085SAngus Ainslie (Purism)	#address-cells = <1>;
954eb4ea085SAngus Ainslie (Purism)	#size-cells = <0>;
955eb4ea085SAngus Ainslie (Purism)	dr_mode = "otg";
956eb4ea085SAngus Ainslie (Purism)	status = "okay";
957eb4ea085SAngus Ainslie (Purism)
958eb4ea085SAngus Ainslie (Purism)	port@0 {
959eb4ea085SAngus Ainslie (Purism)		reg = <0>;
960eb4ea085SAngus Ainslie (Purism)
961eb4ea085SAngus Ainslie (Purism)		typec_hs: endpoint {
962eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_hs>;
963eb4ea085SAngus Ainslie (Purism)		};
964eb4ea085SAngus Ainslie (Purism)	};
965eb4ea085SAngus Ainslie (Purism)
966eb4ea085SAngus Ainslie (Purism)	port@1 {
967eb4ea085SAngus Ainslie (Purism)		reg = <1>;
968eb4ea085SAngus Ainslie (Purism)
969eb4ea085SAngus Ainslie (Purism)		typec_ss: endpoint {
970eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_ss>;
971eb4ea085SAngus Ainslie (Purism)		};
972eb4ea085SAngus Ainslie (Purism)	};
973eb4ea085SAngus Ainslie (Purism)};
974eb4ea085SAngus Ainslie (Purism)
975eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 {
976eb4ea085SAngus Ainslie (Purism)	dr_mode = "host";
977eb4ea085SAngus Ainslie (Purism)	status = "okay";
978eb4ea085SAngus Ainslie (Purism)};
979eb4ea085SAngus Ainslie (Purism)
980eb4ea085SAngus Ainslie (Purism)&usdhc1 {
981e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
982e045f044SAnson Huang	assigned-clock-rates = <400000000>;
983eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
984eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc1>;
985eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
986eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
987eb4ea085SAngus Ainslie (Purism)	bus-width = <8>;
988eb4ea085SAngus Ainslie (Purism)	non-removable;
989eb4ea085SAngus Ainslie (Purism)	status = "okay";
990eb4ea085SAngus Ainslie (Purism)};
991eb4ea085SAngus Ainslie (Purism)
992eb4ea085SAngus Ainslie (Purism)&usdhc2 {
993e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
994e045f044SAnson Huang	assigned-clock-rates = <200000000>;
995eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
996eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc2>;
997eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
998eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
999eb4ea085SAngus Ainslie (Purism)	bus-width = <4>;
1000eb4ea085SAngus Ainslie (Purism)	vmmc-supply = <&reg_usdhc2_vmmc>;
1001eb4ea085SAngus Ainslie (Purism)	power-supply = <&wifi_pwr_en>;
10029dae8563SAngus Ainslie (Purism)	broken-cd;
1003eb4ea085SAngus Ainslie (Purism)	disable-wp;
1004eb4ea085SAngus Ainslie (Purism)	cap-sdio-irq;
1005eb4ea085SAngus Ainslie (Purism)	keep-power-in-suspend;
1006eb4ea085SAngus Ainslie (Purism)	wakeup-source;
1007eb4ea085SAngus Ainslie (Purism)	status = "okay";
1008eb4ea085SAngus Ainslie (Purism)};
1009eb4ea085SAngus Ainslie (Purism)
1010eb4ea085SAngus Ainslie (Purism)&wdog1 {
1011eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
1012eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_wdog>;
1013eb4ea085SAngus Ainslie (Purism)	fsl,ext-reset-output;
1014eb4ea085SAngus Ainslie (Purism)	status = "okay";
1015eb4ea085SAngus Ainslie (Purism)};
1016