1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+
2eb4ea085SAngus Ainslie (Purism)/*
3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC
4eb4ea085SAngus Ainslie (Purism) */
5eb4ea085SAngus Ainslie (Purism)
6eb4ea085SAngus Ainslie (Purism)/dts-v1/;
7eb4ea085SAngus Ainslie (Purism)
8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h"
9eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h"
10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h"
11eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi"
12eb4ea085SAngus Ainslie (Purism)
13eb4ea085SAngus Ainslie (Purism)/ {
14eb4ea085SAngus Ainslie (Purism)	model = "Purism Librem 5 devkit";
15eb4ea085SAngus Ainslie (Purism)	compatible = "purism,librem5-devkit", "fsl,imx8mq";
16eb4ea085SAngus Ainslie (Purism)
17eb4ea085SAngus Ainslie (Purism)	backlight_dsi: backlight-dsi {
18eb4ea085SAngus Ainslie (Purism)		compatible = "pwm-backlight";
19eb4ea085SAngus Ainslie (Purism)		/* 200 Hz for the PAM2841 */
20eb4ea085SAngus Ainslie (Purism)		pwms = <&pwm1 0 5000000>;
21eb4ea085SAngus Ainslie (Purism)		brightness-levels = <0 100>;
22eb4ea085SAngus Ainslie (Purism)		num-interpolated-steps = <100>;
23eb4ea085SAngus Ainslie (Purism)		/* Default brightness level (index into the array defined by */
24eb4ea085SAngus Ainslie (Purism)		/* the "brightness-levels" property) */
25eb4ea085SAngus Ainslie (Purism)		default-brightness-level = <0>;
26eb4ea085SAngus Ainslie (Purism)		power-supply = <&reg_22v4_p>;
27eb4ea085SAngus Ainslie (Purism)	};
28eb4ea085SAngus Ainslie (Purism)
29eb4ea085SAngus Ainslie (Purism)	chosen {
30eb4ea085SAngus Ainslie (Purism)		stdout-path = &uart1;
31eb4ea085SAngus Ainslie (Purism)	};
32eb4ea085SAngus Ainslie (Purism)
33eb4ea085SAngus Ainslie (Purism)	gpio-keys {
34eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-keys";
35eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
36eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_keys>;
37eb4ea085SAngus Ainslie (Purism)
38eb4ea085SAngus Ainslie (Purism)		btn1 {
39eb4ea085SAngus Ainslie (Purism)			label = "VOL_UP";
40eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
41eb4ea085SAngus Ainslie (Purism)			wakeup-source;
42eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEUP>;
43eb4ea085SAngus Ainslie (Purism)		};
44eb4ea085SAngus Ainslie (Purism)
45eb4ea085SAngus Ainslie (Purism)		btn2 {
46eb4ea085SAngus Ainslie (Purism)			label = "VOL_DOWN";
47eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
48eb4ea085SAngus Ainslie (Purism)			wakeup-source;
49eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEDOWN>;
50eb4ea085SAngus Ainslie (Purism)		};
51eb4ea085SAngus Ainslie (Purism)
52eb4ea085SAngus Ainslie (Purism)		hp-det {
53eb4ea085SAngus Ainslie (Purism)			label = "HP_DET";
54eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
55eb4ea085SAngus Ainslie (Purism)			wakeup-source;
56eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_HP>;
57eb4ea085SAngus Ainslie (Purism)		};
58eb4ea085SAngus Ainslie (Purism)	};
59eb4ea085SAngus Ainslie (Purism)
60eb4ea085SAngus Ainslie (Purism)	leds {
61eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-leds";
62eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
63eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_leds>;
64eb4ea085SAngus Ainslie (Purism)
65eb4ea085SAngus Ainslie (Purism)		led1 {
66eb4ea085SAngus Ainslie (Purism)			label = "LED 1";
67eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
68eb4ea085SAngus Ainslie (Purism)			default-state = "off";
69eb4ea085SAngus Ainslie (Purism)		};
70eb4ea085SAngus Ainslie (Purism)	};
71eb4ea085SAngus Ainslie (Purism)
72eb4ea085SAngus Ainslie (Purism)	pmic_osc: clock-pmic {
73eb4ea085SAngus Ainslie (Purism)		compatible = "fixed-clock";
74eb4ea085SAngus Ainslie (Purism)		#clock-cells = <0>;
75eb4ea085SAngus Ainslie (Purism)		clock-frequency = <32768>;
76eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_osc";
77eb4ea085SAngus Ainslie (Purism)	};
78eb4ea085SAngus Ainslie (Purism)
79eb4ea085SAngus Ainslie (Purism)	reg_1v8_p: regulator-1v8-p {
80eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
81eb4ea085SAngus Ainslie (Purism)		regulator-name = "1v8_p";
82eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <1800000>;
83eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <1800000>;
84eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
85eb4ea085SAngus Ainslie (Purism)	};
86eb4ea085SAngus Ainslie (Purism)
87eb4ea085SAngus Ainslie (Purism)	reg_2v8_p: regulator-2v8-p {
88eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
89eb4ea085SAngus Ainslie (Purism)		regulator-name = "2v8_p";
90eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <2800000>;
91eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <2800000>;
92eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
93eb4ea085SAngus Ainslie (Purism)	};
94eb4ea085SAngus Ainslie (Purism)
95eb4ea085SAngus Ainslie (Purism)	reg_3v3_p: regulator-3v3-p {
96eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
97eb4ea085SAngus Ainslie (Purism)		regulator-name = "3v3_p";
98eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
99eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
100eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
101eb4ea085SAngus Ainslie (Purism)
102eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
103eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
104eb4ea085SAngus Ainslie (Purism)		};
105eb4ea085SAngus Ainslie (Purism)	};
106eb4ea085SAngus Ainslie (Purism)
107eb4ea085SAngus Ainslie (Purism)	reg_5v_p: regulator-5v-p {
108eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
109eb4ea085SAngus Ainslie (Purism)		regulator-name = "5v_p";
110eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <5000000>;
111eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <5000000>;
112eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
113eb4ea085SAngus Ainslie (Purism)
114eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
115eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
116eb4ea085SAngus Ainslie (Purism)		};
117eb4ea085SAngus Ainslie (Purism)	};
118eb4ea085SAngus Ainslie (Purism)
119eb4ea085SAngus Ainslie (Purism)	reg_22v4_p: regulator-22v4-p  {
120eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
121eb4ea085SAngus Ainslie (Purism)		regulator-name = "22v4_P";
122eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <22400000>;
123eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <22400000>;
124eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
125eb4ea085SAngus Ainslie (Purism)	};
126eb4ea085SAngus Ainslie (Purism)
127eb4ea085SAngus Ainslie (Purism)	reg_pwr_en: regulator-pwr-en {
128eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
129eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
130eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pwr_en>;
131eb4ea085SAngus Ainslie (Purism)		regulator-name = "PWR_EN";
132eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
133eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
134eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
135eb4ea085SAngus Ainslie (Purism)		enable-active-high;
136eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
137eb4ea085SAngus Ainslie (Purism)	};
138eb4ea085SAngus Ainslie (Purism)
139eb4ea085SAngus Ainslie (Purism)	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
140eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
141eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
142eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_usdhc2_pwr>;
143eb4ea085SAngus Ainslie (Purism)		regulator-name = "VSD_3V3";
144eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
145eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
146eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
147eb4ea085SAngus Ainslie (Purism)		enable-active-high;
148eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
149eb4ea085SAngus Ainslie (Purism)	};
150eb4ea085SAngus Ainslie (Purism)
151eb4ea085SAngus Ainslie (Purism)	vibrator {
152eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-vibrator";
153eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
154eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_haptic>;
155eb4ea085SAngus Ainslie (Purism)	        enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
156eb4ea085SAngus Ainslie (Purism)		vcc-supply = <&reg_3v3_p>;
157eb4ea085SAngus Ainslie (Purism)	};
158eb4ea085SAngus Ainslie (Purism)
159eb4ea085SAngus Ainslie (Purism)	wifi_pwr_en: regulator-wifi-en {
160eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
161eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
162eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
163eb4ea085SAngus Ainslie (Purism)		regulator-name = "WIFI_EN";
164eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
165eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
166eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
167eb4ea085SAngus Ainslie (Purism)		enable-active-high;
168eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
169eb4ea085SAngus Ainslie (Purism)	};
170eb4ea085SAngus Ainslie (Purism)};
171eb4ea085SAngus Ainslie (Purism)
172eb4ea085SAngus Ainslie (Purism)&clk {
173eb4ea085SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
174eb4ea085SAngus Ainslie (Purism)	assigned-clock-rates = <786432000>, <722534400>;
175eb4ea085SAngus Ainslie (Purism)};
176eb4ea085SAngus Ainslie (Purism)
177eb4ea085SAngus Ainslie (Purism)&fec1 {
178eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
179eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_fec1>;
180eb4ea085SAngus Ainslie (Purism)	phy-mode = "rgmii-id";
181eb4ea085SAngus Ainslie (Purism)	phy-handle = <&ethphy0>;
182eb4ea085SAngus Ainslie (Purism)	fsl,magic-packet;
183eb4ea085SAngus Ainslie (Purism)	phy-supply = <&reg_3v3_p>;
184eb4ea085SAngus Ainslie (Purism)	status = "okay";
185eb4ea085SAngus Ainslie (Purism)
186eb4ea085SAngus Ainslie (Purism)	mdio {
187eb4ea085SAngus Ainslie (Purism)		#address-cells = <1>;
188eb4ea085SAngus Ainslie (Purism)		#size-cells = <0>;
189eb4ea085SAngus Ainslie (Purism)
190eb4ea085SAngus Ainslie (Purism)		ethphy0: ethernet-phy@1 {
191eb4ea085SAngus Ainslie (Purism)			compatible = "ethernet-phy-ieee802.3-c22";
192eb4ea085SAngus Ainslie (Purism)			reg = <1>;
193eb4ea085SAngus Ainslie (Purism)		};
194eb4ea085SAngus Ainslie (Purism)	};
195eb4ea085SAngus Ainslie (Purism)};
196eb4ea085SAngus Ainslie (Purism)
197eb4ea085SAngus Ainslie (Purism)&i2c1 {
198eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
199eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
200eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c1>;
201eb4ea085SAngus Ainslie (Purism)	status = "okay";
202eb4ea085SAngus Ainslie (Purism)
203eb4ea085SAngus Ainslie (Purism)	pmic: pmic@4b {
204eb4ea085SAngus Ainslie (Purism)		compatible = "rohm,bd71837";
205eb4ea085SAngus Ainslie (Purism)		reg = <0x4b>;
206eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
207eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pmic>;
208eb4ea085SAngus Ainslie (Purism)		clocks = <&pmic_osc>;
209eb4ea085SAngus Ainslie (Purism)		clock-names = "osc";
210eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_clk";
211eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio1>;
212eb4ea085SAngus Ainslie (Purism)		interrupts = <3 GPIO_ACTIVE_LOW>;
213eb4ea085SAngus Ainslie (Purism)		interrupt-names = "irq";
214eb4ea085SAngus Ainslie (Purism)		rohm,reset-snvs-powered;
215eb4ea085SAngus Ainslie (Purism)
216eb4ea085SAngus Ainslie (Purism)		regulators {
217eb4ea085SAngus Ainslie (Purism)			buck1_reg: BUCK1 {
218eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck1";
219eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
220eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
221eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
222eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
223eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <900000>;
224eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <850000>;
225eb4ea085SAngus Ainslie (Purism)				rohm,dvs-suspend-voltage = <800000>;
226eb4ea085SAngus Ainslie (Purism)			};
227eb4ea085SAngus Ainslie (Purism)
228eb4ea085SAngus Ainslie (Purism)			buck2_reg: BUCK2 {
229eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck2";
230eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
231eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
232eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
233eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
234eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
235eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <900000>;
236eb4ea085SAngus Ainslie (Purism)			};
237eb4ea085SAngus Ainslie (Purism)
238eb4ea085SAngus Ainslie (Purism)			buck3_reg: BUCK3 {
239eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck3";
240eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
241eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
242eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
243eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
244eb4ea085SAngus Ainslie (Purism)			};
245eb4ea085SAngus Ainslie (Purism)
246eb4ea085SAngus Ainslie (Purism)			buck4_reg: BUCK4 {
247eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck4";
248eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
249eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
250eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
251eb4ea085SAngus Ainslie (Purism)			};
252eb4ea085SAngus Ainslie (Purism)
253eb4ea085SAngus Ainslie (Purism)			buck5_reg: BUCK5 {
254eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck5";
255eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
256eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1350000>;
257eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
258eb4ea085SAngus Ainslie (Purism)			};
259eb4ea085SAngus Ainslie (Purism)
260eb4ea085SAngus Ainslie (Purism)			buck6_reg: BUCK6 {
261eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck6";
262eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
263eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
264eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
265eb4ea085SAngus Ainslie (Purism)			};
266eb4ea085SAngus Ainslie (Purism)
267eb4ea085SAngus Ainslie (Purism)			buck7_reg: BUCK7 {
268eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck7";
269eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1605000>;
270eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1995000>;
271eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
272eb4ea085SAngus Ainslie (Purism)			};
273eb4ea085SAngus Ainslie (Purism)
274eb4ea085SAngus Ainslie (Purism)			buck8_reg: BUCK8 {
275eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck8";
276eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <800000>;
277eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1400000>;
278eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
279eb4ea085SAngus Ainslie (Purism)			};
280eb4ea085SAngus Ainslie (Purism)
281eb4ea085SAngus Ainslie (Purism)			ldo1_reg: LDO1 {
282eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo1";
283eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
284eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
285eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
286eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
287eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
288eb4ea085SAngus Ainslie (Purism)			};
289eb4ea085SAngus Ainslie (Purism)
290eb4ea085SAngus Ainslie (Purism)			ldo2_reg: LDO2 {
291eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo2";
292eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
293eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <900000>;
294eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
295eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
296eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
297eb4ea085SAngus Ainslie (Purism)			};
298eb4ea085SAngus Ainslie (Purism)
299eb4ea085SAngus Ainslie (Purism)			ldo3_reg: LDO3 {
300eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo3";
301eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
302eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
303eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
304eb4ea085SAngus Ainslie (Purism)			};
305eb4ea085SAngus Ainslie (Purism)
306eb4ea085SAngus Ainslie (Purism)			ldo4_reg: LDO4 {
307eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo4";
308eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
309eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
310eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
311eb4ea085SAngus Ainslie (Purism)			};
312eb4ea085SAngus Ainslie (Purism)
313eb4ea085SAngus Ainslie (Purism)			ldo5_reg: LDO5 {
314eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo5";
315eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
316eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
317eb4ea085SAngus Ainslie (Purism)			};
318eb4ea085SAngus Ainslie (Purism)
319eb4ea085SAngus Ainslie (Purism)			ldo6_reg: LDO6 {
320eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo6";
321eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
322eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
323eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
324eb4ea085SAngus Ainslie (Purism)			};
325eb4ea085SAngus Ainslie (Purism)
326eb4ea085SAngus Ainslie (Purism)			ldo7_reg: LDO7 {
327eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo7";
328eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
329eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
330eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
331eb4ea085SAngus Ainslie (Purism)			};
332eb4ea085SAngus Ainslie (Purism)		};
333eb4ea085SAngus Ainslie (Purism)	};
334eb4ea085SAngus Ainslie (Purism)
335eb4ea085SAngus Ainslie (Purism)	typec_ptn5100: usb_typec@52 {
336eb4ea085SAngus Ainslie (Purism)		compatible = "nxp,ptn5110";
337eb4ea085SAngus Ainslie (Purism)		reg = <0x52>;
338eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
339eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_typec>;
340eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
341eb4ea085SAngus Ainslie (Purism)		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
342eb4ea085SAngus Ainslie (Purism)
343eb4ea085SAngus Ainslie (Purism)		connector {
344eb4ea085SAngus Ainslie (Purism)			compatible = "usb-c-connector";
345eb4ea085SAngus Ainslie (Purism)			label = "USB-C";
346eb4ea085SAngus Ainslie (Purism)			data-role = "dual";
347eb4ea085SAngus Ainslie (Purism)			power-role = "dual";
348eb4ea085SAngus Ainslie (Purism)			try-power-role = "sink";
349eb4ea085SAngus Ainslie (Purism)			source-pdos = <PDO_FIXED(5000, 2000,
350eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_USB_COMM |
351eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
352eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )>;
353eb4ea085SAngus Ainslie (Purism)			sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM |
354eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
355eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )
356eb4ea085SAngus Ainslie (Purism)			     PDO_VAR(5000, 12000, 2000)>;
357eb4ea085SAngus Ainslie (Purism)			op-sink-microwatt = <10000000>;
358eb4ea085SAngus Ainslie (Purism)
359eb4ea085SAngus Ainslie (Purism)			ports {
360eb4ea085SAngus Ainslie (Purism)				#address-cells = <1>;
361eb4ea085SAngus Ainslie (Purism)				#size-cells = <0>;
362eb4ea085SAngus Ainslie (Purism)
363eb4ea085SAngus Ainslie (Purism)				port@0 {
364eb4ea085SAngus Ainslie (Purism)					reg = <0>;
365eb4ea085SAngus Ainslie (Purism)
366eb4ea085SAngus Ainslie (Purism)					usb_con_hs: endpoint {
367eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_hs>;
368eb4ea085SAngus Ainslie (Purism)					};
369eb4ea085SAngus Ainslie (Purism)				};
370eb4ea085SAngus Ainslie (Purism)
371eb4ea085SAngus Ainslie (Purism)				port@1 {
372eb4ea085SAngus Ainslie (Purism)					reg = <1>;
373eb4ea085SAngus Ainslie (Purism)
374eb4ea085SAngus Ainslie (Purism)					usb_con_ss: endpoint {
375eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_ss>;
376eb4ea085SAngus Ainslie (Purism)					};
377eb4ea085SAngus Ainslie (Purism)				};
378eb4ea085SAngus Ainslie (Purism)			};
379eb4ea085SAngus Ainslie (Purism)		};
380eb4ea085SAngus Ainslie (Purism)	};
381eb4ea085SAngus Ainslie (Purism)
382eb4ea085SAngus Ainslie (Purism)	rtc@68 {
383eb4ea085SAngus Ainslie (Purism)		compatible = "microcrystal,rv4162";
384eb4ea085SAngus Ainslie (Purism)		reg = <0x68>;
385eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
386eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_rtc>;
387eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio4>;
388eb4ea085SAngus Ainslie (Purism)		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
389eb4ea085SAngus Ainslie (Purism)	};
390eb4ea085SAngus Ainslie (Purism)
391eb4ea085SAngus Ainslie (Purism)	charger@6b { /* bq25896 */
392eb4ea085SAngus Ainslie (Purism)		compatible = "ti,bq25890";
393eb4ea085SAngus Ainslie (Purism)		reg = <0x6b>;
394eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
395eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_charger>;
396eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
397eb4ea085SAngus Ainslie (Purism)		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
398eb4ea085SAngus Ainslie (Purism)		ti,battery-regulation-voltage = <4192000>; /* 4.192V */
399eb4ea085SAngus Ainslie (Purism)		ti,charge-current = <1600000>; /* 1.6A */
400eb4ea085SAngus Ainslie (Purism)		ti,termination-current = <66000>;  /* 66mA */
401eb4ea085SAngus Ainslie (Purism)		ti,precharge-current = <130000>; /* 130mA */
402eb4ea085SAngus Ainslie (Purism)		ti,minimum-sys-voltage = <3000000>; /* 3V */
403eb4ea085SAngus Ainslie (Purism)		ti,boost-voltage = <5000000>; /* 5V */
404eb4ea085SAngus Ainslie (Purism)		ti,boost-max-current = <50000>; /* 50mA */
405eb4ea085SAngus Ainslie (Purism)	};
406eb4ea085SAngus Ainslie (Purism)};
407eb4ea085SAngus Ainslie (Purism)
408eb4ea085SAngus Ainslie (Purism)&i2c3 {
409eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
410eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
411eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c3>;
412eb4ea085SAngus Ainslie (Purism)	status = "okay";
413eb4ea085SAngus Ainslie (Purism)
414eb4ea085SAngus Ainslie (Purism)	magnetometer@1e	{
415eb4ea085SAngus Ainslie (Purism)		compatible = "st,lsm9ds1-magn";
416eb4ea085SAngus Ainslie (Purism)		reg = <0x1e>;
417eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
418eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_imu>;
419eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
420eb4ea085SAngus Ainslie (Purism)		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
421eb4ea085SAngus Ainslie (Purism)		vdd-supply = <&reg_3v3_p>;
422eb4ea085SAngus Ainslie (Purism)		vddio-supply = <&reg_3v3_p>;
423eb4ea085SAngus Ainslie (Purism)	};
424eb4ea085SAngus Ainslie (Purism)
425eb4ea085SAngus Ainslie (Purism)	touchscreen@5d {
426eb4ea085SAngus Ainslie (Purism)		compatible = "goodix,gt5688";
427eb4ea085SAngus Ainslie (Purism)		reg = <0x5d>;
428eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
429eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_ts>;
430eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
431eb4ea085SAngus Ainslie (Purism)		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
432eb4ea085SAngus Ainslie (Purism)		reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
433eb4ea085SAngus Ainslie (Purism)		irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
434eb4ea085SAngus Ainslie (Purism)		touchscreen-size-x = <720>;
435eb4ea085SAngus Ainslie (Purism)		touchscreen-size-y = <1440>;
436eb4ea085SAngus Ainslie (Purism)		AVDD28-supply = <&reg_2v8_p>;
437eb4ea085SAngus Ainslie (Purism)		VDDIO-supply = <&reg_1v8_p>;
438eb4ea085SAngus Ainslie (Purism)	};
439eb4ea085SAngus Ainslie (Purism)};
440eb4ea085SAngus Ainslie (Purism)
441eb4ea085SAngus Ainslie (Purism)&iomuxc {
442eb4ea085SAngus Ainslie (Purism)	pinctrl_bl: blgrp {
443eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
444eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT	0x6 /* DSI_BL_PWM */
445eb4ea085SAngus Ainslie (Purism)		>;
446eb4ea085SAngus Ainslie (Purism)	};
447eb4ea085SAngus Ainslie (Purism)
448eb4ea085SAngus Ainslie (Purism)	pinctrl_bt: btgrp {
449eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
450eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11	0x16 /* nBT_DISABLE */
451eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7	0x10 /* BT_HOST_WAKE */
452eb4ea085SAngus Ainslie (Purism)		>;
453eb4ea085SAngus Ainslie (Purism)	};
454eb4ea085SAngus Ainslie (Purism)
455eb4ea085SAngus Ainslie (Purism)	pinctrl_charger: chargergrp {
456eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
457eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x80 /* CHRG_nINT */
458eb4ea085SAngus Ainslie (Purism)		>;
459eb4ea085SAngus Ainslie (Purism)	};
460eb4ea085SAngus Ainslie (Purism)
461eb4ea085SAngus Ainslie (Purism)	pinctrl_fec1: fec1grp {
462eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
463eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
464eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
465eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
466eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
467eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
468eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
469eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
470eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
471eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
472eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
473eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
474eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
475eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
476eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
477eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
478eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x1f
479eb4ea085SAngus Ainslie (Purism)		>;
480eb4ea085SAngus Ainslie (Purism)	};
481eb4ea085SAngus Ainslie (Purism)
482eb4ea085SAngus Ainslie (Purism)	pinctrl_ts: tsgrp {
483eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
484eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0		0x16  /* TOUCH INT */
485eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19  /* TOUCH RST */
486eb4ea085SAngus Ainslie (Purism)		>;
487eb4ea085SAngus Ainslie (Purism)	};
488eb4ea085SAngus Ainslie (Purism)
489eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_leds: gpioledgrp {
490eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
491eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16
492eb4ea085SAngus Ainslie (Purism)		>;
493eb4ea085SAngus Ainslie (Purism)	};
494eb4ea085SAngus Ainslie (Purism)
495eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_keys: gpiokeygrp {
496eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
497eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x16
498eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22	0x16
499eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x180  /* HP_DET */
500eb4ea085SAngus Ainslie (Purism)		>;
501eb4ea085SAngus Ainslie (Purism)	};
502eb4ea085SAngus Ainslie (Purism)
503eb4ea085SAngus Ainslie (Purism)	pinctrl_haptic: hapticgrp {
504eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
505eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4		0xc6   /* nHAPTIC */
506eb4ea085SAngus Ainslie (Purism)		>;
507eb4ea085SAngus Ainslie (Purism)	};
508eb4ea085SAngus Ainslie (Purism)
509eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c1: i2c1grp {
510eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
511eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000001f
512eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000001f
513eb4ea085SAngus Ainslie (Purism)		>;
514eb4ea085SAngus Ainslie (Purism)	};
515eb4ea085SAngus Ainslie (Purism)
516eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c3: i2c3grp {
517eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
518eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x4000001f
519eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x4000001f
520eb4ea085SAngus Ainslie (Purism)		>;
521eb4ea085SAngus Ainslie (Purism)	};
522eb4ea085SAngus Ainslie (Purism)
523eb4ea085SAngus Ainslie (Purism)	pinctrl_imu: imugrp {
524eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
525eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x8  /* IMU_INT */
526eb4ea085SAngus Ainslie (Purism)		>;
527eb4ea085SAngus Ainslie (Purism)	};
528eb4ea085SAngus Ainslie (Purism)
529eb4ea085SAngus Ainslie (Purism)	pinctrl_pmic: pmicgrp {
530eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
531eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x80  /* PMIC intr */
532eb4ea085SAngus Ainslie (Purism)		>;
533eb4ea085SAngus Ainslie (Purism)	};
534eb4ea085SAngus Ainslie (Purism)
535eb4ea085SAngus Ainslie (Purism)	pinctrl_pwr_en: pwrengrp {
536eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
537eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x06
538eb4ea085SAngus Ainslie (Purism)		>;
539eb4ea085SAngus Ainslie (Purism)	};
540eb4ea085SAngus Ainslie (Purism)
541eb4ea085SAngus Ainslie (Purism)	pinctrl_rtc: rtcgrp {
542eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
543eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29	0x80  /* RTC intr */
544eb4ea085SAngus Ainslie (Purism)		>;
545eb4ea085SAngus Ainslie (Purism)	};
546eb4ea085SAngus Ainslie (Purism)
547eb4ea085SAngus Ainslie (Purism)	pinctrl_typec: typecgrp {
548eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
549eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x16
550eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x80
551eb4ea085SAngus Ainslie (Purism)		>;
552eb4ea085SAngus Ainslie (Purism)	};
553eb4ea085SAngus Ainslie (Purism)
554eb4ea085SAngus Ainslie (Purism)	pinctrl_uart1: uart1grp {
555eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
556eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
557eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
558eb4ea085SAngus Ainslie (Purism)		>;
559eb4ea085SAngus Ainslie (Purism)	};
560eb4ea085SAngus Ainslie (Purism)
561eb4ea085SAngus Ainslie (Purism)	pinctrl_uart2: uart2grp {
562eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
563eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
564eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
565eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
566eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
567eb4ea085SAngus Ainslie (Purism)		>;
568eb4ea085SAngus Ainslie (Purism)	};
569eb4ea085SAngus Ainslie (Purism)
570eb4ea085SAngus Ainslie (Purism)	pinctrl_uart3: uart3grp {
571eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
572eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
573eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
574eb4ea085SAngus Ainslie (Purism)		>;
575eb4ea085SAngus Ainslie (Purism)	};
576eb4ea085SAngus Ainslie (Purism)
577eb4ea085SAngus Ainslie (Purism)	pinctrl_uart4: uart4grp {
578eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
579eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
580eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
581eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x49
582eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49
583eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x49
584eb4ea085SAngus Ainslie (Purism)		>;
585eb4ea085SAngus Ainslie (Purism)	};
586eb4ea085SAngus Ainslie (Purism)
587eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1: usdhc1grp {
588eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
589eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
590eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
591eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
592eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
593eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
594eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
595eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
596eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
597eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
598eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
599eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
600eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
601eb4ea085SAngus Ainslie (Purism)		>;
602eb4ea085SAngus Ainslie (Purism)	};
603eb4ea085SAngus Ainslie (Purism)
604eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
605eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
606eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
607eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
608eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
609eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
610eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
611eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
612eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
613eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
614eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
615eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
616eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
617eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
618eb4ea085SAngus Ainslie (Purism)		>;
619eb4ea085SAngus Ainslie (Purism)	};
620eb4ea085SAngus Ainslie (Purism)
621eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
622eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
623eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
624eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
625eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
626eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
627eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
628eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
629eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
630eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
631eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
632eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
633eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
634eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
635eb4ea085SAngus Ainslie (Purism)		>;
636eb4ea085SAngus Ainslie (Purism)	};
637eb4ea085SAngus Ainslie (Purism)
638eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_pwr: usdhc2grppwr {
639eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
640eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
641eb4ea085SAngus Ainslie (Purism)		>;
642eb4ea085SAngus Ainslie (Purism)	};
643eb4ea085SAngus Ainslie (Purism)
644eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_gpio: usdhc2grpgpio {
645eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
646eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */
647eb4ea085SAngus Ainslie (Purism)		>;
648eb4ea085SAngus Ainslie (Purism)	};
649eb4ea085SAngus Ainslie (Purism)
650eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2: usdhc2grp {
651eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
652eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
653eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
654eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
655eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
656eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
657eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
658eb4ea085SAngus Ainslie (Purism)		>;
659eb4ea085SAngus Ainslie (Purism)	};
660eb4ea085SAngus Ainslie (Purism)
661eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
662eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
663eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d
664eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd
665eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcd
666eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcd
667eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcd
668eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcd
669eb4ea085SAngus Ainslie (Purism)		>;
670eb4ea085SAngus Ainslie (Purism)	};
671eb4ea085SAngus Ainslie (Purism)
672eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
673eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
674eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f
675eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf
676eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcf
677eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcf
678eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcf
679eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcf
680eb4ea085SAngus Ainslie (Purism)		>;
681eb4ea085SAngus Ainslie (Purism)	};
682eb4ea085SAngus Ainslie (Purism)
683eb4ea085SAngus Ainslie (Purism)	pinctrl_wdog: wdoggrp {
684eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
685eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
686eb4ea085SAngus Ainslie (Purism)		>;
687eb4ea085SAngus Ainslie (Purism)	};
688eb4ea085SAngus Ainslie (Purism)
689eb4ea085SAngus Ainslie (Purism)	pinctrl_wifi_pwr_en: wifipwrengrp {
690eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
691eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5         0x06
692eb4ea085SAngus Ainslie (Purism)		>;
693eb4ea085SAngus Ainslie (Purism)	};
694eb4ea085SAngus Ainslie (Purism)
695eb4ea085SAngus Ainslie (Purism)	pinctrl_wwan: wwangrp {
696eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
697eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x09 /* nWWAN_DISABLE */
698eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80 /* nWoWWAN */
699eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9	0x19 /* WWAN_RESET */
700eb4ea085SAngus Ainslie (Purism)		>;
701eb4ea085SAngus Ainslie (Purism)	};
702eb4ea085SAngus Ainslie (Purism)};
703eb4ea085SAngus Ainslie (Purism)
704eb4ea085SAngus Ainslie (Purism)&pgc_gpu {
705eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck3_reg>;
706eb4ea085SAngus Ainslie (Purism)};
707eb4ea085SAngus Ainslie (Purism)
708eb4ea085SAngus Ainslie (Purism)&pgc_vpu {
709eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck4_reg>;
710eb4ea085SAngus Ainslie (Purism)};
711eb4ea085SAngus Ainslie (Purism)
712eb4ea085SAngus Ainslie (Purism)&pwm1 {
713eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
714eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_bl>;
715eb4ea085SAngus Ainslie (Purism)	status = "okay";
716eb4ea085SAngus Ainslie (Purism)};
717eb4ea085SAngus Ainslie (Purism)
718eb4ea085SAngus Ainslie (Purism)
719eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */
720eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
721eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart1>;
722eb4ea085SAngus Ainslie (Purism)	status = "okay";
723eb4ea085SAngus Ainslie (Purism)};
724eb4ea085SAngus Ainslie (Purism)
725eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */
726eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
727eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart3>;
728eb4ea085SAngus Ainslie (Purism)	status = "okay";
729eb4ea085SAngus Ainslie (Purism)};
730eb4ea085SAngus Ainslie (Purism)
731eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */
732eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
733eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
734eb4ea085SAngus Ainslie (Purism)	uart-has-rtscts;
735eb4ea085SAngus Ainslie (Purism)	status = "okay";
736eb4ea085SAngus Ainslie (Purism)};
737eb4ea085SAngus Ainslie (Purism)
738eb4ea085SAngus Ainslie (Purism)&usb3_phy0 {
739eb4ea085SAngus Ainslie (Purism)	status = "okay";
740eb4ea085SAngus Ainslie (Purism)};
741eb4ea085SAngus Ainslie (Purism)
742eb4ea085SAngus Ainslie (Purism)&usb3_phy1 {
743eb4ea085SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
744eb4ea085SAngus Ainslie (Purism)	status = "okay";
745eb4ea085SAngus Ainslie (Purism)};
746eb4ea085SAngus Ainslie (Purism)
747eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 {
748eb4ea085SAngus Ainslie (Purism)	#address-cells = <1>;
749eb4ea085SAngus Ainslie (Purism)	#size-cells = <0>;
750eb4ea085SAngus Ainslie (Purism)	dr_mode = "otg";
751eb4ea085SAngus Ainslie (Purism)	status = "okay";
752eb4ea085SAngus Ainslie (Purism)
753eb4ea085SAngus Ainslie (Purism)	port@0 {
754eb4ea085SAngus Ainslie (Purism)		reg = <0>;
755eb4ea085SAngus Ainslie (Purism)
756eb4ea085SAngus Ainslie (Purism)		typec_hs: endpoint {
757eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_hs>;
758eb4ea085SAngus Ainslie (Purism)		};
759eb4ea085SAngus Ainslie (Purism)	};
760eb4ea085SAngus Ainslie (Purism)
761eb4ea085SAngus Ainslie (Purism)	port@1 {
762eb4ea085SAngus Ainslie (Purism)		reg = <1>;
763eb4ea085SAngus Ainslie (Purism)
764eb4ea085SAngus Ainslie (Purism)		typec_ss: endpoint {
765eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_ss>;
766eb4ea085SAngus Ainslie (Purism)		};
767eb4ea085SAngus Ainslie (Purism)	};
768eb4ea085SAngus Ainslie (Purism)};
769eb4ea085SAngus Ainslie (Purism)
770eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 {
771eb4ea085SAngus Ainslie (Purism)	dr_mode = "host";
772eb4ea085SAngus Ainslie (Purism)	status = "okay";
773eb4ea085SAngus Ainslie (Purism)};
774eb4ea085SAngus Ainslie (Purism)
775eb4ea085SAngus Ainslie (Purism)&usdhc1 {
776eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
777eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc1>;
778eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
779eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
780eb4ea085SAngus Ainslie (Purism)	bus-width = <8>;
781eb4ea085SAngus Ainslie (Purism)	non-removable;
782eb4ea085SAngus Ainslie (Purism)	status = "okay";
783eb4ea085SAngus Ainslie (Purism)};
784eb4ea085SAngus Ainslie (Purism)
785eb4ea085SAngus Ainslie (Purism)&usdhc2 {
786eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
787eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc2>;
788eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
789eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
790eb4ea085SAngus Ainslie (Purism)	bus-width = <4>;
791eb4ea085SAngus Ainslie (Purism)	vmmc-supply = <&reg_usdhc2_vmmc>;
792eb4ea085SAngus Ainslie (Purism)	power-supply = <&wifi_pwr_en>;
793eb4ea085SAngus Ainslie (Purism)	non-removable;
794eb4ea085SAngus Ainslie (Purism)	disable-wp;
795eb4ea085SAngus Ainslie (Purism)	cap-sdio-irq;
796eb4ea085SAngus Ainslie (Purism)	keep-power-in-suspend;
797eb4ea085SAngus Ainslie (Purism)	wakeup-source;
798eb4ea085SAngus Ainslie (Purism)	status = "okay";
799eb4ea085SAngus Ainslie (Purism)};
800eb4ea085SAngus Ainslie (Purism)
801eb4ea085SAngus Ainslie (Purism)&wdog1 {
802eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
803eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_wdog>;
804eb4ea085SAngus Ainslie (Purism)	fsl,ext-reset-output;
805eb4ea085SAngus Ainslie (Purism)	status = "okay";
806eb4ea085SAngus Ainslie (Purism)};
807