1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+ 2eb4ea085SAngus Ainslie (Purism)/* 3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC 4eb4ea085SAngus Ainslie (Purism) */ 5eb4ea085SAngus Ainslie (Purism) 6eb4ea085SAngus Ainslie (Purism)/dts-v1/; 7eb4ea085SAngus Ainslie (Purism) 8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h" 9eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h" 10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h" 11eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi" 12eb4ea085SAngus Ainslie (Purism) 13eb4ea085SAngus Ainslie (Purism)/ { 14eb4ea085SAngus Ainslie (Purism) model = "Purism Librem 5 devkit"; 15eb4ea085SAngus Ainslie (Purism) compatible = "purism,librem5-devkit", "fsl,imx8mq"; 16eb4ea085SAngus Ainslie (Purism) 17eb4ea085SAngus Ainslie (Purism) backlight_dsi: backlight-dsi { 18eb4ea085SAngus Ainslie (Purism) compatible = "pwm-backlight"; 19eb4ea085SAngus Ainslie (Purism) /* 200 Hz for the PAM2841 */ 20eb4ea085SAngus Ainslie (Purism) pwms = <&pwm1 0 5000000>; 21eb4ea085SAngus Ainslie (Purism) brightness-levels = <0 100>; 22eb4ea085SAngus Ainslie (Purism) num-interpolated-steps = <100>; 23eb4ea085SAngus Ainslie (Purism) /* Default brightness level (index into the array defined by */ 24eb4ea085SAngus Ainslie (Purism) /* the "brightness-levels" property) */ 25eb4ea085SAngus Ainslie (Purism) default-brightness-level = <0>; 26eb4ea085SAngus Ainslie (Purism) power-supply = <®_22v4_p>; 27eb4ea085SAngus Ainslie (Purism) }; 28eb4ea085SAngus Ainslie (Purism) 29eb4ea085SAngus Ainslie (Purism) chosen { 30eb4ea085SAngus Ainslie (Purism) stdout-path = &uart1; 31eb4ea085SAngus Ainslie (Purism) }; 32eb4ea085SAngus Ainslie (Purism) 33eb4ea085SAngus Ainslie (Purism) gpio-keys { 34eb4ea085SAngus Ainslie (Purism) compatible = "gpio-keys"; 35eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 36eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_keys>; 37eb4ea085SAngus Ainslie (Purism) 38eb4ea085SAngus Ainslie (Purism) btn1 { 39eb4ea085SAngus Ainslie (Purism) label = "VOL_UP"; 40eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 41eb4ea085SAngus Ainslie (Purism) wakeup-source; 42eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEUP>; 43eb4ea085SAngus Ainslie (Purism) }; 44eb4ea085SAngus Ainslie (Purism) 45eb4ea085SAngus Ainslie (Purism) btn2 { 46eb4ea085SAngus Ainslie (Purism) label = "VOL_DOWN"; 47eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 48eb4ea085SAngus Ainslie (Purism) wakeup-source; 49eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEDOWN>; 50eb4ea085SAngus Ainslie (Purism) }; 51eb4ea085SAngus Ainslie (Purism) 52eb4ea085SAngus Ainslie (Purism) hp-det { 53eb4ea085SAngus Ainslie (Purism) label = "HP_DET"; 54eb4ea085SAngus Ainslie (Purism) gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 55eb4ea085SAngus Ainslie (Purism) wakeup-source; 56eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_HP>; 57eb4ea085SAngus Ainslie (Purism) }; 58eb4ea085SAngus Ainslie (Purism) }; 59eb4ea085SAngus Ainslie (Purism) 60eb4ea085SAngus Ainslie (Purism) leds { 61eb4ea085SAngus Ainslie (Purism) compatible = "gpio-leds"; 62eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 63eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_leds>; 64eb4ea085SAngus Ainslie (Purism) 65eb4ea085SAngus Ainslie (Purism) led1 { 66eb4ea085SAngus Ainslie (Purism) label = "LED 1"; 67eb4ea085SAngus Ainslie (Purism) gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 68eb4ea085SAngus Ainslie (Purism) default-state = "off"; 69eb4ea085SAngus Ainslie (Purism) }; 70eb4ea085SAngus Ainslie (Purism) }; 71eb4ea085SAngus Ainslie (Purism) 72eb4ea085SAngus Ainslie (Purism) pmic_osc: clock-pmic { 73eb4ea085SAngus Ainslie (Purism) compatible = "fixed-clock"; 74eb4ea085SAngus Ainslie (Purism) #clock-cells = <0>; 75eb4ea085SAngus Ainslie (Purism) clock-frequency = <32768>; 76eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_osc"; 77eb4ea085SAngus Ainslie (Purism) }; 78eb4ea085SAngus Ainslie (Purism) 79eb4ea085SAngus Ainslie (Purism) reg_1v8_p: regulator-1v8-p { 80eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 81eb4ea085SAngus Ainslie (Purism) regulator-name = "1v8_p"; 82eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 83eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 84eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 85eb4ea085SAngus Ainslie (Purism) }; 86eb4ea085SAngus Ainslie (Purism) 87eb4ea085SAngus Ainslie (Purism) reg_2v8_p: regulator-2v8-p { 88eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 89eb4ea085SAngus Ainslie (Purism) regulator-name = "2v8_p"; 90eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <2800000>; 91eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <2800000>; 92eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 93eb4ea085SAngus Ainslie (Purism) }; 94eb4ea085SAngus Ainslie (Purism) 95eb4ea085SAngus Ainslie (Purism) reg_3v3_p: regulator-3v3-p { 96eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 97eb4ea085SAngus Ainslie (Purism) regulator-name = "3v3_p"; 98eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 99eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 100eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 101eb4ea085SAngus Ainslie (Purism) 102eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 103eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 104eb4ea085SAngus Ainslie (Purism) }; 105eb4ea085SAngus Ainslie (Purism) }; 106eb4ea085SAngus Ainslie (Purism) 107eb4ea085SAngus Ainslie (Purism) reg_5v_p: regulator-5v-p { 108eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 109eb4ea085SAngus Ainslie (Purism) regulator-name = "5v_p"; 110eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <5000000>; 111eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <5000000>; 112eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 113eb4ea085SAngus Ainslie (Purism) 114eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 115eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 116eb4ea085SAngus Ainslie (Purism) }; 117eb4ea085SAngus Ainslie (Purism) }; 118eb4ea085SAngus Ainslie (Purism) 119eb4ea085SAngus Ainslie (Purism) reg_22v4_p: regulator-22v4-p { 120eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 121eb4ea085SAngus Ainslie (Purism) regulator-name = "22v4_P"; 122eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <22400000>; 123eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <22400000>; 124eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 125eb4ea085SAngus Ainslie (Purism) }; 126eb4ea085SAngus Ainslie (Purism) 127eb4ea085SAngus Ainslie (Purism) reg_pwr_en: regulator-pwr-en { 128eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 129eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 130eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pwr_en>; 131eb4ea085SAngus Ainslie (Purism) regulator-name = "PWR_EN"; 132eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 133eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 134eb4ea085SAngus Ainslie (Purism) gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 135eb4ea085SAngus Ainslie (Purism) enable-active-high; 136eb4ea085SAngus Ainslie (Purism) regulator-always-on; 137eb4ea085SAngus Ainslie (Purism) }; 138eb4ea085SAngus Ainslie (Purism) 139eb4ea085SAngus Ainslie (Purism) reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 140eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 141eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 142eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2_pwr>; 143eb4ea085SAngus Ainslie (Purism) regulator-name = "VSD_3V3"; 144eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 145eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 146eb4ea085SAngus Ainslie (Purism) gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 147eb4ea085SAngus Ainslie (Purism) enable-active-high; 148eb4ea085SAngus Ainslie (Purism) regulator-always-on; 149eb4ea085SAngus Ainslie (Purism) }; 150eb4ea085SAngus Ainslie (Purism) 151eb4ea085SAngus Ainslie (Purism) vibrator { 152eb4ea085SAngus Ainslie (Purism) compatible = "gpio-vibrator"; 153eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 154eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_haptic>; 155eb4ea085SAngus Ainslie (Purism) enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; 156eb4ea085SAngus Ainslie (Purism) vcc-supply = <®_3v3_p>; 157eb4ea085SAngus Ainslie (Purism) }; 158eb4ea085SAngus Ainslie (Purism) 159eb4ea085SAngus Ainslie (Purism) wifi_pwr_en: regulator-wifi-en { 160eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 161eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 162eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wifi_pwr_en>; 163eb4ea085SAngus Ainslie (Purism) regulator-name = "WIFI_EN"; 164eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 165eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 166eb4ea085SAngus Ainslie (Purism) gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 167eb4ea085SAngus Ainslie (Purism) enable-active-high; 168eb4ea085SAngus Ainslie (Purism) regulator-always-on; 169eb4ea085SAngus Ainslie (Purism) }; 170eb4ea085SAngus Ainslie (Purism)}; 171eb4ea085SAngus Ainslie (Purism) 172eb4ea085SAngus Ainslie (Purism)&clk { 173eb4ea085SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; 174eb4ea085SAngus Ainslie (Purism) assigned-clock-rates = <786432000>, <722534400>; 175eb4ea085SAngus Ainslie (Purism)}; 176eb4ea085SAngus Ainslie (Purism) 1779d9005a5SGuido Günther&dphy { 1789d9005a5SGuido Günther status = "okay"; 1799d9005a5SGuido Günther}; 1809d9005a5SGuido Günther 181eb4ea085SAngus Ainslie (Purism)&fec1 { 182eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 183eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_fec1>; 184eb4ea085SAngus Ainslie (Purism) phy-mode = "rgmii-id"; 185eb4ea085SAngus Ainslie (Purism) phy-handle = <ðphy0>; 186eb4ea085SAngus Ainslie (Purism) fsl,magic-packet; 187eb4ea085SAngus Ainslie (Purism) phy-supply = <®_3v3_p>; 188eb4ea085SAngus Ainslie (Purism) status = "okay"; 189eb4ea085SAngus Ainslie (Purism) 190eb4ea085SAngus Ainslie (Purism) mdio { 191eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 192eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 193eb4ea085SAngus Ainslie (Purism) 194eb4ea085SAngus Ainslie (Purism) ethphy0: ethernet-phy@1 { 195eb4ea085SAngus Ainslie (Purism) compatible = "ethernet-phy-ieee802.3-c22"; 196eb4ea085SAngus Ainslie (Purism) reg = <1>; 197eb4ea085SAngus Ainslie (Purism) }; 198eb4ea085SAngus Ainslie (Purism) }; 199eb4ea085SAngus Ainslie (Purism)}; 200eb4ea085SAngus Ainslie (Purism) 201eb4ea085SAngus Ainslie (Purism)&i2c1 { 202eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 203eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 204eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c1>; 205eb4ea085SAngus Ainslie (Purism) status = "okay"; 206eb4ea085SAngus Ainslie (Purism) 207eb4ea085SAngus Ainslie (Purism) pmic: pmic@4b { 208eb4ea085SAngus Ainslie (Purism) compatible = "rohm,bd71837"; 209eb4ea085SAngus Ainslie (Purism) reg = <0x4b>; 210eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 211eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pmic>; 212eb4ea085SAngus Ainslie (Purism) clocks = <&pmic_osc>; 213eb4ea085SAngus Ainslie (Purism) clock-names = "osc"; 214eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_clk"; 215eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio1>; 216eb4ea085SAngus Ainslie (Purism) interrupts = <3 GPIO_ACTIVE_LOW>; 217eb4ea085SAngus Ainslie (Purism) interrupt-names = "irq"; 218eb4ea085SAngus Ainslie (Purism) rohm,reset-snvs-powered; 219eb4ea085SAngus Ainslie (Purism) 220eb4ea085SAngus Ainslie (Purism) regulators { 221eb4ea085SAngus Ainslie (Purism) buck1_reg: BUCK1 { 222eb4ea085SAngus Ainslie (Purism) regulator-name = "buck1"; 223eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 224eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 225eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 226eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 227eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <900000>; 228eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <850000>; 229eb4ea085SAngus Ainslie (Purism) rohm,dvs-suspend-voltage = <800000>; 230eb4ea085SAngus Ainslie (Purism) }; 231eb4ea085SAngus Ainslie (Purism) 232eb4ea085SAngus Ainslie (Purism) buck2_reg: BUCK2 { 233eb4ea085SAngus Ainslie (Purism) regulator-name = "buck2"; 234eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 235eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 236eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 237eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 238eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 239eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <900000>; 240eb4ea085SAngus Ainslie (Purism) }; 241eb4ea085SAngus Ainslie (Purism) 242eb4ea085SAngus Ainslie (Purism) buck3_reg: BUCK3 { 243eb4ea085SAngus Ainslie (Purism) regulator-name = "buck3"; 244eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 245eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 246eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 247eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 248eb4ea085SAngus Ainslie (Purism) }; 249eb4ea085SAngus Ainslie (Purism) 250eb4ea085SAngus Ainslie (Purism) buck4_reg: BUCK4 { 251eb4ea085SAngus Ainslie (Purism) regulator-name = "buck4"; 252eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 253eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 254eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 255eb4ea085SAngus Ainslie (Purism) }; 256eb4ea085SAngus Ainslie (Purism) 257eb4ea085SAngus Ainslie (Purism) buck5_reg: BUCK5 { 258eb4ea085SAngus Ainslie (Purism) regulator-name = "buck5"; 259eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 260eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1350000>; 261eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 262eb4ea085SAngus Ainslie (Purism) }; 263eb4ea085SAngus Ainslie (Purism) 264eb4ea085SAngus Ainslie (Purism) buck6_reg: BUCK6 { 265eb4ea085SAngus Ainslie (Purism) regulator-name = "buck6"; 266eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 267eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 268eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 269eb4ea085SAngus Ainslie (Purism) }; 270eb4ea085SAngus Ainslie (Purism) 271eb4ea085SAngus Ainslie (Purism) buck7_reg: BUCK7 { 272eb4ea085SAngus Ainslie (Purism) regulator-name = "buck7"; 273eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1605000>; 274eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1995000>; 275eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 276eb4ea085SAngus Ainslie (Purism) }; 277eb4ea085SAngus Ainslie (Purism) 278eb4ea085SAngus Ainslie (Purism) buck8_reg: BUCK8 { 279eb4ea085SAngus Ainslie (Purism) regulator-name = "buck8"; 280eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <800000>; 281eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1400000>; 282eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 283eb4ea085SAngus Ainslie (Purism) }; 284eb4ea085SAngus Ainslie (Purism) 285eb4ea085SAngus Ainslie (Purism) ldo1_reg: LDO1 { 286eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo1"; 287eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 288eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 289eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 290eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 291eb4ea085SAngus Ainslie (Purism) regulator-always-on; 292eb4ea085SAngus Ainslie (Purism) }; 293eb4ea085SAngus Ainslie (Purism) 294eb4ea085SAngus Ainslie (Purism) ldo2_reg: LDO2 { 295eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo2"; 296eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 297eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <900000>; 298eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 299eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 300eb4ea085SAngus Ainslie (Purism) regulator-always-on; 301eb4ea085SAngus Ainslie (Purism) }; 302eb4ea085SAngus Ainslie (Purism) 303eb4ea085SAngus Ainslie (Purism) ldo3_reg: LDO3 { 304eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo3"; 305eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 306eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 307eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 308eb4ea085SAngus Ainslie (Purism) }; 309eb4ea085SAngus Ainslie (Purism) 310eb4ea085SAngus Ainslie (Purism) ldo4_reg: LDO4 { 311eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo4"; 312eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 313eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 314eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 315eb4ea085SAngus Ainslie (Purism) }; 316eb4ea085SAngus Ainslie (Purism) 317eb4ea085SAngus Ainslie (Purism) ldo5_reg: LDO5 { 318eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo5"; 319eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 320eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 321eb4ea085SAngus Ainslie (Purism) }; 322eb4ea085SAngus Ainslie (Purism) 323eb4ea085SAngus Ainslie (Purism) ldo6_reg: LDO6 { 324eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo6"; 325eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 326eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 327eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 328eb4ea085SAngus Ainslie (Purism) }; 329eb4ea085SAngus Ainslie (Purism) 330eb4ea085SAngus Ainslie (Purism) ldo7_reg: LDO7 { 331eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo7"; 332eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 333eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 334eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 335eb4ea085SAngus Ainslie (Purism) }; 336eb4ea085SAngus Ainslie (Purism) }; 337eb4ea085SAngus Ainslie (Purism) }; 338eb4ea085SAngus Ainslie (Purism) 339eb4ea085SAngus Ainslie (Purism) typec_ptn5100: usb_typec@52 { 340eb4ea085SAngus Ainslie (Purism) compatible = "nxp,ptn5110"; 341eb4ea085SAngus Ainslie (Purism) reg = <0x52>; 342eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 343eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_typec>; 344eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 345eb4ea085SAngus Ainslie (Purism) interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 346eb4ea085SAngus Ainslie (Purism) 347eb4ea085SAngus Ainslie (Purism) connector { 348eb4ea085SAngus Ainslie (Purism) compatible = "usb-c-connector"; 349eb4ea085SAngus Ainslie (Purism) label = "USB-C"; 350eb4ea085SAngus Ainslie (Purism) data-role = "dual"; 351eb4ea085SAngus Ainslie (Purism) power-role = "dual"; 352eb4ea085SAngus Ainslie (Purism) try-power-role = "sink"; 353eb4ea085SAngus Ainslie (Purism) source-pdos = <PDO_FIXED(5000, 2000, 354eb4ea085SAngus Ainslie (Purism) PDO_FIXED_USB_COMM | 355eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 356eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP )>; 357eb4ea085SAngus Ainslie (Purism) sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM | 358eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 359eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP ) 3608155b786SAngus Ainslie (Purism) PDO_VAR(5000, 3000, 3000)>; 361eb4ea085SAngus Ainslie (Purism) op-sink-microwatt = <10000000>; 362eb4ea085SAngus Ainslie (Purism) 363eb4ea085SAngus Ainslie (Purism) ports { 364eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 365eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 366eb4ea085SAngus Ainslie (Purism) 367eb4ea085SAngus Ainslie (Purism) port@0 { 368eb4ea085SAngus Ainslie (Purism) reg = <0>; 369eb4ea085SAngus Ainslie (Purism) 370eb4ea085SAngus Ainslie (Purism) usb_con_hs: endpoint { 371eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_hs>; 372eb4ea085SAngus Ainslie (Purism) }; 373eb4ea085SAngus Ainslie (Purism) }; 374eb4ea085SAngus Ainslie (Purism) 375eb4ea085SAngus Ainslie (Purism) port@1 { 376eb4ea085SAngus Ainslie (Purism) reg = <1>; 377eb4ea085SAngus Ainslie (Purism) 378eb4ea085SAngus Ainslie (Purism) usb_con_ss: endpoint { 379eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_ss>; 380eb4ea085SAngus Ainslie (Purism) }; 381eb4ea085SAngus Ainslie (Purism) }; 382eb4ea085SAngus Ainslie (Purism) }; 383eb4ea085SAngus Ainslie (Purism) }; 384eb4ea085SAngus Ainslie (Purism) }; 385eb4ea085SAngus Ainslie (Purism) 386eb4ea085SAngus Ainslie (Purism) rtc@68 { 387eb4ea085SAngus Ainslie (Purism) compatible = "microcrystal,rv4162"; 388eb4ea085SAngus Ainslie (Purism) reg = <0x68>; 389eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 390eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_rtc>; 391eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio4>; 392eb4ea085SAngus Ainslie (Purism) interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 393eb4ea085SAngus Ainslie (Purism) }; 394eb4ea085SAngus Ainslie (Purism) 395eb4ea085SAngus Ainslie (Purism) charger@6b { /* bq25896 */ 396eb4ea085SAngus Ainslie (Purism) compatible = "ti,bq25890"; 397eb4ea085SAngus Ainslie (Purism) reg = <0x6b>; 398eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 399eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_charger>; 400eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 401eb4ea085SAngus Ainslie (Purism) interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 402eb4ea085SAngus Ainslie (Purism) ti,battery-regulation-voltage = <4192000>; /* 4.192V */ 403eb4ea085SAngus Ainslie (Purism) ti,charge-current = <1600000>; /* 1.6A */ 404eb4ea085SAngus Ainslie (Purism) ti,termination-current = <66000>; /* 66mA */ 405eb4ea085SAngus Ainslie (Purism) ti,precharge-current = <130000>; /* 130mA */ 406eb4ea085SAngus Ainslie (Purism) ti,minimum-sys-voltage = <3000000>; /* 3V */ 407eb4ea085SAngus Ainslie (Purism) ti,boost-voltage = <5000000>; /* 5V */ 408eb4ea085SAngus Ainslie (Purism) ti,boost-max-current = <50000>; /* 50mA */ 409eb4ea085SAngus Ainslie (Purism) }; 410eb4ea085SAngus Ainslie (Purism)}; 411eb4ea085SAngus Ainslie (Purism) 412eb4ea085SAngus Ainslie (Purism)&i2c3 { 413eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 414eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 415eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c3>; 416eb4ea085SAngus Ainslie (Purism) status = "okay"; 417eb4ea085SAngus Ainslie (Purism) 418eb4ea085SAngus Ainslie (Purism) magnetometer@1e { 419eb4ea085SAngus Ainslie (Purism) compatible = "st,lsm9ds1-magn"; 420eb4ea085SAngus Ainslie (Purism) reg = <0x1e>; 421eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 422eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_imu>; 423eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 424106f7b3bSAngus Ainslie (Purism) interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 425eb4ea085SAngus Ainslie (Purism) vdd-supply = <®_3v3_p>; 426eb4ea085SAngus Ainslie (Purism) vddio-supply = <®_3v3_p>; 427eb4ea085SAngus Ainslie (Purism) }; 428eb4ea085SAngus Ainslie (Purism) 429eb4ea085SAngus Ainslie (Purism) touchscreen@5d { 430eb4ea085SAngus Ainslie (Purism) compatible = "goodix,gt5688"; 431eb4ea085SAngus Ainslie (Purism) reg = <0x5d>; 432eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 433eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_ts>; 434eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 435eb4ea085SAngus Ainslie (Purism) interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 436eb4ea085SAngus Ainslie (Purism) reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 437eb4ea085SAngus Ainslie (Purism) irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 438eb4ea085SAngus Ainslie (Purism) touchscreen-size-x = <720>; 439eb4ea085SAngus Ainslie (Purism) touchscreen-size-y = <1440>; 440eb4ea085SAngus Ainslie (Purism) AVDD28-supply = <®_2v8_p>; 441eb4ea085SAngus Ainslie (Purism) VDDIO-supply = <®_1v8_p>; 442eb4ea085SAngus Ainslie (Purism) }; 443537c00e3SMartin Kepplinger 444ea38ca9aSGuido Günther proximity-sensor@60 { 445ea38ca9aSGuido Günther compatible = "vishay,vcnl4040"; 446ea38ca9aSGuido Günther reg = <0x60>; 447ea38ca9aSGuido Günther pinctrl-0 = <&pinctrl_prox>; 448ea38ca9aSGuido Günther }; 449ea38ca9aSGuido Günther 450537c00e3SMartin Kepplinger accel-gyro@6a { 451537c00e3SMartin Kepplinger compatible = "st,lsm9ds1-imu"; 452537c00e3SMartin Kepplinger reg = <0x6a>; 453537c00e3SMartin Kepplinger vdd-supply = <®_3v3_p>; 454537c00e3SMartin Kepplinger vddio-supply = <®_3v3_p>; 455537c00e3SMartin Kepplinger }; 456eb4ea085SAngus Ainslie (Purism)}; 457eb4ea085SAngus Ainslie (Purism) 458eb4ea085SAngus Ainslie (Purism)&iomuxc { 459eb4ea085SAngus Ainslie (Purism) pinctrl_bl: blgrp { 460eb4ea085SAngus Ainslie (Purism) fsl,pins = < 461eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */ 462eb4ea085SAngus Ainslie (Purism) >; 463eb4ea085SAngus Ainslie (Purism) }; 464eb4ea085SAngus Ainslie (Purism) 465eb4ea085SAngus Ainslie (Purism) pinctrl_bt: btgrp { 466eb4ea085SAngus Ainslie (Purism) fsl,pins = < 467eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */ 468eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */ 469eb4ea085SAngus Ainslie (Purism) >; 470eb4ea085SAngus Ainslie (Purism) }; 471eb4ea085SAngus Ainslie (Purism) 472eb4ea085SAngus Ainslie (Purism) pinctrl_charger: chargergrp { 473eb4ea085SAngus Ainslie (Purism) fsl,pins = < 474eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */ 475eb4ea085SAngus Ainslie (Purism) >; 476eb4ea085SAngus Ainslie (Purism) }; 477eb4ea085SAngus Ainslie (Purism) 478eb4ea085SAngus Ainslie (Purism) pinctrl_fec1: fec1grp { 479eb4ea085SAngus Ainslie (Purism) fsl,pins = < 480eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 481eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 482eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 483eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 484eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 485eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 486eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 487eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 488eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 489eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 490eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 491eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 492eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 493eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 494eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 495eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f 496eb4ea085SAngus Ainslie (Purism) >; 497eb4ea085SAngus Ainslie (Purism) }; 498eb4ea085SAngus Ainslie (Purism) 499eb4ea085SAngus Ainslie (Purism) pinctrl_ts: tsgrp { 500eb4ea085SAngus Ainslie (Purism) fsl,pins = < 501eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */ 502eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ 503eb4ea085SAngus Ainslie (Purism) >; 504eb4ea085SAngus Ainslie (Purism) }; 505eb4ea085SAngus Ainslie (Purism) 506eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_leds: gpioledgrp { 507eb4ea085SAngus Ainslie (Purism) fsl,pins = < 508eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 509eb4ea085SAngus Ainslie (Purism) >; 510eb4ea085SAngus Ainslie (Purism) }; 511eb4ea085SAngus Ainslie (Purism) 512eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_keys: gpiokeygrp { 513eb4ea085SAngus Ainslie (Purism) fsl,pins = < 514eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 515eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16 516eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */ 517eb4ea085SAngus Ainslie (Purism) >; 518eb4ea085SAngus Ainslie (Purism) }; 519eb4ea085SAngus Ainslie (Purism) 520eb4ea085SAngus Ainslie (Purism) pinctrl_haptic: hapticgrp { 521eb4ea085SAngus Ainslie (Purism) fsl,pins = < 522eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ 523eb4ea085SAngus Ainslie (Purism) >; 524eb4ea085SAngus Ainslie (Purism) }; 525eb4ea085SAngus Ainslie (Purism) 526eb4ea085SAngus Ainslie (Purism) pinctrl_i2c1: i2c1grp { 527eb4ea085SAngus Ainslie (Purism) fsl,pins = < 528eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f 529eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f 530eb4ea085SAngus Ainslie (Purism) >; 531eb4ea085SAngus Ainslie (Purism) }; 532eb4ea085SAngus Ainslie (Purism) 533eb4ea085SAngus Ainslie (Purism) pinctrl_i2c3: i2c3grp { 534eb4ea085SAngus Ainslie (Purism) fsl,pins = < 535eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f 536eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f 537eb4ea085SAngus Ainslie (Purism) >; 538eb4ea085SAngus Ainslie (Purism) }; 539eb4ea085SAngus Ainslie (Purism) 540eb4ea085SAngus Ainslie (Purism) pinctrl_imu: imugrp { 541eb4ea085SAngus Ainslie (Purism) fsl,pins = < 542eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */ 543eb4ea085SAngus Ainslie (Purism) >; 544eb4ea085SAngus Ainslie (Purism) }; 545eb4ea085SAngus Ainslie (Purism) 546eb4ea085SAngus Ainslie (Purism) pinctrl_pmic: pmicgrp { 547eb4ea085SAngus Ainslie (Purism) fsl,pins = < 548eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */ 549eb4ea085SAngus Ainslie (Purism) >; 550eb4ea085SAngus Ainslie (Purism) }; 551eb4ea085SAngus Ainslie (Purism) 552ea38ca9aSGuido Günther pinctrl_prox: proxgrp { 553ea38ca9aSGuido Günther fsl,pins = < 554ea38ca9aSGuido Günther MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */ 555ea38ca9aSGuido Günther >; 556ea38ca9aSGuido Günther }; 557ea38ca9aSGuido Günther 558eb4ea085SAngus Ainslie (Purism) pinctrl_pwr_en: pwrengrp { 559eb4ea085SAngus Ainslie (Purism) fsl,pins = < 560eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06 561eb4ea085SAngus Ainslie (Purism) >; 562eb4ea085SAngus Ainslie (Purism) }; 563eb4ea085SAngus Ainslie (Purism) 564eb4ea085SAngus Ainslie (Purism) pinctrl_rtc: rtcgrp { 565eb4ea085SAngus Ainslie (Purism) fsl,pins = < 566eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */ 567eb4ea085SAngus Ainslie (Purism) >; 568eb4ea085SAngus Ainslie (Purism) }; 569eb4ea085SAngus Ainslie (Purism) 570eb4ea085SAngus Ainslie (Purism) pinctrl_typec: typecgrp { 571eb4ea085SAngus Ainslie (Purism) fsl,pins = < 572eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 573eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80 574eb4ea085SAngus Ainslie (Purism) >; 575eb4ea085SAngus Ainslie (Purism) }; 576eb4ea085SAngus Ainslie (Purism) 577eb4ea085SAngus Ainslie (Purism) pinctrl_uart1: uart1grp { 578eb4ea085SAngus Ainslie (Purism) fsl,pins = < 579eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 580eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 581eb4ea085SAngus Ainslie (Purism) >; 582eb4ea085SAngus Ainslie (Purism) }; 583eb4ea085SAngus Ainslie (Purism) 584eb4ea085SAngus Ainslie (Purism) pinctrl_uart2: uart2grp { 585eb4ea085SAngus Ainslie (Purism) fsl,pins = < 586eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 587eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 588eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 589eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 590eb4ea085SAngus Ainslie (Purism) >; 591eb4ea085SAngus Ainslie (Purism) }; 592eb4ea085SAngus Ainslie (Purism) 593eb4ea085SAngus Ainslie (Purism) pinctrl_uart3: uart3grp { 594eb4ea085SAngus Ainslie (Purism) fsl,pins = < 595eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 596eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 597eb4ea085SAngus Ainslie (Purism) >; 598eb4ea085SAngus Ainslie (Purism) }; 599eb4ea085SAngus Ainslie (Purism) 600eb4ea085SAngus Ainslie (Purism) pinctrl_uart4: uart4grp { 601eb4ea085SAngus Ainslie (Purism) fsl,pins = < 602eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 603eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 604eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 605eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 606eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49 607eb4ea085SAngus Ainslie (Purism) >; 608eb4ea085SAngus Ainslie (Purism) }; 609eb4ea085SAngus Ainslie (Purism) 610eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc1: usdhc1grp { 611eb4ea085SAngus Ainslie (Purism) fsl,pins = < 612eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 613eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 614eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 615eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 616eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 617eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 618eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 619eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 620eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 621eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 622eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 623eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 624eb4ea085SAngus Ainslie (Purism) >; 625eb4ea085SAngus Ainslie (Purism) }; 626eb4ea085SAngus Ainslie (Purism) 627eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 628eb4ea085SAngus Ainslie (Purism) fsl,pins = < 629eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 630eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 631eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 632eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 633eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 634eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 635eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 636eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 637eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 638eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 639eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 640eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 641eb4ea085SAngus Ainslie (Purism) >; 642eb4ea085SAngus Ainslie (Purism) }; 643eb4ea085SAngus Ainslie (Purism) 644eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 645eb4ea085SAngus Ainslie (Purism) fsl,pins = < 646eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 647eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 648eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 649eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 650eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 651eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 652eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 653eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 654eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 655eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 656eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 657eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 658eb4ea085SAngus Ainslie (Purism) >; 659eb4ea085SAngus Ainslie (Purism) }; 660eb4ea085SAngus Ainslie (Purism) 661eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2_pwr: usdhc2grppwr { 662eb4ea085SAngus Ainslie (Purism) fsl,pins = < 663eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 664eb4ea085SAngus Ainslie (Purism) >; 665eb4ea085SAngus Ainslie (Purism) }; 666eb4ea085SAngus Ainslie (Purism) 667eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2_gpio: usdhc2grpgpio { 668eb4ea085SAngus Ainslie (Purism) fsl,pins = < 669eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ 670eb4ea085SAngus Ainslie (Purism) >; 671eb4ea085SAngus Ainslie (Purism) }; 672eb4ea085SAngus Ainslie (Purism) 673eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2: usdhc2grp { 674eb4ea085SAngus Ainslie (Purism) fsl,pins = < 675eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 676eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 677eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 678eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 679eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 680eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 681eb4ea085SAngus Ainslie (Purism) >; 682eb4ea085SAngus Ainslie (Purism) }; 683eb4ea085SAngus Ainslie (Purism) 684eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 685eb4ea085SAngus Ainslie (Purism) fsl,pins = < 686eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 687eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 688eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 689eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 690eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 691eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 692eb4ea085SAngus Ainslie (Purism) >; 693eb4ea085SAngus Ainslie (Purism) }; 694eb4ea085SAngus Ainslie (Purism) 695eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 696eb4ea085SAngus Ainslie (Purism) fsl,pins = < 697eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 698eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf 699eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf 700eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf 701eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf 702eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf 703eb4ea085SAngus Ainslie (Purism) >; 704eb4ea085SAngus Ainslie (Purism) }; 705eb4ea085SAngus Ainslie (Purism) 706eb4ea085SAngus Ainslie (Purism) pinctrl_wdog: wdoggrp { 707eb4ea085SAngus Ainslie (Purism) fsl,pins = < 708eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 709eb4ea085SAngus Ainslie (Purism) >; 710eb4ea085SAngus Ainslie (Purism) }; 711eb4ea085SAngus Ainslie (Purism) 712eb4ea085SAngus Ainslie (Purism) pinctrl_wifi_pwr_en: wifipwrengrp { 713eb4ea085SAngus Ainslie (Purism) fsl,pins = < 714eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 715eb4ea085SAngus Ainslie (Purism) >; 716eb4ea085SAngus Ainslie (Purism) }; 717eb4ea085SAngus Ainslie (Purism) 718eb4ea085SAngus Ainslie (Purism) pinctrl_wwan: wwangrp { 719eb4ea085SAngus Ainslie (Purism) fsl,pins = < 720eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */ 721eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ 722eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */ 723eb4ea085SAngus Ainslie (Purism) >; 724eb4ea085SAngus Ainslie (Purism) }; 725eb4ea085SAngus Ainslie (Purism)}; 726eb4ea085SAngus Ainslie (Purism) 727eb4ea085SAngus Ainslie (Purism)&pgc_gpu { 728eb4ea085SAngus Ainslie (Purism) power-supply = <&buck3_reg>; 729eb4ea085SAngus Ainslie (Purism)}; 730eb4ea085SAngus Ainslie (Purism) 731eb4ea085SAngus Ainslie (Purism)&pgc_vpu { 732eb4ea085SAngus Ainslie (Purism) power-supply = <&buck4_reg>; 733eb4ea085SAngus Ainslie (Purism)}; 734eb4ea085SAngus Ainslie (Purism) 735eb4ea085SAngus Ainslie (Purism)&pwm1 { 736eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 737eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_bl>; 738eb4ea085SAngus Ainslie (Purism) status = "okay"; 739eb4ea085SAngus Ainslie (Purism)}; 740eb4ea085SAngus Ainslie (Purism) 74101407158SAngus Ainslie (Purism)&snvs_pwrkey { 74201407158SAngus Ainslie (Purism) status = "okay"; 74301407158SAngus Ainslie (Purism)}; 744eb4ea085SAngus Ainslie (Purism) 745eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */ 746eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 747eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart1>; 748eb4ea085SAngus Ainslie (Purism) status = "okay"; 749eb4ea085SAngus Ainslie (Purism)}; 750eb4ea085SAngus Ainslie (Purism) 751eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */ 752eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 753eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart3>; 754eb4ea085SAngus Ainslie (Purism) status = "okay"; 755eb4ea085SAngus Ainslie (Purism)}; 756eb4ea085SAngus Ainslie (Purism) 757eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */ 758eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 759eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; 760eb4ea085SAngus Ainslie (Purism) uart-has-rtscts; 761eb4ea085SAngus Ainslie (Purism) status = "okay"; 762eb4ea085SAngus Ainslie (Purism)}; 763eb4ea085SAngus Ainslie (Purism) 764eb4ea085SAngus Ainslie (Purism)&usb3_phy0 { 765dde061b8SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 766eb4ea085SAngus Ainslie (Purism) status = "okay"; 767eb4ea085SAngus Ainslie (Purism)}; 768eb4ea085SAngus Ainslie (Purism) 769eb4ea085SAngus Ainslie (Purism)&usb3_phy1 { 770eb4ea085SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 771eb4ea085SAngus Ainslie (Purism) status = "okay"; 772eb4ea085SAngus Ainslie (Purism)}; 773eb4ea085SAngus Ainslie (Purism) 774eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 { 775eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 776eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 777eb4ea085SAngus Ainslie (Purism) dr_mode = "otg"; 778eb4ea085SAngus Ainslie (Purism) status = "okay"; 779eb4ea085SAngus Ainslie (Purism) 780eb4ea085SAngus Ainslie (Purism) port@0 { 781eb4ea085SAngus Ainslie (Purism) reg = <0>; 782eb4ea085SAngus Ainslie (Purism) 783eb4ea085SAngus Ainslie (Purism) typec_hs: endpoint { 784eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_hs>; 785eb4ea085SAngus Ainslie (Purism) }; 786eb4ea085SAngus Ainslie (Purism) }; 787eb4ea085SAngus Ainslie (Purism) 788eb4ea085SAngus Ainslie (Purism) port@1 { 789eb4ea085SAngus Ainslie (Purism) reg = <1>; 790eb4ea085SAngus Ainslie (Purism) 791eb4ea085SAngus Ainslie (Purism) typec_ss: endpoint { 792eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_ss>; 793eb4ea085SAngus Ainslie (Purism) }; 794eb4ea085SAngus Ainslie (Purism) }; 795eb4ea085SAngus Ainslie (Purism)}; 796eb4ea085SAngus Ainslie (Purism) 797eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 { 798eb4ea085SAngus Ainslie (Purism) dr_mode = "host"; 799eb4ea085SAngus Ainslie (Purism) status = "okay"; 800eb4ea085SAngus Ainslie (Purism)}; 801eb4ea085SAngus Ainslie (Purism) 802eb4ea085SAngus Ainslie (Purism)&usdhc1 { 803e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 804e045f044SAnson Huang assigned-clock-rates = <400000000>; 805eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 806eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc1>; 807eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 808eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 809eb4ea085SAngus Ainslie (Purism) bus-width = <8>; 810eb4ea085SAngus Ainslie (Purism) non-removable; 811eb4ea085SAngus Ainslie (Purism) status = "okay"; 812eb4ea085SAngus Ainslie (Purism)}; 813eb4ea085SAngus Ainslie (Purism) 814eb4ea085SAngus Ainslie (Purism)&usdhc2 { 815e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 816e045f044SAnson Huang assigned-clock-rates = <200000000>; 817eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 818eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2>; 819eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 820eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 821eb4ea085SAngus Ainslie (Purism) bus-width = <4>; 822eb4ea085SAngus Ainslie (Purism) vmmc-supply = <®_usdhc2_vmmc>; 823eb4ea085SAngus Ainslie (Purism) power-supply = <&wifi_pwr_en>; 824eb4ea085SAngus Ainslie (Purism) non-removable; 825eb4ea085SAngus Ainslie (Purism) disable-wp; 826eb4ea085SAngus Ainslie (Purism) cap-sdio-irq; 827eb4ea085SAngus Ainslie (Purism) keep-power-in-suspend; 828eb4ea085SAngus Ainslie (Purism) wakeup-source; 829eb4ea085SAngus Ainslie (Purism) status = "okay"; 830eb4ea085SAngus Ainslie (Purism)}; 831eb4ea085SAngus Ainslie (Purism) 832eb4ea085SAngus Ainslie (Purism)&wdog1 { 833eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 834eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wdog>; 835eb4ea085SAngus Ainslie (Purism) fsl,ext-reset-output; 836eb4ea085SAngus Ainslie (Purism) status = "okay"; 837eb4ea085SAngus Ainslie (Purism)}; 838