1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+ 2eb4ea085SAngus Ainslie (Purism)/* 3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC 4eb4ea085SAngus Ainslie (Purism) */ 5eb4ea085SAngus Ainslie (Purism) 6eb4ea085SAngus Ainslie (Purism)/dts-v1/; 7eb4ea085SAngus Ainslie (Purism) 8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h" 9d8fa4792SKrzysztof Kozlowski#include <dt-bindings/interrupt-controller/irq.h> 10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h" 11eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h" 12eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi" 13eb4ea085SAngus Ainslie (Purism) 14eb4ea085SAngus Ainslie (Purism)/ { 15eb4ea085SAngus Ainslie (Purism) model = "Purism Librem 5 devkit"; 16eb4ea085SAngus Ainslie (Purism) compatible = "purism,librem5-devkit", "fsl,imx8mq"; 17eb4ea085SAngus Ainslie (Purism) 18eb4ea085SAngus Ainslie (Purism) backlight_dsi: backlight-dsi { 19eb4ea085SAngus Ainslie (Purism) compatible = "pwm-backlight"; 20eb4ea085SAngus Ainslie (Purism) /* 200 Hz for the PAM2841 */ 21eb4ea085SAngus Ainslie (Purism) pwms = <&pwm1 0 5000000>; 22eb4ea085SAngus Ainslie (Purism) brightness-levels = <0 100>; 23eb4ea085SAngus Ainslie (Purism) num-interpolated-steps = <100>; 24eb4ea085SAngus Ainslie (Purism) /* Default brightness level (index into the array defined by */ 25eb4ea085SAngus Ainslie (Purism) /* the "brightness-levels" property) */ 26eb4ea085SAngus Ainslie (Purism) default-brightness-level = <0>; 27eb4ea085SAngus Ainslie (Purism) power-supply = <®_22v4_p>; 28eb4ea085SAngus Ainslie (Purism) }; 29eb4ea085SAngus Ainslie (Purism) 30eb4ea085SAngus Ainslie (Purism) chosen { 31eb4ea085SAngus Ainslie (Purism) stdout-path = &uart1; 32eb4ea085SAngus Ainslie (Purism) }; 33eb4ea085SAngus Ainslie (Purism) 34eb4ea085SAngus Ainslie (Purism) gpio-keys { 35eb4ea085SAngus Ainslie (Purism) compatible = "gpio-keys"; 36eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 37eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_keys>; 38eb4ea085SAngus Ainslie (Purism) 39eb4ea085SAngus Ainslie (Purism) btn1 { 40eb4ea085SAngus Ainslie (Purism) label = "VOL_UP"; 41eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 42eb4ea085SAngus Ainslie (Purism) wakeup-source; 43eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEUP>; 44eb4ea085SAngus Ainslie (Purism) }; 45eb4ea085SAngus Ainslie (Purism) 46eb4ea085SAngus Ainslie (Purism) btn2 { 47eb4ea085SAngus Ainslie (Purism) label = "VOL_DOWN"; 48eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 49eb4ea085SAngus Ainslie (Purism) wakeup-source; 50eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEDOWN>; 51eb4ea085SAngus Ainslie (Purism) }; 52eb4ea085SAngus Ainslie (Purism) 533ef506b3SAngus Ainslie (Purism) wwan-wake { 543ef506b3SAngus Ainslie (Purism) label = "WWAN_WAKE"; 553ef506b3SAngus Ainslie (Purism) gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; 563ef506b3SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 57d8fa4792SKrzysztof Kozlowski interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 583ef506b3SAngus Ainslie (Purism) wakeup-source; 593ef506b3SAngus Ainslie (Purism) linux,code = <KEY_PHONE>; 603ef506b3SAngus Ainslie (Purism) }; 61eb4ea085SAngus Ainslie (Purism) }; 62eb4ea085SAngus Ainslie (Purism) 63eb4ea085SAngus Ainslie (Purism) leds { 64eb4ea085SAngus Ainslie (Purism) compatible = "gpio-leds"; 65eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 66eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_leds>; 67eb4ea085SAngus Ainslie (Purism) 68eb4ea085SAngus Ainslie (Purism) led1 { 69eb4ea085SAngus Ainslie (Purism) label = "LED 1"; 70eb4ea085SAngus Ainslie (Purism) gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 71eb4ea085SAngus Ainslie (Purism) default-state = "off"; 72eb4ea085SAngus Ainslie (Purism) }; 73eb4ea085SAngus Ainslie (Purism) }; 74eb4ea085SAngus Ainslie (Purism) 75eb4ea085SAngus Ainslie (Purism) pmic_osc: clock-pmic { 76eb4ea085SAngus Ainslie (Purism) compatible = "fixed-clock"; 77eb4ea085SAngus Ainslie (Purism) #clock-cells = <0>; 78eb4ea085SAngus Ainslie (Purism) clock-frequency = <32768>; 79eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_osc"; 80eb4ea085SAngus Ainslie (Purism) }; 81eb4ea085SAngus Ainslie (Purism) 82eb4ea085SAngus Ainslie (Purism) reg_1v8_p: regulator-1v8-p { 83eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 84eb4ea085SAngus Ainslie (Purism) regulator-name = "1v8_p"; 85eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 86eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 87eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 88eb4ea085SAngus Ainslie (Purism) }; 89eb4ea085SAngus Ainslie (Purism) 90eb4ea085SAngus Ainslie (Purism) reg_2v8_p: regulator-2v8-p { 91eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 92eb4ea085SAngus Ainslie (Purism) regulator-name = "2v8_p"; 93eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <2800000>; 94eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <2800000>; 95eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 96eb4ea085SAngus Ainslie (Purism) }; 97eb4ea085SAngus Ainslie (Purism) 98eb4ea085SAngus Ainslie (Purism) reg_3v3_p: regulator-3v3-p { 99eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 100eb4ea085SAngus Ainslie (Purism) regulator-name = "3v3_p"; 101eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 102eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 103eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 104eb4ea085SAngus Ainslie (Purism) 105eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 106eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 107eb4ea085SAngus Ainslie (Purism) }; 108eb4ea085SAngus Ainslie (Purism) }; 109eb4ea085SAngus Ainslie (Purism) 110eb4ea085SAngus Ainslie (Purism) reg_5v_p: regulator-5v-p { 111eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 112eb4ea085SAngus Ainslie (Purism) regulator-name = "5v_p"; 113eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <5000000>; 114eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <5000000>; 115eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 116eb4ea085SAngus Ainslie (Purism) 117eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 118eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 119eb4ea085SAngus Ainslie (Purism) }; 120eb4ea085SAngus Ainslie (Purism) }; 121eb4ea085SAngus Ainslie (Purism) 122eb4ea085SAngus Ainslie (Purism) reg_22v4_p: regulator-22v4-p { 123eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 124eb4ea085SAngus Ainslie (Purism) regulator-name = "22v4_P"; 125eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <22400000>; 126eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <22400000>; 127eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 128eb4ea085SAngus Ainslie (Purism) }; 129eb4ea085SAngus Ainslie (Purism) 130eb4ea085SAngus Ainslie (Purism) reg_pwr_en: regulator-pwr-en { 131eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 132eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 133eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pwr_en>; 134eb4ea085SAngus Ainslie (Purism) regulator-name = "PWR_EN"; 135eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 136eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 137eb4ea085SAngus Ainslie (Purism) gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 138eb4ea085SAngus Ainslie (Purism) enable-active-high; 139eb4ea085SAngus Ainslie (Purism) regulator-always-on; 140eb4ea085SAngus Ainslie (Purism) }; 141eb4ea085SAngus Ainslie (Purism) 142eb4ea085SAngus Ainslie (Purism) reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 143eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 144eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 145eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2_pwr>; 146eb4ea085SAngus Ainslie (Purism) regulator-name = "VSD_3V3"; 147eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 148eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 149eb4ea085SAngus Ainslie (Purism) gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 150eb4ea085SAngus Ainslie (Purism) enable-active-high; 151eb4ea085SAngus Ainslie (Purism) regulator-always-on; 152eb4ea085SAngus Ainslie (Purism) }; 153eb4ea085SAngus Ainslie (Purism) 1547f7b7997SAngus Ainslie (Purism) wwan_codec: sound-wwan-codec { 1557f7b7997SAngus Ainslie (Purism) compatible = "option,gtm601"; 1567f7b7997SAngus Ainslie (Purism) #sound-dai-cells = <0>; 1577f7b7997SAngus Ainslie (Purism) }; 1587f7b7997SAngus Ainslie (Purism) 15915094482SGuido Günther mic_mux: mic-mux { 16015094482SGuido Günther compatible = "simple-audio-mux"; 16115094482SGuido Günther pinctrl-names = "default"; 16215094482SGuido Günther pinctrl-0 = <&pinctrl_micsel>; 16315094482SGuido Günther mux-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; 16415094482SGuido Günther sound-name-prefix = "Mic Mux"; 16515094482SGuido Günther }; 16615094482SGuido Günther 167c53f0166SAngus Ainslie (Purism) sound { 168c53f0166SAngus Ainslie (Purism) compatible = "simple-audio-card"; 169*d779f4c9SGuido Günther pinctrl-names = "default"; 170*d779f4c9SGuido Günther pinctrl-0 = <&pinctrl_hpdet>; 17115094482SGuido Günther simple-audio-card,aux-devs = <&speaker_amp>, <&mic_mux>; 1725b65f39dSGuido Günther simple-audio-card,name = "Librem 5 Devkit"; 173c53f0166SAngus Ainslie (Purism) simple-audio-card,format = "i2s"; 174c53f0166SAngus Ainslie (Purism) simple-audio-card,widgets = 17515094482SGuido Günther "Microphone", "Builtin Microphone", 17615094482SGuido Günther "Microphone", "Headset Microphone", 177*d779f4c9SGuido Günther "Headphone", "Headphones", 17839a346d9SGuido Günther "Speaker", "Builtin Speaker"; 179c53f0166SAngus Ainslie (Purism) simple-audio-card,routing = 18015094482SGuido Günther "MIC_IN", "Mic Mux OUT", 18115094482SGuido Günther "Mic Mux IN1", "Headset Microphone", 18215094482SGuido Günther "Mic Mux IN2", "Builtin Microphone", 18315094482SGuido Günther "Mic Mux OUT", "Mic Bias", 184*d779f4c9SGuido Günther "Headphones", "HP_OUT", 1856f46f7ffSGuido Günther "Builtin Speaker", "Speaker Amp OUTR", 1866f46f7ffSGuido Günther "Speaker Amp INR", "LINE_OUT"; 187*d779f4c9SGuido Günther simple-audio-card,hp-det-gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; 188c53f0166SAngus Ainslie (Purism) 189c53f0166SAngus Ainslie (Purism) simple-audio-card,cpu { 190c53f0166SAngus Ainslie (Purism) sound-dai = <&sai2>; 191c53f0166SAngus Ainslie (Purism) }; 192c53f0166SAngus Ainslie (Purism) 193c53f0166SAngus Ainslie (Purism) simple-audio-card,codec { 194c53f0166SAngus Ainslie (Purism) sound-dai = <&sgtl5000>; 195c53f0166SAngus Ainslie (Purism) clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 196c53f0166SAngus Ainslie (Purism) frame-master; 197c53f0166SAngus Ainslie (Purism) bitclock-master; 198c53f0166SAngus Ainslie (Purism) }; 199c53f0166SAngus Ainslie (Purism) }; 200c53f0166SAngus Ainslie (Purism) 2017f7b7997SAngus Ainslie (Purism) sound-wwan { 2027f7b7997SAngus Ainslie (Purism) compatible = "simple-audio-card"; 2037f7b7997SAngus Ainslie (Purism) simple-audio-card,name = "SIMCom SIM7100"; 2047f7b7997SAngus Ainslie (Purism) simple-audio-card,format = "dsp_a"; 2057f7b7997SAngus Ainslie (Purism) 2067f7b7997SAngus Ainslie (Purism) simple-audio-card,cpu { 2077f7b7997SAngus Ainslie (Purism) sound-dai = <&sai6>; 2087f7b7997SAngus Ainslie (Purism) }; 2097f7b7997SAngus Ainslie (Purism) 2107f7b7997SAngus Ainslie (Purism) telephony_link_master: simple-audio-card,codec { 2117f7b7997SAngus Ainslie (Purism) sound-dai = <&wwan_codec>; 2127f7b7997SAngus Ainslie (Purism) frame-master; 2137f7b7997SAngus Ainslie (Purism) bitclock-master; 2147f7b7997SAngus Ainslie (Purism) }; 2157f7b7997SAngus Ainslie (Purism) }; 2167f7b7997SAngus Ainslie (Purism) 2176f46f7ffSGuido Günther speaker_amp: speaker-amp { 2186f46f7ffSGuido Günther compatible = "simple-audio-amplifier"; 2196f46f7ffSGuido Günther pinctrl-names = "default"; 2206f46f7ffSGuido Günther pinctrl-0 = <&pinctrl_spkamp>; 2216f46f7ffSGuido Günther VCC-supply = <®_3v3_p>; 2226f46f7ffSGuido Günther sound-name-prefix = "Speaker Amp"; 2236f46f7ffSGuido Günther enable-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 2246f46f7ffSGuido Günther }; 2256f46f7ffSGuido Günther 226eb4ea085SAngus Ainslie (Purism) vibrator { 227eb4ea085SAngus Ainslie (Purism) compatible = "gpio-vibrator"; 228eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 229eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_haptic>; 230eb4ea085SAngus Ainslie (Purism) enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; 231eb4ea085SAngus Ainslie (Purism) vcc-supply = <®_3v3_p>; 232eb4ea085SAngus Ainslie (Purism) }; 233eb4ea085SAngus Ainslie (Purism) 234eb4ea085SAngus Ainslie (Purism) wifi_pwr_en: regulator-wifi-en { 235eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 236eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 237eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wifi_pwr_en>; 238eb4ea085SAngus Ainslie (Purism) regulator-name = "WIFI_EN"; 239eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 240eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 241eb4ea085SAngus Ainslie (Purism) gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 242eb4ea085SAngus Ainslie (Purism) enable-active-high; 243eb4ea085SAngus Ainslie (Purism) regulator-always-on; 244eb4ea085SAngus Ainslie (Purism) }; 245eb4ea085SAngus Ainslie (Purism)}; 246eb4ea085SAngus Ainslie (Purism) 247a2e47ba2SAngus Ainslie (Purism)&A53_0 { 248a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 249a2e47ba2SAngus Ainslie (Purism)}; 250a2e47ba2SAngus Ainslie (Purism) 251a2e47ba2SAngus Ainslie (Purism)&A53_1 { 252a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 253a2e47ba2SAngus Ainslie (Purism)}; 254a2e47ba2SAngus Ainslie (Purism) 255a2e47ba2SAngus Ainslie (Purism)&A53_2 { 256a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 257a2e47ba2SAngus Ainslie (Purism)}; 258a2e47ba2SAngus Ainslie (Purism) 259a2e47ba2SAngus Ainslie (Purism)&A53_3 { 260a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 261a2e47ba2SAngus Ainslie (Purism)}; 262a2e47ba2SAngus Ainslie (Purism) 2639d9005a5SGuido Günther&dphy { 2649d9005a5SGuido Günther status = "okay"; 2659d9005a5SGuido Günther}; 2669d9005a5SGuido Günther 267eb4ea085SAngus Ainslie (Purism)&fec1 { 268eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 269eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_fec1>; 270eb4ea085SAngus Ainslie (Purism) phy-mode = "rgmii-id"; 271eb4ea085SAngus Ainslie (Purism) phy-handle = <ðphy0>; 272eb4ea085SAngus Ainslie (Purism) fsl,magic-packet; 273eb4ea085SAngus Ainslie (Purism) phy-supply = <®_3v3_p>; 274eb4ea085SAngus Ainslie (Purism) status = "okay"; 275eb4ea085SAngus Ainslie (Purism) 276eb4ea085SAngus Ainslie (Purism) mdio { 277eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 278eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 279eb4ea085SAngus Ainslie (Purism) 280eb4ea085SAngus Ainslie (Purism) ethphy0: ethernet-phy@1 { 281eb4ea085SAngus Ainslie (Purism) compatible = "ethernet-phy-ieee802.3-c22"; 282eb4ea085SAngus Ainslie (Purism) reg = <1>; 283eb4ea085SAngus Ainslie (Purism) }; 284eb4ea085SAngus Ainslie (Purism) }; 285eb4ea085SAngus Ainslie (Purism)}; 286eb4ea085SAngus Ainslie (Purism) 287eb4ea085SAngus Ainslie (Purism)&i2c1 { 288eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 289eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 290eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c1>; 291eb4ea085SAngus Ainslie (Purism) status = "okay"; 292eb4ea085SAngus Ainslie (Purism) 293eb4ea085SAngus Ainslie (Purism) pmic: pmic@4b { 294eb4ea085SAngus Ainslie (Purism) compatible = "rohm,bd71837"; 295eb4ea085SAngus Ainslie (Purism) reg = <0x4b>; 296eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 297eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pmic>; 298eb4ea085SAngus Ainslie (Purism) clocks = <&pmic_osc>; 299eb4ea085SAngus Ainslie (Purism) clock-names = "osc"; 300a4a3550eSKrzysztof Kozlowski #clock-cells = <0>; 301eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_clk"; 302eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio1>; 303d8fa4792SKrzysztof Kozlowski interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 304eb4ea085SAngus Ainslie (Purism) rohm,reset-snvs-powered; 305eb4ea085SAngus Ainslie (Purism) 306eb4ea085SAngus Ainslie (Purism) regulators { 307eb4ea085SAngus Ainslie (Purism) buck1_reg: BUCK1 { 308eb4ea085SAngus Ainslie (Purism) regulator-name = "buck1"; 309eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 310eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 311eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 312edb93de4SGuido Günther regulator-always-on; 313eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 314eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <900000>; 315eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <850000>; 316eb4ea085SAngus Ainslie (Purism) rohm,dvs-suspend-voltage = <800000>; 317eb4ea085SAngus Ainslie (Purism) }; 318eb4ea085SAngus Ainslie (Purism) 319eb4ea085SAngus Ainslie (Purism) buck2_reg: BUCK2 { 320eb4ea085SAngus Ainslie (Purism) regulator-name = "buck2"; 321eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 322eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 323eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 324eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 325eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 326eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <900000>; 327eb4ea085SAngus Ainslie (Purism) }; 328eb4ea085SAngus Ainslie (Purism) 329eb4ea085SAngus Ainslie (Purism) buck3_reg: BUCK3 { 330eb4ea085SAngus Ainslie (Purism) regulator-name = "buck3"; 331eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 332eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 333eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 33476eceb0fSGuido Günther rohm,dvs-run-voltage = <900000>; 335eb4ea085SAngus Ainslie (Purism) }; 336eb4ea085SAngus Ainslie (Purism) 337eb4ea085SAngus Ainslie (Purism) buck4_reg: BUCK4 { 338eb4ea085SAngus Ainslie (Purism) regulator-name = "buck4"; 339eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 340eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 341eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 342eb4ea085SAngus Ainslie (Purism) }; 343eb4ea085SAngus Ainslie (Purism) 344eb4ea085SAngus Ainslie (Purism) buck5_reg: BUCK5 { 345eb4ea085SAngus Ainslie (Purism) regulator-name = "buck5"; 346eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 347eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1350000>; 348eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 349edb93de4SGuido Günther regulator-always-on; 350eb4ea085SAngus Ainslie (Purism) }; 351eb4ea085SAngus Ainslie (Purism) 352eb4ea085SAngus Ainslie (Purism) buck6_reg: BUCK6 { 353eb4ea085SAngus Ainslie (Purism) regulator-name = "buck6"; 354eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 355eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 356eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 357edb93de4SGuido Günther regulator-always-on; 358eb4ea085SAngus Ainslie (Purism) }; 359eb4ea085SAngus Ainslie (Purism) 360eb4ea085SAngus Ainslie (Purism) buck7_reg: BUCK7 { 361eb4ea085SAngus Ainslie (Purism) regulator-name = "buck7"; 362eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1605000>; 363eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1995000>; 364eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 365edb93de4SGuido Günther regulator-always-on; 366eb4ea085SAngus Ainslie (Purism) }; 367eb4ea085SAngus Ainslie (Purism) 368eb4ea085SAngus Ainslie (Purism) buck8_reg: BUCK8 { 369eb4ea085SAngus Ainslie (Purism) regulator-name = "buck8"; 370eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <800000>; 371eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1400000>; 372eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 373edb93de4SGuido Günther regulator-always-on; 374eb4ea085SAngus Ainslie (Purism) }; 375eb4ea085SAngus Ainslie (Purism) 376eb4ea085SAngus Ainslie (Purism) ldo1_reg: LDO1 { 377eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo1"; 378eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 379eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 380eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 381eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 382eb4ea085SAngus Ainslie (Purism) regulator-always-on; 383eb4ea085SAngus Ainslie (Purism) }; 384eb4ea085SAngus Ainslie (Purism) 385eb4ea085SAngus Ainslie (Purism) ldo2_reg: LDO2 { 386eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo2"; 387eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 388eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <900000>; 389eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 390eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 391eb4ea085SAngus Ainslie (Purism) regulator-always-on; 392eb4ea085SAngus Ainslie (Purism) }; 393eb4ea085SAngus Ainslie (Purism) 394eb4ea085SAngus Ainslie (Purism) ldo3_reg: LDO3 { 395eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo3"; 396eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 397eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 398eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 399edb93de4SGuido Günther regulator-always-on; 400eb4ea085SAngus Ainslie (Purism) }; 401eb4ea085SAngus Ainslie (Purism) 402eb4ea085SAngus Ainslie (Purism) ldo4_reg: LDO4 { 403eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo4"; 404eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 405eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 406eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 407edb93de4SGuido Günther regulator-always-on; 408eb4ea085SAngus Ainslie (Purism) }; 409eb4ea085SAngus Ainslie (Purism) 410eb4ea085SAngus Ainslie (Purism) ldo5_reg: LDO5 { 411eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo5"; 412eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 413eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 414edb93de4SGuido Günther regulator-always-on; 415eb4ea085SAngus Ainslie (Purism) }; 416eb4ea085SAngus Ainslie (Purism) 417eb4ea085SAngus Ainslie (Purism) ldo6_reg: LDO6 { 418eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo6"; 419eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 420eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 421eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 422edb93de4SGuido Günther regulator-always-on; 423eb4ea085SAngus Ainslie (Purism) }; 424eb4ea085SAngus Ainslie (Purism) 425eb4ea085SAngus Ainslie (Purism) ldo7_reg: LDO7 { 426eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo7"; 427eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 428eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 429eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 430edb93de4SGuido Günther regulator-always-on; 431eb4ea085SAngus Ainslie (Purism) }; 432eb4ea085SAngus Ainslie (Purism) }; 433eb4ea085SAngus Ainslie (Purism) }; 434eb4ea085SAngus Ainslie (Purism) 4359251dad3SGuido Günther typec_ptn5100: usb-typec@52 { 436eb4ea085SAngus Ainslie (Purism) compatible = "nxp,ptn5110"; 437eb4ea085SAngus Ainslie (Purism) reg = <0x52>; 438eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 439eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_typec>; 440eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 441eb4ea085SAngus Ainslie (Purism) interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 442eb4ea085SAngus Ainslie (Purism) 443eb4ea085SAngus Ainslie (Purism) connector { 444eb4ea085SAngus Ainslie (Purism) compatible = "usb-c-connector"; 445eb4ea085SAngus Ainslie (Purism) label = "USB-C"; 446eb4ea085SAngus Ainslie (Purism) data-role = "dual"; 447eb4ea085SAngus Ainslie (Purism) power-role = "dual"; 448eb4ea085SAngus Ainslie (Purism) try-power-role = "sink"; 449eb4ea085SAngus Ainslie (Purism) source-pdos = <PDO_FIXED(5000, 2000, 450eb4ea085SAngus Ainslie (Purism) PDO_FIXED_USB_COMM | 451eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 452eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP )>; 4535369d191SAngus Ainslie (Purism) sink-pdos = <PDO_FIXED(5000, 3500, PDO_FIXED_USB_COMM | 454eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 455eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP ) 4565369d191SAngus Ainslie (Purism) PDO_VAR(5000, 5000, 3500)>; 457eb4ea085SAngus Ainslie (Purism) op-sink-microwatt = <10000000>; 458eb4ea085SAngus Ainslie (Purism) 459eb4ea085SAngus Ainslie (Purism) ports { 460eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 461eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 462eb4ea085SAngus Ainslie (Purism) 463eb4ea085SAngus Ainslie (Purism) port@0 { 464eb4ea085SAngus Ainslie (Purism) reg = <0>; 465eb4ea085SAngus Ainslie (Purism) 466eb4ea085SAngus Ainslie (Purism) usb_con_hs: endpoint { 467eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_hs>; 468eb4ea085SAngus Ainslie (Purism) }; 469eb4ea085SAngus Ainslie (Purism) }; 470eb4ea085SAngus Ainslie (Purism) 471eb4ea085SAngus Ainslie (Purism) port@1 { 472eb4ea085SAngus Ainslie (Purism) reg = <1>; 473eb4ea085SAngus Ainslie (Purism) 474eb4ea085SAngus Ainslie (Purism) usb_con_ss: endpoint { 475eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_ss>; 476eb4ea085SAngus Ainslie (Purism) }; 477eb4ea085SAngus Ainslie (Purism) }; 478eb4ea085SAngus Ainslie (Purism) }; 479eb4ea085SAngus Ainslie (Purism) }; 480eb4ea085SAngus Ainslie (Purism) }; 481eb4ea085SAngus Ainslie (Purism) 482eb4ea085SAngus Ainslie (Purism) rtc@68 { 483eb4ea085SAngus Ainslie (Purism) compatible = "microcrystal,rv4162"; 484eb4ea085SAngus Ainslie (Purism) reg = <0x68>; 485eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 486eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_rtc>; 487eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio4>; 488eb4ea085SAngus Ainslie (Purism) interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 489eb4ea085SAngus Ainslie (Purism) }; 490eb4ea085SAngus Ainslie (Purism) 491eb4ea085SAngus Ainslie (Purism) charger@6b { /* bq25896 */ 492eb4ea085SAngus Ainslie (Purism) compatible = "ti,bq25890"; 493eb4ea085SAngus Ainslie (Purism) reg = <0x6b>; 494eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 495eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_charger>; 496eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 497eb4ea085SAngus Ainslie (Purism) interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 498eb4ea085SAngus Ainslie (Purism) ti,battery-regulation-voltage = <4192000>; /* 4.192V */ 499eb4ea085SAngus Ainslie (Purism) ti,charge-current = <1600000>; /* 1.6A */ 500eb4ea085SAngus Ainslie (Purism) ti,termination-current = <66000>; /* 66mA */ 501eb4ea085SAngus Ainslie (Purism) ti,precharge-current = <130000>; /* 130mA */ 502eb4ea085SAngus Ainslie (Purism) ti,minimum-sys-voltage = <3000000>; /* 3V */ 503eb4ea085SAngus Ainslie (Purism) ti,boost-voltage = <5000000>; /* 5V */ 504eb4ea085SAngus Ainslie (Purism) ti,boost-max-current = <50000>; /* 50mA */ 505eb4ea085SAngus Ainslie (Purism) }; 506eb4ea085SAngus Ainslie (Purism)}; 507eb4ea085SAngus Ainslie (Purism) 508eb4ea085SAngus Ainslie (Purism)&i2c3 { 509eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 510eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 511eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c3>; 512eb4ea085SAngus Ainslie (Purism) status = "okay"; 513eb4ea085SAngus Ainslie (Purism) 514eb4ea085SAngus Ainslie (Purism) magnetometer@1e { 515eb4ea085SAngus Ainslie (Purism) compatible = "st,lsm9ds1-magn"; 516eb4ea085SAngus Ainslie (Purism) reg = <0x1e>; 517eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 518eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_imu>; 519eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 520106f7b3bSAngus Ainslie (Purism) interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 521eb4ea085SAngus Ainslie (Purism) vdd-supply = <®_3v3_p>; 522eb4ea085SAngus Ainslie (Purism) vddio-supply = <®_3v3_p>; 523eb4ea085SAngus Ainslie (Purism) }; 524eb4ea085SAngus Ainslie (Purism) 525c53f0166SAngus Ainslie (Purism) sgtl5000: audio-codec@a { 526c53f0166SAngus Ainslie (Purism) compatible = "fsl,sgtl5000"; 527c53f0166SAngus Ainslie (Purism) clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 528c53f0166SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 529c53f0166SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 530c53f0166SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 531c53f0166SAngus Ainslie (Purism) #sound-dai-cells = <0>; 532c53f0166SAngus Ainslie (Purism) reg = <0x0a>; 533c53f0166SAngus Ainslie (Purism) VDDD-supply = <®_1v8_p>; 534c53f0166SAngus Ainslie (Purism) VDDIO-supply = <®_3v3_p>; 535c53f0166SAngus Ainslie (Purism) VDDA-supply = <®_3v3_p>; 536c53f0166SAngus Ainslie (Purism) }; 537c53f0166SAngus Ainslie (Purism) 538eb4ea085SAngus Ainslie (Purism) touchscreen@5d { 539eb4ea085SAngus Ainslie (Purism) compatible = "goodix,gt5688"; 540eb4ea085SAngus Ainslie (Purism) reg = <0x5d>; 541eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 542eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_ts>; 543eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 544eb4ea085SAngus Ainslie (Purism) interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 545eb4ea085SAngus Ainslie (Purism) reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 546eb4ea085SAngus Ainslie (Purism) irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 547eb4ea085SAngus Ainslie (Purism) touchscreen-size-x = <720>; 548eb4ea085SAngus Ainslie (Purism) touchscreen-size-y = <1440>; 549eb4ea085SAngus Ainslie (Purism) AVDD28-supply = <®_2v8_p>; 550eb4ea085SAngus Ainslie (Purism) VDDIO-supply = <®_1v8_p>; 551eb4ea085SAngus Ainslie (Purism) }; 552537c00e3SMartin Kepplinger 553ea38ca9aSGuido Günther proximity-sensor@60 { 554ea38ca9aSGuido Günther compatible = "vishay,vcnl4040"; 555ea38ca9aSGuido Günther reg = <0x60>; 556ea38ca9aSGuido Günther pinctrl-0 = <&pinctrl_prox>; 557ea38ca9aSGuido Günther }; 558ea38ca9aSGuido Günther 559537c00e3SMartin Kepplinger accel-gyro@6a { 560537c00e3SMartin Kepplinger compatible = "st,lsm9ds1-imu"; 561537c00e3SMartin Kepplinger reg = <0x6a>; 562537c00e3SMartin Kepplinger vdd-supply = <®_3v3_p>; 563537c00e3SMartin Kepplinger vddio-supply = <®_3v3_p>; 564eef22bb1SMartin Kepplinger mount-matrix = "1", "0", "0", 565eef22bb1SMartin Kepplinger "0", "1", "0", 566eef22bb1SMartin Kepplinger "0", "0", "-1"; 567537c00e3SMartin Kepplinger }; 568eb4ea085SAngus Ainslie (Purism)}; 569eb4ea085SAngus Ainslie (Purism) 570eb4ea085SAngus Ainslie (Purism)&iomuxc { 571eb4ea085SAngus Ainslie (Purism) pinctrl_bl: blgrp { 572eb4ea085SAngus Ainslie (Purism) fsl,pins = < 573eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */ 574eb4ea085SAngus Ainslie (Purism) >; 575eb4ea085SAngus Ainslie (Purism) }; 576eb4ea085SAngus Ainslie (Purism) 577eb4ea085SAngus Ainslie (Purism) pinctrl_bt: btgrp { 578eb4ea085SAngus Ainslie (Purism) fsl,pins = < 579eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */ 580eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */ 581eb4ea085SAngus Ainslie (Purism) >; 582eb4ea085SAngus Ainslie (Purism) }; 583eb4ea085SAngus Ainslie (Purism) 584eb4ea085SAngus Ainslie (Purism) pinctrl_charger: chargergrp { 585eb4ea085SAngus Ainslie (Purism) fsl,pins = < 586eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */ 587eb4ea085SAngus Ainslie (Purism) >; 588eb4ea085SAngus Ainslie (Purism) }; 589eb4ea085SAngus Ainslie (Purism) 590eb4ea085SAngus Ainslie (Purism) pinctrl_fec1: fec1grp { 591eb4ea085SAngus Ainslie (Purism) fsl,pins = < 592eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 593eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 594eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 595eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 596eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 597eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 598eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 599eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 600eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 601eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 602eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 603eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 604eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 605eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 606eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 607eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f 608eb4ea085SAngus Ainslie (Purism) >; 609eb4ea085SAngus Ainslie (Purism) }; 610eb4ea085SAngus Ainslie (Purism) 611eb4ea085SAngus Ainslie (Purism) pinctrl_ts: tsgrp { 612eb4ea085SAngus Ainslie (Purism) fsl,pins = < 613eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */ 614eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ 615eb4ea085SAngus Ainslie (Purism) >; 616eb4ea085SAngus Ainslie (Purism) }; 617eb4ea085SAngus Ainslie (Purism) 618eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_leds: gpioledgrp { 619eb4ea085SAngus Ainslie (Purism) fsl,pins = < 620eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 621eb4ea085SAngus Ainslie (Purism) >; 622eb4ea085SAngus Ainslie (Purism) }; 623eb4ea085SAngus Ainslie (Purism) 624eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_keys: gpiokeygrp { 625eb4ea085SAngus Ainslie (Purism) fsl,pins = < 626eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 627eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16 6283ef506b3SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ 629eb4ea085SAngus Ainslie (Purism) >; 630eb4ea085SAngus Ainslie (Purism) }; 631eb4ea085SAngus Ainslie (Purism) 632eb4ea085SAngus Ainslie (Purism) pinctrl_haptic: hapticgrp { 633eb4ea085SAngus Ainslie (Purism) fsl,pins = < 634eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ 635eb4ea085SAngus Ainslie (Purism) >; 636eb4ea085SAngus Ainslie (Purism) }; 637eb4ea085SAngus Ainslie (Purism) 638*d779f4c9SGuido Günther pinctrl_hpdet: hpdetgrp { 639*d779f4c9SGuido Günther fsl,pins = < 640*d779f4c9SGuido Günther MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */ 641*d779f4c9SGuido Günther >; 642*d779f4c9SGuido Günther }; 643*d779f4c9SGuido Günther 644eb4ea085SAngus Ainslie (Purism) pinctrl_i2c1: i2c1grp { 645eb4ea085SAngus Ainslie (Purism) fsl,pins = < 646eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f 647eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f 648eb4ea085SAngus Ainslie (Purism) >; 649eb4ea085SAngus Ainslie (Purism) }; 650eb4ea085SAngus Ainslie (Purism) 651eb4ea085SAngus Ainslie (Purism) pinctrl_i2c3: i2c3grp { 652eb4ea085SAngus Ainslie (Purism) fsl,pins = < 653eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f 654eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f 655eb4ea085SAngus Ainslie (Purism) >; 656eb4ea085SAngus Ainslie (Purism) }; 657eb4ea085SAngus Ainslie (Purism) 658eb4ea085SAngus Ainslie (Purism) pinctrl_imu: imugrp { 659eb4ea085SAngus Ainslie (Purism) fsl,pins = < 660eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */ 661eb4ea085SAngus Ainslie (Purism) >; 662eb4ea085SAngus Ainslie (Purism) }; 663eb4ea085SAngus Ainslie (Purism) 66415094482SGuido Günther pinctrl_micsel: micselgrp { 66515094482SGuido Günther fsl,pins = < 66615094482SGuido Günther MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6 /* MIC_SEL */ 66715094482SGuido Günther >; 66815094482SGuido Günther }; 66915094482SGuido Günther 6706f46f7ffSGuido Günther pinctrl_spkamp: spkamp { 6716f46f7ffSGuido Günther fsl,pins = < 6726f46f7ffSGuido Günther MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x81 /* MUTE */ 6736f46f7ffSGuido Günther >; 6746f46f7ffSGuido Günther }; 6756f46f7ffSGuido Günther 676eb4ea085SAngus Ainslie (Purism) pinctrl_pmic: pmicgrp { 677eb4ea085SAngus Ainslie (Purism) fsl,pins = < 678eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */ 679eb4ea085SAngus Ainslie (Purism) >; 680eb4ea085SAngus Ainslie (Purism) }; 681eb4ea085SAngus Ainslie (Purism) 682ea38ca9aSGuido Günther pinctrl_prox: proxgrp { 683ea38ca9aSGuido Günther fsl,pins = < 684ea38ca9aSGuido Günther MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */ 685ea38ca9aSGuido Günther >; 686ea38ca9aSGuido Günther }; 687ea38ca9aSGuido Günther 688eb4ea085SAngus Ainslie (Purism) pinctrl_pwr_en: pwrengrp { 689eb4ea085SAngus Ainslie (Purism) fsl,pins = < 690eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06 691eb4ea085SAngus Ainslie (Purism) >; 692eb4ea085SAngus Ainslie (Purism) }; 693eb4ea085SAngus Ainslie (Purism) 694eb4ea085SAngus Ainslie (Purism) pinctrl_rtc: rtcgrp { 695eb4ea085SAngus Ainslie (Purism) fsl,pins = < 696eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */ 697eb4ea085SAngus Ainslie (Purism) >; 698eb4ea085SAngus Ainslie (Purism) }; 699eb4ea085SAngus Ainslie (Purism) 700c53f0166SAngus Ainslie (Purism) pinctrl_sai2: sai2grp { 701c53f0166SAngus Ainslie (Purism) fsl,pins = < 702c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 703c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 704c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 705c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 706c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 707c53f0166SAngus Ainslie (Purism) >; 708c53f0166SAngus Ainslie (Purism) }; 709c53f0166SAngus Ainslie (Purism) 7107f7b7997SAngus Ainslie (Purism) pinctrl_sai6: sai6grp { 7117f7b7997SAngus Ainslie (Purism) fsl,pins = < 7127f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 7137f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 7147f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 7157f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 7167f7b7997SAngus Ainslie (Purism) >; 7177f7b7997SAngus Ainslie (Purism) }; 7187f7b7997SAngus Ainslie (Purism) 719eb4ea085SAngus Ainslie (Purism) pinctrl_typec: typecgrp { 720eb4ea085SAngus Ainslie (Purism) fsl,pins = < 721eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 722eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80 723eb4ea085SAngus Ainslie (Purism) >; 724eb4ea085SAngus Ainslie (Purism) }; 725eb4ea085SAngus Ainslie (Purism) 726eb4ea085SAngus Ainslie (Purism) pinctrl_uart1: uart1grp { 727eb4ea085SAngus Ainslie (Purism) fsl,pins = < 728eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 729eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 730eb4ea085SAngus Ainslie (Purism) >; 731eb4ea085SAngus Ainslie (Purism) }; 732eb4ea085SAngus Ainslie (Purism) 733eb4ea085SAngus Ainslie (Purism) pinctrl_uart2: uart2grp { 734eb4ea085SAngus Ainslie (Purism) fsl,pins = < 735eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 736eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 737eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 738eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 739eb4ea085SAngus Ainslie (Purism) >; 740eb4ea085SAngus Ainslie (Purism) }; 741eb4ea085SAngus Ainslie (Purism) 742eb4ea085SAngus Ainslie (Purism) pinctrl_uart3: uart3grp { 743eb4ea085SAngus Ainslie (Purism) fsl,pins = < 744eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 745eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 746eb4ea085SAngus Ainslie (Purism) >; 747eb4ea085SAngus Ainslie (Purism) }; 748eb4ea085SAngus Ainslie (Purism) 749eb4ea085SAngus Ainslie (Purism) pinctrl_uart4: uart4grp { 750eb4ea085SAngus Ainslie (Purism) fsl,pins = < 751eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 752eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 753eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 754eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 755eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49 756eb4ea085SAngus Ainslie (Purism) >; 757eb4ea085SAngus Ainslie (Purism) }; 758eb4ea085SAngus Ainslie (Purism) 759eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc1: usdhc1grp { 760eb4ea085SAngus Ainslie (Purism) fsl,pins = < 761eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 762eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 763eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 764eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 765eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 766eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 767eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 768eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 769eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 770eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 771eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 772eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 773eb4ea085SAngus Ainslie (Purism) >; 774eb4ea085SAngus Ainslie (Purism) }; 775eb4ea085SAngus Ainslie (Purism) 776ae560c43SKrzysztof Kozlowski pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 777eb4ea085SAngus Ainslie (Purism) fsl,pins = < 778eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 779eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 780eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 781eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 782eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 783eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 784eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 785eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 786eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 787eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 788eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 789eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 790eb4ea085SAngus Ainslie (Purism) >; 791eb4ea085SAngus Ainslie (Purism) }; 792eb4ea085SAngus Ainslie (Purism) 793ae560c43SKrzysztof Kozlowski pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 794eb4ea085SAngus Ainslie (Purism) fsl,pins = < 795eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 796eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 797eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 798eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 799eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 800eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 801eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 802eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 803eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 804eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 805eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 806eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 807eb4ea085SAngus Ainslie (Purism) >; 808eb4ea085SAngus Ainslie (Purism) }; 809eb4ea085SAngus Ainslie (Purism) 810ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_pwr: usdhc2pwrgrp { 811eb4ea085SAngus Ainslie (Purism) fsl,pins = < 812eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 813eb4ea085SAngus Ainslie (Purism) >; 814eb4ea085SAngus Ainslie (Purism) }; 815eb4ea085SAngus Ainslie (Purism) 816ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_gpio: usdhc2gpiogrp { 817eb4ea085SAngus Ainslie (Purism) fsl,pins = < 818eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ 819eb4ea085SAngus Ainslie (Purism) >; 820eb4ea085SAngus Ainslie (Purism) }; 821eb4ea085SAngus Ainslie (Purism) 822eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2: usdhc2grp { 823eb4ea085SAngus Ainslie (Purism) fsl,pins = < 824eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 825eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 826eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 827eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 828eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 829eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 830eb4ea085SAngus Ainslie (Purism) >; 831eb4ea085SAngus Ainslie (Purism) }; 832eb4ea085SAngus Ainslie (Purism) 833ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 834eb4ea085SAngus Ainslie (Purism) fsl,pins = < 835eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 836eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 837eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 838eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 839eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 840eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 841eb4ea085SAngus Ainslie (Purism) >; 842eb4ea085SAngus Ainslie (Purism) }; 843eb4ea085SAngus Ainslie (Purism) 844ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 845eb4ea085SAngus Ainslie (Purism) fsl,pins = < 846eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 847eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf 848eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf 849eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf 850eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf 851eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf 852eb4ea085SAngus Ainslie (Purism) >; 853eb4ea085SAngus Ainslie (Purism) }; 854eb4ea085SAngus Ainslie (Purism) 855eb4ea085SAngus Ainslie (Purism) pinctrl_wdog: wdoggrp { 856eb4ea085SAngus Ainslie (Purism) fsl,pins = < 857eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 858eb4ea085SAngus Ainslie (Purism) >; 859eb4ea085SAngus Ainslie (Purism) }; 860eb4ea085SAngus Ainslie (Purism) 861eb4ea085SAngus Ainslie (Purism) pinctrl_wifi_pwr_en: wifipwrengrp { 862eb4ea085SAngus Ainslie (Purism) fsl,pins = < 863eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 864eb4ea085SAngus Ainslie (Purism) >; 865eb4ea085SAngus Ainslie (Purism) }; 866eb4ea085SAngus Ainslie (Purism) 867eb4ea085SAngus Ainslie (Purism) pinctrl_wwan: wwangrp { 868eb4ea085SAngus Ainslie (Purism) fsl,pins = < 869eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */ 870eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ 871eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */ 872eb4ea085SAngus Ainslie (Purism) >; 873eb4ea085SAngus Ainslie (Purism) }; 874eb4ea085SAngus Ainslie (Purism)}; 875eb4ea085SAngus Ainslie (Purism) 876e8151ef3SGuido Günther&lcdif { 877e8151ef3SGuido Günther status = "okay"; 878e8151ef3SGuido Günther}; 879e8151ef3SGuido Günther 880e8151ef3SGuido Günther&mipi_dsi { 881e8151ef3SGuido Günther status = "okay"; 882e8151ef3SGuido Günther #address-cells = <1>; 883e8151ef3SGuido Günther #size-cells = <0>; 884e8151ef3SGuido Günther 885e8151ef3SGuido Günther panel@0 { 886e8151ef3SGuido Günther compatible = "rocktech,jh057n00900"; 887e8151ef3SGuido Günther reg = <0>; 888e8151ef3SGuido Günther backlight = <&backlight_dsi>; 889e8151ef3SGuido Günther reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; 890e8151ef3SGuido Günther iovcc-supply = <®_1v8_p>; 891e8151ef3SGuido Günther vcc-supply = <®_2v8_p>; 892e8151ef3SGuido Günther port { 893e8151ef3SGuido Günther panel_in: endpoint { 894e8151ef3SGuido Günther remote-endpoint = <&mipi_dsi_out>; 895e8151ef3SGuido Günther }; 896e8151ef3SGuido Günther }; 897e8151ef3SGuido Günther }; 898e8151ef3SGuido Günther 899e8151ef3SGuido Günther ports { 900e8151ef3SGuido Günther port@1 { 901e8151ef3SGuido Günther reg = <1>; 902e8151ef3SGuido Günther mipi_dsi_out: endpoint { 903e8151ef3SGuido Günther remote-endpoint = <&panel_in>; 904e8151ef3SGuido Günther }; 905e8151ef3SGuido Günther }; 906e8151ef3SGuido Günther }; 907e8151ef3SGuido Günther}; 908e8151ef3SGuido Günther 909eb4ea085SAngus Ainslie (Purism)&pgc_gpu { 910eb4ea085SAngus Ainslie (Purism) power-supply = <&buck3_reg>; 911eb4ea085SAngus Ainslie (Purism)}; 912eb4ea085SAngus Ainslie (Purism) 913eb4ea085SAngus Ainslie (Purism)&pgc_vpu { 914eb4ea085SAngus Ainslie (Purism) power-supply = <&buck4_reg>; 915eb4ea085SAngus Ainslie (Purism)}; 916eb4ea085SAngus Ainslie (Purism) 917eb4ea085SAngus Ainslie (Purism)&pwm1 { 918eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 919eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_bl>; 920eb4ea085SAngus Ainslie (Purism) status = "okay"; 921eb4ea085SAngus Ainslie (Purism)}; 922eb4ea085SAngus Ainslie (Purism) 92301407158SAngus Ainslie (Purism)&snvs_pwrkey { 92401407158SAngus Ainslie (Purism) status = "okay"; 92501407158SAngus Ainslie (Purism)}; 926eb4ea085SAngus Ainslie (Purism) 927ff38c1ddSGuido Günther&snvs_rtc { 928ff38c1ddSGuido Günther status = "disabled"; 929ff38c1ddSGuido Günther}; 930ff38c1ddSGuido Günther 931c53f0166SAngus Ainslie (Purism)&sai2 { 932c53f0166SAngus Ainslie (Purism) pinctrl-names = "default"; 933c53f0166SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_sai2>; 934c53f0166SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 935c53f0166SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 936c53f0166SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 937c53f0166SAngus Ainslie (Purism) status = "okay"; 938c53f0166SAngus Ainslie (Purism)}; 939c53f0166SAngus Ainslie (Purism) 9407f7b7997SAngus Ainslie (Purism)&sai6 { 9417f7b7997SAngus Ainslie (Purism) pinctrl-names = "default"; 9427f7b7997SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_sai6>; 9437f7b7997SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; 9447f7b7997SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 9457f7b7997SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 9467f7b7997SAngus Ainslie (Purism) fsl,sai-synchronous-rx; 9477f7b7997SAngus Ainslie (Purism) status = "okay"; 9487f7b7997SAngus Ainslie (Purism)}; 9497f7b7997SAngus Ainslie (Purism) 950eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */ 951eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 952eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart1>; 953eb4ea085SAngus Ainslie (Purism) status = "okay"; 954eb4ea085SAngus Ainslie (Purism)}; 955eb4ea085SAngus Ainslie (Purism) 956eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */ 957eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 958eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart3>; 959eb4ea085SAngus Ainslie (Purism) status = "okay"; 960eb4ea085SAngus Ainslie (Purism)}; 961eb4ea085SAngus Ainslie (Purism) 962eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */ 963eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 964eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; 965eb4ea085SAngus Ainslie (Purism) uart-has-rtscts; 966eb4ea085SAngus Ainslie (Purism) status = "okay"; 967eb4ea085SAngus Ainslie (Purism)}; 968eb4ea085SAngus Ainslie (Purism) 969eb4ea085SAngus Ainslie (Purism)&usb3_phy0 { 970dde061b8SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 971eb4ea085SAngus Ainslie (Purism) status = "okay"; 972eb4ea085SAngus Ainslie (Purism)}; 973eb4ea085SAngus Ainslie (Purism) 974eb4ea085SAngus Ainslie (Purism)&usb3_phy1 { 975eb4ea085SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 976eb4ea085SAngus Ainslie (Purism) status = "okay"; 977eb4ea085SAngus Ainslie (Purism)}; 978eb4ea085SAngus Ainslie (Purism) 979eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 { 980eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 981eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 982eb4ea085SAngus Ainslie (Purism) dr_mode = "otg"; 983eb4ea085SAngus Ainslie (Purism) status = "okay"; 984eb4ea085SAngus Ainslie (Purism) 985eb4ea085SAngus Ainslie (Purism) port@0 { 986eb4ea085SAngus Ainslie (Purism) reg = <0>; 987eb4ea085SAngus Ainslie (Purism) 988eb4ea085SAngus Ainslie (Purism) typec_hs: endpoint { 989eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_hs>; 990eb4ea085SAngus Ainslie (Purism) }; 991eb4ea085SAngus Ainslie (Purism) }; 992eb4ea085SAngus Ainslie (Purism) 993eb4ea085SAngus Ainslie (Purism) port@1 { 994eb4ea085SAngus Ainslie (Purism) reg = <1>; 995eb4ea085SAngus Ainslie (Purism) 996eb4ea085SAngus Ainslie (Purism) typec_ss: endpoint { 997eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_ss>; 998eb4ea085SAngus Ainslie (Purism) }; 999eb4ea085SAngus Ainslie (Purism) }; 1000eb4ea085SAngus Ainslie (Purism)}; 1001eb4ea085SAngus Ainslie (Purism) 1002eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 { 1003eb4ea085SAngus Ainslie (Purism) dr_mode = "host"; 1004eb4ea085SAngus Ainslie (Purism) status = "okay"; 1005eb4ea085SAngus Ainslie (Purism)}; 1006eb4ea085SAngus Ainslie (Purism) 1007eb4ea085SAngus Ainslie (Purism)&usdhc1 { 1008e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 1009e045f044SAnson Huang assigned-clock-rates = <400000000>; 1010eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1011eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc1>; 1012eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 1013eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 1014eb4ea085SAngus Ainslie (Purism) bus-width = <8>; 1015eb4ea085SAngus Ainslie (Purism) non-removable; 1016eb4ea085SAngus Ainslie (Purism) status = "okay"; 1017eb4ea085SAngus Ainslie (Purism)}; 1018eb4ea085SAngus Ainslie (Purism) 1019eb4ea085SAngus Ainslie (Purism)&usdhc2 { 1020e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 1021e045f044SAnson Huang assigned-clock-rates = <200000000>; 1022eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1023eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2>; 1024eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 1025eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 1026eb4ea085SAngus Ainslie (Purism) bus-width = <4>; 1027eb4ea085SAngus Ainslie (Purism) vmmc-supply = <®_usdhc2_vmmc>; 1028eb4ea085SAngus Ainslie (Purism) power-supply = <&wifi_pwr_en>; 10299dae8563SAngus Ainslie (Purism) broken-cd; 1030eb4ea085SAngus Ainslie (Purism) disable-wp; 1031eb4ea085SAngus Ainslie (Purism) cap-sdio-irq; 1032eb4ea085SAngus Ainslie (Purism) keep-power-in-suspend; 1033eb4ea085SAngus Ainslie (Purism) wakeup-source; 1034eb4ea085SAngus Ainslie (Purism) status = "okay"; 1035eb4ea085SAngus Ainslie (Purism)}; 1036eb4ea085SAngus Ainslie (Purism) 1037eb4ea085SAngus Ainslie (Purism)&wdog1 { 1038eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 1039eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wdog>; 1040eb4ea085SAngus Ainslie (Purism) fsl,ext-reset-output; 1041eb4ea085SAngus Ainslie (Purism) status = "okay"; 1042eb4ea085SAngus Ainslie (Purism)}; 1043