1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+
2eb4ea085SAngus Ainslie (Purism)/*
3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC
4eb4ea085SAngus Ainslie (Purism) */
5eb4ea085SAngus Ainslie (Purism)
6eb4ea085SAngus Ainslie (Purism)/dts-v1/;
7eb4ea085SAngus Ainslie (Purism)
8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h"
9eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h"
10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h"
11eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi"
12eb4ea085SAngus Ainslie (Purism)
13eb4ea085SAngus Ainslie (Purism)/ {
14eb4ea085SAngus Ainslie (Purism)	model = "Purism Librem 5 devkit";
15eb4ea085SAngus Ainslie (Purism)	compatible = "purism,librem5-devkit", "fsl,imx8mq";
16eb4ea085SAngus Ainslie (Purism)
17eb4ea085SAngus Ainslie (Purism)	backlight_dsi: backlight-dsi {
18eb4ea085SAngus Ainslie (Purism)		compatible = "pwm-backlight";
19eb4ea085SAngus Ainslie (Purism)		/* 200 Hz for the PAM2841 */
20eb4ea085SAngus Ainslie (Purism)		pwms = <&pwm1 0 5000000>;
21eb4ea085SAngus Ainslie (Purism)		brightness-levels = <0 100>;
22eb4ea085SAngus Ainslie (Purism)		num-interpolated-steps = <100>;
23eb4ea085SAngus Ainslie (Purism)		/* Default brightness level (index into the array defined by */
24eb4ea085SAngus Ainslie (Purism)		/* the "brightness-levels" property) */
25eb4ea085SAngus Ainslie (Purism)		default-brightness-level = <0>;
26eb4ea085SAngus Ainslie (Purism)		power-supply = <&reg_22v4_p>;
27eb4ea085SAngus Ainslie (Purism)	};
28eb4ea085SAngus Ainslie (Purism)
29eb4ea085SAngus Ainslie (Purism)	chosen {
30eb4ea085SAngus Ainslie (Purism)		stdout-path = &uart1;
31eb4ea085SAngus Ainslie (Purism)	};
32eb4ea085SAngus Ainslie (Purism)
33eb4ea085SAngus Ainslie (Purism)	gpio-keys {
34eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-keys";
35eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
36eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_keys>;
37eb4ea085SAngus Ainslie (Purism)
38eb4ea085SAngus Ainslie (Purism)		btn1 {
39eb4ea085SAngus Ainslie (Purism)			label = "VOL_UP";
40eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
41eb4ea085SAngus Ainslie (Purism)			wakeup-source;
42eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEUP>;
43eb4ea085SAngus Ainslie (Purism)		};
44eb4ea085SAngus Ainslie (Purism)
45eb4ea085SAngus Ainslie (Purism)		btn2 {
46eb4ea085SAngus Ainslie (Purism)			label = "VOL_DOWN";
47eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
48eb4ea085SAngus Ainslie (Purism)			wakeup-source;
49eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEDOWN>;
50eb4ea085SAngus Ainslie (Purism)		};
51eb4ea085SAngus Ainslie (Purism)
52eb4ea085SAngus Ainslie (Purism)		hp-det {
53eb4ea085SAngus Ainslie (Purism)			label = "HP_DET";
54eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
55eb4ea085SAngus Ainslie (Purism)			wakeup-source;
56eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_HP>;
57eb4ea085SAngus Ainslie (Purism)		};
58eb4ea085SAngus Ainslie (Purism)	};
59eb4ea085SAngus Ainslie (Purism)
60eb4ea085SAngus Ainslie (Purism)	leds {
61eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-leds";
62eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
63eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_leds>;
64eb4ea085SAngus Ainslie (Purism)
65eb4ea085SAngus Ainslie (Purism)		led1 {
66eb4ea085SAngus Ainslie (Purism)			label = "LED 1";
67eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
68eb4ea085SAngus Ainslie (Purism)			default-state = "off";
69eb4ea085SAngus Ainslie (Purism)		};
70eb4ea085SAngus Ainslie (Purism)	};
71eb4ea085SAngus Ainslie (Purism)
72eb4ea085SAngus Ainslie (Purism)	pmic_osc: clock-pmic {
73eb4ea085SAngus Ainslie (Purism)		compatible = "fixed-clock";
74eb4ea085SAngus Ainslie (Purism)		#clock-cells = <0>;
75eb4ea085SAngus Ainslie (Purism)		clock-frequency = <32768>;
76eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_osc";
77eb4ea085SAngus Ainslie (Purism)	};
78eb4ea085SAngus Ainslie (Purism)
79eb4ea085SAngus Ainslie (Purism)	reg_1v8_p: regulator-1v8-p {
80eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
81eb4ea085SAngus Ainslie (Purism)		regulator-name = "1v8_p";
82eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <1800000>;
83eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <1800000>;
84eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
85eb4ea085SAngus Ainslie (Purism)	};
86eb4ea085SAngus Ainslie (Purism)
87eb4ea085SAngus Ainslie (Purism)	reg_2v8_p: regulator-2v8-p {
88eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
89eb4ea085SAngus Ainslie (Purism)		regulator-name = "2v8_p";
90eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <2800000>;
91eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <2800000>;
92eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
93eb4ea085SAngus Ainslie (Purism)	};
94eb4ea085SAngus Ainslie (Purism)
95eb4ea085SAngus Ainslie (Purism)	reg_3v3_p: regulator-3v3-p {
96eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
97eb4ea085SAngus Ainslie (Purism)		regulator-name = "3v3_p";
98eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
99eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
100eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
101eb4ea085SAngus Ainslie (Purism)
102eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
103eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
104eb4ea085SAngus Ainslie (Purism)		};
105eb4ea085SAngus Ainslie (Purism)	};
106eb4ea085SAngus Ainslie (Purism)
107eb4ea085SAngus Ainslie (Purism)	reg_5v_p: regulator-5v-p {
108eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
109eb4ea085SAngus Ainslie (Purism)		regulator-name = "5v_p";
110eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <5000000>;
111eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <5000000>;
112eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
113eb4ea085SAngus Ainslie (Purism)
114eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
115eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
116eb4ea085SAngus Ainslie (Purism)		};
117eb4ea085SAngus Ainslie (Purism)	};
118eb4ea085SAngus Ainslie (Purism)
119eb4ea085SAngus Ainslie (Purism)	reg_22v4_p: regulator-22v4-p  {
120eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
121eb4ea085SAngus Ainslie (Purism)		regulator-name = "22v4_P";
122eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <22400000>;
123eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <22400000>;
124eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
125eb4ea085SAngus Ainslie (Purism)	};
126eb4ea085SAngus Ainslie (Purism)
127eb4ea085SAngus Ainslie (Purism)	reg_pwr_en: regulator-pwr-en {
128eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
129eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
130eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pwr_en>;
131eb4ea085SAngus Ainslie (Purism)		regulator-name = "PWR_EN";
132eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
133eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
134eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
135eb4ea085SAngus Ainslie (Purism)		enable-active-high;
136eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
137eb4ea085SAngus Ainslie (Purism)	};
138eb4ea085SAngus Ainslie (Purism)
139eb4ea085SAngus Ainslie (Purism)	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
140eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
141eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
142eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_usdhc2_pwr>;
143eb4ea085SAngus Ainslie (Purism)		regulator-name = "VSD_3V3";
144eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
145eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
146eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
147eb4ea085SAngus Ainslie (Purism)		enable-active-high;
148eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
149eb4ea085SAngus Ainslie (Purism)	};
150eb4ea085SAngus Ainslie (Purism)
151c53f0166SAngus Ainslie (Purism)	sound {
152c53f0166SAngus Ainslie (Purism)		compatible = "simple-audio-card";
153c53f0166SAngus Ainslie (Purism)		simple-audio-card,name = "sgtl5000";
154c53f0166SAngus Ainslie (Purism)		simple-audio-card,format = "i2s";
155c53f0166SAngus Ainslie (Purism)		simple-audio-card,widgets =
156c53f0166SAngus Ainslie (Purism)			"Microphone", "Microphone Jack",
157c53f0166SAngus Ainslie (Purism)			"Headphone", "Headphone Jack",
158c53f0166SAngus Ainslie (Purism)			"Speaker", "Speaker Ext",
159c53f0166SAngus Ainslie (Purism)			"Line", "Line In Jack";
160c53f0166SAngus Ainslie (Purism)		simple-audio-card,routing =
161c53f0166SAngus Ainslie (Purism)			"MIC_IN", "Microphone Jack",
162c53f0166SAngus Ainslie (Purism)			"Microphone Jack", "Mic Bias",
163c53f0166SAngus Ainslie (Purism)			"LINE_IN", "Line In Jack",
164c53f0166SAngus Ainslie (Purism)			"Headphone Jack", "HP_OUT",
165c53f0166SAngus Ainslie (Purism)			"Speaker Ext", "LINE_OUT";
166c53f0166SAngus Ainslie (Purism)
167c53f0166SAngus Ainslie (Purism)		simple-audio-card,cpu {
168c53f0166SAngus Ainslie (Purism)			sound-dai = <&sai2>;
169c53f0166SAngus Ainslie (Purism)		};
170c53f0166SAngus Ainslie (Purism)
171c53f0166SAngus Ainslie (Purism)		simple-audio-card,codec {
172c53f0166SAngus Ainslie (Purism)			sound-dai = <&sgtl5000>;
173c53f0166SAngus Ainslie (Purism)			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
174c53f0166SAngus Ainslie (Purism)			frame-master;
175c53f0166SAngus Ainslie (Purism)			bitclock-master;
176c53f0166SAngus Ainslie (Purism)		};
177c53f0166SAngus Ainslie (Purism)	};
178c53f0166SAngus Ainslie (Purism)
179eb4ea085SAngus Ainslie (Purism)	vibrator {
180eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-vibrator";
181eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
182eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_haptic>;
183eb4ea085SAngus Ainslie (Purism)	        enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
184eb4ea085SAngus Ainslie (Purism)		vcc-supply = <&reg_3v3_p>;
185eb4ea085SAngus Ainslie (Purism)	};
186eb4ea085SAngus Ainslie (Purism)
187eb4ea085SAngus Ainslie (Purism)	wifi_pwr_en: regulator-wifi-en {
188eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
189eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
190eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
191eb4ea085SAngus Ainslie (Purism)		regulator-name = "WIFI_EN";
192eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
193eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
194eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
195eb4ea085SAngus Ainslie (Purism)		enable-active-high;
196eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
197eb4ea085SAngus Ainslie (Purism)	};
198eb4ea085SAngus Ainslie (Purism)};
199eb4ea085SAngus Ainslie (Purism)
200eb4ea085SAngus Ainslie (Purism)&clk {
201eb4ea085SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
202eb4ea085SAngus Ainslie (Purism)	assigned-clock-rates = <786432000>, <722534400>;
203eb4ea085SAngus Ainslie (Purism)};
204eb4ea085SAngus Ainslie (Purism)
2059d9005a5SGuido Günther&dphy {
2069d9005a5SGuido Günther	status = "okay";
2079d9005a5SGuido Günther};
2089d9005a5SGuido Günther
209eb4ea085SAngus Ainslie (Purism)&fec1 {
210eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
211eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_fec1>;
212eb4ea085SAngus Ainslie (Purism)	phy-mode = "rgmii-id";
213eb4ea085SAngus Ainslie (Purism)	phy-handle = <&ethphy0>;
214eb4ea085SAngus Ainslie (Purism)	fsl,magic-packet;
215eb4ea085SAngus Ainslie (Purism)	phy-supply = <&reg_3v3_p>;
216eb4ea085SAngus Ainslie (Purism)	status = "okay";
217eb4ea085SAngus Ainslie (Purism)
218eb4ea085SAngus Ainslie (Purism)	mdio {
219eb4ea085SAngus Ainslie (Purism)		#address-cells = <1>;
220eb4ea085SAngus Ainslie (Purism)		#size-cells = <0>;
221eb4ea085SAngus Ainslie (Purism)
222eb4ea085SAngus Ainslie (Purism)		ethphy0: ethernet-phy@1 {
223eb4ea085SAngus Ainslie (Purism)			compatible = "ethernet-phy-ieee802.3-c22";
224eb4ea085SAngus Ainslie (Purism)			reg = <1>;
225eb4ea085SAngus Ainslie (Purism)		};
226eb4ea085SAngus Ainslie (Purism)	};
227eb4ea085SAngus Ainslie (Purism)};
228eb4ea085SAngus Ainslie (Purism)
229eb4ea085SAngus Ainslie (Purism)&i2c1 {
230eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
231eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
232eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c1>;
233eb4ea085SAngus Ainslie (Purism)	status = "okay";
234eb4ea085SAngus Ainslie (Purism)
235eb4ea085SAngus Ainslie (Purism)	pmic: pmic@4b {
236eb4ea085SAngus Ainslie (Purism)		compatible = "rohm,bd71837";
237eb4ea085SAngus Ainslie (Purism)		reg = <0x4b>;
238eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
239eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pmic>;
240eb4ea085SAngus Ainslie (Purism)		clocks = <&pmic_osc>;
241eb4ea085SAngus Ainslie (Purism)		clock-names = "osc";
242eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_clk";
243eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio1>;
244eb4ea085SAngus Ainslie (Purism)		interrupts = <3 GPIO_ACTIVE_LOW>;
245eb4ea085SAngus Ainslie (Purism)		interrupt-names = "irq";
246eb4ea085SAngus Ainslie (Purism)		rohm,reset-snvs-powered;
247eb4ea085SAngus Ainslie (Purism)
248eb4ea085SAngus Ainslie (Purism)		regulators {
249eb4ea085SAngus Ainslie (Purism)			buck1_reg: BUCK1 {
250eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck1";
251eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
252eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
253eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
254eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
255eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <900000>;
256eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <850000>;
257eb4ea085SAngus Ainslie (Purism)				rohm,dvs-suspend-voltage = <800000>;
258eb4ea085SAngus Ainslie (Purism)			};
259eb4ea085SAngus Ainslie (Purism)
260eb4ea085SAngus Ainslie (Purism)			buck2_reg: BUCK2 {
261eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck2";
262eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
263eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
264eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
265eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
266eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
267eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <900000>;
268eb4ea085SAngus Ainslie (Purism)			};
269eb4ea085SAngus Ainslie (Purism)
270eb4ea085SAngus Ainslie (Purism)			buck3_reg: BUCK3 {
271eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck3";
272eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
273eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
274eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
275eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
276eb4ea085SAngus Ainslie (Purism)			};
277eb4ea085SAngus Ainslie (Purism)
278eb4ea085SAngus Ainslie (Purism)			buck4_reg: BUCK4 {
279eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck4";
280eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
281eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
282eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
283eb4ea085SAngus Ainslie (Purism)			};
284eb4ea085SAngus Ainslie (Purism)
285eb4ea085SAngus Ainslie (Purism)			buck5_reg: BUCK5 {
286eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck5";
287eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
288eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1350000>;
289eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
290eb4ea085SAngus Ainslie (Purism)			};
291eb4ea085SAngus Ainslie (Purism)
292eb4ea085SAngus Ainslie (Purism)			buck6_reg: BUCK6 {
293eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck6";
294eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
295eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
296eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
297eb4ea085SAngus Ainslie (Purism)			};
298eb4ea085SAngus Ainslie (Purism)
299eb4ea085SAngus Ainslie (Purism)			buck7_reg: BUCK7 {
300eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck7";
301eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1605000>;
302eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1995000>;
303eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
304eb4ea085SAngus Ainslie (Purism)			};
305eb4ea085SAngus Ainslie (Purism)
306eb4ea085SAngus Ainslie (Purism)			buck8_reg: BUCK8 {
307eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck8";
308eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <800000>;
309eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1400000>;
310eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
311eb4ea085SAngus Ainslie (Purism)			};
312eb4ea085SAngus Ainslie (Purism)
313eb4ea085SAngus Ainslie (Purism)			ldo1_reg: LDO1 {
314eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo1";
315eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
316eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
317eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
318eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
319eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
320eb4ea085SAngus Ainslie (Purism)			};
321eb4ea085SAngus Ainslie (Purism)
322eb4ea085SAngus Ainslie (Purism)			ldo2_reg: LDO2 {
323eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo2";
324eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
325eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <900000>;
326eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
327eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
328eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
329eb4ea085SAngus Ainslie (Purism)			};
330eb4ea085SAngus Ainslie (Purism)
331eb4ea085SAngus Ainslie (Purism)			ldo3_reg: LDO3 {
332eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo3";
333eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
334eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
335eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
336eb4ea085SAngus Ainslie (Purism)			};
337eb4ea085SAngus Ainslie (Purism)
338eb4ea085SAngus Ainslie (Purism)			ldo4_reg: LDO4 {
339eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo4";
340eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
341eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
342eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
343eb4ea085SAngus Ainslie (Purism)			};
344eb4ea085SAngus Ainslie (Purism)
345eb4ea085SAngus Ainslie (Purism)			ldo5_reg: LDO5 {
346eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo5";
347eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
348eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
349eb4ea085SAngus Ainslie (Purism)			};
350eb4ea085SAngus Ainslie (Purism)
351eb4ea085SAngus Ainslie (Purism)			ldo6_reg: LDO6 {
352eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo6";
353eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
354eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
355eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
356eb4ea085SAngus Ainslie (Purism)			};
357eb4ea085SAngus Ainslie (Purism)
358eb4ea085SAngus Ainslie (Purism)			ldo7_reg: LDO7 {
359eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo7";
360eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
361eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
362eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
363eb4ea085SAngus Ainslie (Purism)			};
364eb4ea085SAngus Ainslie (Purism)		};
365eb4ea085SAngus Ainslie (Purism)	};
366eb4ea085SAngus Ainslie (Purism)
367eb4ea085SAngus Ainslie (Purism)	typec_ptn5100: usb_typec@52 {
368eb4ea085SAngus Ainslie (Purism)		compatible = "nxp,ptn5110";
369eb4ea085SAngus Ainslie (Purism)		reg = <0x52>;
370eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
371eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_typec>;
372eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
373eb4ea085SAngus Ainslie (Purism)		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
374eb4ea085SAngus Ainslie (Purism)
375eb4ea085SAngus Ainslie (Purism)		connector {
376eb4ea085SAngus Ainslie (Purism)			compatible = "usb-c-connector";
377eb4ea085SAngus Ainslie (Purism)			label = "USB-C";
378eb4ea085SAngus Ainslie (Purism)			data-role = "dual";
379eb4ea085SAngus Ainslie (Purism)			power-role = "dual";
380eb4ea085SAngus Ainslie (Purism)			try-power-role = "sink";
381eb4ea085SAngus Ainslie (Purism)			source-pdos = <PDO_FIXED(5000, 2000,
382eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_USB_COMM |
383eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
384eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )>;
385eb4ea085SAngus Ainslie (Purism)			sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM |
386eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
387eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )
3888155b786SAngus Ainslie (Purism)			     PDO_VAR(5000, 3000, 3000)>;
389eb4ea085SAngus Ainslie (Purism)			op-sink-microwatt = <10000000>;
390eb4ea085SAngus Ainslie (Purism)
391eb4ea085SAngus Ainslie (Purism)			ports {
392eb4ea085SAngus Ainslie (Purism)				#address-cells = <1>;
393eb4ea085SAngus Ainslie (Purism)				#size-cells = <0>;
394eb4ea085SAngus Ainslie (Purism)
395eb4ea085SAngus Ainslie (Purism)				port@0 {
396eb4ea085SAngus Ainslie (Purism)					reg = <0>;
397eb4ea085SAngus Ainslie (Purism)
398eb4ea085SAngus Ainslie (Purism)					usb_con_hs: endpoint {
399eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_hs>;
400eb4ea085SAngus Ainslie (Purism)					};
401eb4ea085SAngus Ainslie (Purism)				};
402eb4ea085SAngus Ainslie (Purism)
403eb4ea085SAngus Ainslie (Purism)				port@1 {
404eb4ea085SAngus Ainslie (Purism)					reg = <1>;
405eb4ea085SAngus Ainslie (Purism)
406eb4ea085SAngus Ainslie (Purism)					usb_con_ss: endpoint {
407eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_ss>;
408eb4ea085SAngus Ainslie (Purism)					};
409eb4ea085SAngus Ainslie (Purism)				};
410eb4ea085SAngus Ainslie (Purism)			};
411eb4ea085SAngus Ainslie (Purism)		};
412eb4ea085SAngus Ainslie (Purism)	};
413eb4ea085SAngus Ainslie (Purism)
414eb4ea085SAngus Ainslie (Purism)	rtc@68 {
415eb4ea085SAngus Ainslie (Purism)		compatible = "microcrystal,rv4162";
416eb4ea085SAngus Ainslie (Purism)		reg = <0x68>;
417eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
418eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_rtc>;
419eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio4>;
420eb4ea085SAngus Ainslie (Purism)		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
421eb4ea085SAngus Ainslie (Purism)	};
422eb4ea085SAngus Ainslie (Purism)
423eb4ea085SAngus Ainslie (Purism)	charger@6b { /* bq25896 */
424eb4ea085SAngus Ainslie (Purism)		compatible = "ti,bq25890";
425eb4ea085SAngus Ainslie (Purism)		reg = <0x6b>;
426eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
427eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_charger>;
428eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
429eb4ea085SAngus Ainslie (Purism)		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
430eb4ea085SAngus Ainslie (Purism)		ti,battery-regulation-voltage = <4192000>; /* 4.192V */
431eb4ea085SAngus Ainslie (Purism)		ti,charge-current = <1600000>; /* 1.6A */
432eb4ea085SAngus Ainslie (Purism)		ti,termination-current = <66000>;  /* 66mA */
433eb4ea085SAngus Ainslie (Purism)		ti,precharge-current = <130000>; /* 130mA */
434eb4ea085SAngus Ainslie (Purism)		ti,minimum-sys-voltage = <3000000>; /* 3V */
435eb4ea085SAngus Ainslie (Purism)		ti,boost-voltage = <5000000>; /* 5V */
436eb4ea085SAngus Ainslie (Purism)		ti,boost-max-current = <50000>; /* 50mA */
437eb4ea085SAngus Ainslie (Purism)	};
438eb4ea085SAngus Ainslie (Purism)};
439eb4ea085SAngus Ainslie (Purism)
440eb4ea085SAngus Ainslie (Purism)&i2c3 {
441eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
442eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
443eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c3>;
444eb4ea085SAngus Ainslie (Purism)	status = "okay";
445eb4ea085SAngus Ainslie (Purism)
446eb4ea085SAngus Ainslie (Purism)	magnetometer@1e	{
447eb4ea085SAngus Ainslie (Purism)		compatible = "st,lsm9ds1-magn";
448eb4ea085SAngus Ainslie (Purism)		reg = <0x1e>;
449eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
450eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_imu>;
451eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
452106f7b3bSAngus Ainslie (Purism)		interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
453eb4ea085SAngus Ainslie (Purism)		vdd-supply = <&reg_3v3_p>;
454eb4ea085SAngus Ainslie (Purism)		vddio-supply = <&reg_3v3_p>;
455eb4ea085SAngus Ainslie (Purism)	};
456eb4ea085SAngus Ainslie (Purism)
457c53f0166SAngus Ainslie (Purism)	sgtl5000: audio-codec@a {
458c53f0166SAngus Ainslie (Purism)		compatible = "fsl,sgtl5000";
459c53f0166SAngus Ainslie (Purism)		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
460c53f0166SAngus Ainslie (Purism)		assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
461c53f0166SAngus Ainslie (Purism)		assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
462c53f0166SAngus Ainslie (Purism)		assigned-clock-rates = <24576000>;
463c53f0166SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
464c53f0166SAngus Ainslie (Purism)		reg = <0x0a>;
465c53f0166SAngus Ainslie (Purism)		VDDD-supply = <&reg_1v8_p>;
466c53f0166SAngus Ainslie (Purism)		VDDIO-supply = <&reg_3v3_p>;
467c53f0166SAngus Ainslie (Purism)		VDDA-supply = <&reg_3v3_p>;
468c53f0166SAngus Ainslie (Purism)	};
469c53f0166SAngus Ainslie (Purism)
470eb4ea085SAngus Ainslie (Purism)	touchscreen@5d {
471eb4ea085SAngus Ainslie (Purism)		compatible = "goodix,gt5688";
472eb4ea085SAngus Ainslie (Purism)		reg = <0x5d>;
473eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
474eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_ts>;
475eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
476eb4ea085SAngus Ainslie (Purism)		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
477eb4ea085SAngus Ainslie (Purism)		reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
478eb4ea085SAngus Ainslie (Purism)		irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
479eb4ea085SAngus Ainslie (Purism)		touchscreen-size-x = <720>;
480eb4ea085SAngus Ainslie (Purism)		touchscreen-size-y = <1440>;
481eb4ea085SAngus Ainslie (Purism)		AVDD28-supply = <&reg_2v8_p>;
482eb4ea085SAngus Ainslie (Purism)		VDDIO-supply = <&reg_1v8_p>;
483eb4ea085SAngus Ainslie (Purism)	};
484537c00e3SMartin Kepplinger
485ea38ca9aSGuido Günther	proximity-sensor@60 {
486ea38ca9aSGuido Günther		compatible = "vishay,vcnl4040";
487ea38ca9aSGuido Günther		reg = <0x60>;
488ea38ca9aSGuido Günther		pinctrl-0 = <&pinctrl_prox>;
489ea38ca9aSGuido Günther	};
490ea38ca9aSGuido Günther
491537c00e3SMartin Kepplinger	accel-gyro@6a {
492537c00e3SMartin Kepplinger		compatible = "st,lsm9ds1-imu";
493537c00e3SMartin Kepplinger		reg = <0x6a>;
494537c00e3SMartin Kepplinger		vdd-supply = <&reg_3v3_p>;
495537c00e3SMartin Kepplinger		vddio-supply = <&reg_3v3_p>;
496537c00e3SMartin Kepplinger	};
497eb4ea085SAngus Ainslie (Purism)};
498eb4ea085SAngus Ainslie (Purism)
499eb4ea085SAngus Ainslie (Purism)&iomuxc {
500eb4ea085SAngus Ainslie (Purism)	pinctrl_bl: blgrp {
501eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
502eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT	0x6 /* DSI_BL_PWM */
503eb4ea085SAngus Ainslie (Purism)		>;
504eb4ea085SAngus Ainslie (Purism)	};
505eb4ea085SAngus Ainslie (Purism)
506eb4ea085SAngus Ainslie (Purism)	pinctrl_bt: btgrp {
507eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
508eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11	0x16 /* nBT_DISABLE */
509eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7	0x10 /* BT_HOST_WAKE */
510eb4ea085SAngus Ainslie (Purism)		>;
511eb4ea085SAngus Ainslie (Purism)	};
512eb4ea085SAngus Ainslie (Purism)
513eb4ea085SAngus Ainslie (Purism)	pinctrl_charger: chargergrp {
514eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
515eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x80 /* CHRG_nINT */
516eb4ea085SAngus Ainslie (Purism)		>;
517eb4ea085SAngus Ainslie (Purism)	};
518eb4ea085SAngus Ainslie (Purism)
519eb4ea085SAngus Ainslie (Purism)	pinctrl_fec1: fec1grp {
520eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
521eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
522eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
523eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
524eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
525eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
526eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
527eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
528eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
529eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
530eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
531eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
532eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
533eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
534eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
535eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
536eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x1f
537eb4ea085SAngus Ainslie (Purism)		>;
538eb4ea085SAngus Ainslie (Purism)	};
539eb4ea085SAngus Ainslie (Purism)
540eb4ea085SAngus Ainslie (Purism)	pinctrl_ts: tsgrp {
541eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
542eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0		0x16  /* TOUCH INT */
543eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19  /* TOUCH RST */
544eb4ea085SAngus Ainslie (Purism)		>;
545eb4ea085SAngus Ainslie (Purism)	};
546eb4ea085SAngus Ainslie (Purism)
547eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_leds: gpioledgrp {
548eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
549eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16
550eb4ea085SAngus Ainslie (Purism)		>;
551eb4ea085SAngus Ainslie (Purism)	};
552eb4ea085SAngus Ainslie (Purism)
553eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_keys: gpiokeygrp {
554eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
555eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x16
556eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22	0x16
557eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x180  /* HP_DET */
558eb4ea085SAngus Ainslie (Purism)		>;
559eb4ea085SAngus Ainslie (Purism)	};
560eb4ea085SAngus Ainslie (Purism)
561eb4ea085SAngus Ainslie (Purism)	pinctrl_haptic: hapticgrp {
562eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
563eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4		0xc6   /* nHAPTIC */
564eb4ea085SAngus Ainslie (Purism)		>;
565eb4ea085SAngus Ainslie (Purism)	};
566eb4ea085SAngus Ainslie (Purism)
567eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c1: i2c1grp {
568eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
569eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000001f
570eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000001f
571eb4ea085SAngus Ainslie (Purism)		>;
572eb4ea085SAngus Ainslie (Purism)	};
573eb4ea085SAngus Ainslie (Purism)
574eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c3: i2c3grp {
575eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
576eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x4000001f
577eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x4000001f
578eb4ea085SAngus Ainslie (Purism)		>;
579eb4ea085SAngus Ainslie (Purism)	};
580eb4ea085SAngus Ainslie (Purism)
581eb4ea085SAngus Ainslie (Purism)	pinctrl_imu: imugrp {
582eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
583eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x8  /* IMU_INT */
584eb4ea085SAngus Ainslie (Purism)		>;
585eb4ea085SAngus Ainslie (Purism)	};
586eb4ea085SAngus Ainslie (Purism)
587eb4ea085SAngus Ainslie (Purism)	pinctrl_pmic: pmicgrp {
588eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
589eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x80  /* PMIC intr */
590eb4ea085SAngus Ainslie (Purism)		>;
591eb4ea085SAngus Ainslie (Purism)	};
592eb4ea085SAngus Ainslie (Purism)
593ea38ca9aSGuido Günther	pinctrl_prox: proxgrp {
594ea38ca9aSGuido Günther		fsl,pins = <
595ea38ca9aSGuido Günther			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x80  /* prox intr */
596ea38ca9aSGuido Günther		>;
597ea38ca9aSGuido Günther	};
598ea38ca9aSGuido Günther
599eb4ea085SAngus Ainslie (Purism)	pinctrl_pwr_en: pwrengrp {
600eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
601eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x06
602eb4ea085SAngus Ainslie (Purism)		>;
603eb4ea085SAngus Ainslie (Purism)	};
604eb4ea085SAngus Ainslie (Purism)
605eb4ea085SAngus Ainslie (Purism)	pinctrl_rtc: rtcgrp {
606eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
607eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29	0x80  /* RTC intr */
608eb4ea085SAngus Ainslie (Purism)		>;
609eb4ea085SAngus Ainslie (Purism)	};
610eb4ea085SAngus Ainslie (Purism)
611c53f0166SAngus Ainslie (Purism)	pinctrl_sai2: sai2grp {
612c53f0166SAngus Ainslie (Purism)		fsl,pins = <
613c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
614c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
615c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
616c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6
617c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
618c53f0166SAngus Ainslie (Purism)		>;
619c53f0166SAngus Ainslie (Purism)	};
620c53f0166SAngus Ainslie (Purism)
621eb4ea085SAngus Ainslie (Purism)	pinctrl_typec: typecgrp {
622eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
623eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x16
624eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x80
625eb4ea085SAngus Ainslie (Purism)		>;
626eb4ea085SAngus Ainslie (Purism)	};
627eb4ea085SAngus Ainslie (Purism)
628eb4ea085SAngus Ainslie (Purism)	pinctrl_uart1: uart1grp {
629eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
630eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
631eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
632eb4ea085SAngus Ainslie (Purism)		>;
633eb4ea085SAngus Ainslie (Purism)	};
634eb4ea085SAngus Ainslie (Purism)
635eb4ea085SAngus Ainslie (Purism)	pinctrl_uart2: uart2grp {
636eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
637eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
638eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
639eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
640eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
641eb4ea085SAngus Ainslie (Purism)		>;
642eb4ea085SAngus Ainslie (Purism)	};
643eb4ea085SAngus Ainslie (Purism)
644eb4ea085SAngus Ainslie (Purism)	pinctrl_uart3: uart3grp {
645eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
646eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
647eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
648eb4ea085SAngus Ainslie (Purism)		>;
649eb4ea085SAngus Ainslie (Purism)	};
650eb4ea085SAngus Ainslie (Purism)
651eb4ea085SAngus Ainslie (Purism)	pinctrl_uart4: uart4grp {
652eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
653eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
654eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
655eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x49
656eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49
657eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x49
658eb4ea085SAngus Ainslie (Purism)		>;
659eb4ea085SAngus Ainslie (Purism)	};
660eb4ea085SAngus Ainslie (Purism)
661eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1: usdhc1grp {
662eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
663eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
664eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
665eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
666eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
667eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
668eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
669eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
670eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
671eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
672eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
673eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
674eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
675eb4ea085SAngus Ainslie (Purism)		>;
676eb4ea085SAngus Ainslie (Purism)	};
677eb4ea085SAngus Ainslie (Purism)
678eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
679eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
680eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
681eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
682eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
683eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
684eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
685eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
686eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
687eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
688eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
689eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
690eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
691eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
692eb4ea085SAngus Ainslie (Purism)		>;
693eb4ea085SAngus Ainslie (Purism)	};
694eb4ea085SAngus Ainslie (Purism)
695eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
696eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
697eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
698eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
699eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
700eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
701eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
702eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
703eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
704eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
705eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
706eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
707eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
708eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
709eb4ea085SAngus Ainslie (Purism)		>;
710eb4ea085SAngus Ainslie (Purism)	};
711eb4ea085SAngus Ainslie (Purism)
712eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_pwr: usdhc2grppwr {
713eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
714eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
715eb4ea085SAngus Ainslie (Purism)		>;
716eb4ea085SAngus Ainslie (Purism)	};
717eb4ea085SAngus Ainslie (Purism)
718eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_gpio: usdhc2grpgpio {
719eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
720eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */
721eb4ea085SAngus Ainslie (Purism)		>;
722eb4ea085SAngus Ainslie (Purism)	};
723eb4ea085SAngus Ainslie (Purism)
724eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2: usdhc2grp {
725eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
726eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
727eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
728eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
729eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
730eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
731eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
732eb4ea085SAngus Ainslie (Purism)		>;
733eb4ea085SAngus Ainslie (Purism)	};
734eb4ea085SAngus Ainslie (Purism)
735eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
736eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
737eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d
738eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd
739eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcd
740eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcd
741eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcd
742eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcd
743eb4ea085SAngus Ainslie (Purism)		>;
744eb4ea085SAngus Ainslie (Purism)	};
745eb4ea085SAngus Ainslie (Purism)
746eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
747eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
748eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f
749eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf
750eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcf
751eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcf
752eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcf
753eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcf
754eb4ea085SAngus Ainslie (Purism)		>;
755eb4ea085SAngus Ainslie (Purism)	};
756eb4ea085SAngus Ainslie (Purism)
757eb4ea085SAngus Ainslie (Purism)	pinctrl_wdog: wdoggrp {
758eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
759eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
760eb4ea085SAngus Ainslie (Purism)		>;
761eb4ea085SAngus Ainslie (Purism)	};
762eb4ea085SAngus Ainslie (Purism)
763eb4ea085SAngus Ainslie (Purism)	pinctrl_wifi_pwr_en: wifipwrengrp {
764eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
765eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5         0x06
766eb4ea085SAngus Ainslie (Purism)		>;
767eb4ea085SAngus Ainslie (Purism)	};
768eb4ea085SAngus Ainslie (Purism)
769eb4ea085SAngus Ainslie (Purism)	pinctrl_wwan: wwangrp {
770eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
771eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x09 /* nWWAN_DISABLE */
772eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80 /* nWoWWAN */
773eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9	0x19 /* WWAN_RESET */
774eb4ea085SAngus Ainslie (Purism)		>;
775eb4ea085SAngus Ainslie (Purism)	};
776eb4ea085SAngus Ainslie (Purism)};
777eb4ea085SAngus Ainslie (Purism)
778eb4ea085SAngus Ainslie (Purism)&pgc_gpu {
779eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck3_reg>;
780eb4ea085SAngus Ainslie (Purism)};
781eb4ea085SAngus Ainslie (Purism)
782eb4ea085SAngus Ainslie (Purism)&pgc_vpu {
783eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck4_reg>;
784eb4ea085SAngus Ainslie (Purism)};
785eb4ea085SAngus Ainslie (Purism)
786eb4ea085SAngus Ainslie (Purism)&pwm1 {
787eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
788eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_bl>;
789eb4ea085SAngus Ainslie (Purism)	status = "okay";
790eb4ea085SAngus Ainslie (Purism)};
791eb4ea085SAngus Ainslie (Purism)
79201407158SAngus Ainslie (Purism)&snvs_pwrkey {
79301407158SAngus Ainslie (Purism)	status = "okay";
79401407158SAngus Ainslie (Purism)};
795eb4ea085SAngus Ainslie (Purism)
796c53f0166SAngus Ainslie (Purism)&sai2 {
797c53f0166SAngus Ainslie (Purism)	pinctrl-names = "default";
798c53f0166SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai2>;
799c53f0166SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
800c53f0166SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
801c53f0166SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
802c53f0166SAngus Ainslie (Purism)	status = "okay";
803c53f0166SAngus Ainslie (Purism)};
804c53f0166SAngus Ainslie (Purism)
805eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */
806eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
807eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart1>;
808eb4ea085SAngus Ainslie (Purism)	status = "okay";
809eb4ea085SAngus Ainslie (Purism)};
810eb4ea085SAngus Ainslie (Purism)
811eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */
812eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
813eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart3>;
814eb4ea085SAngus Ainslie (Purism)	status = "okay";
815eb4ea085SAngus Ainslie (Purism)};
816eb4ea085SAngus Ainslie (Purism)
817eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */
818eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
819eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
820eb4ea085SAngus Ainslie (Purism)	uart-has-rtscts;
821eb4ea085SAngus Ainslie (Purism)	status = "okay";
822eb4ea085SAngus Ainslie (Purism)};
823eb4ea085SAngus Ainslie (Purism)
824eb4ea085SAngus Ainslie (Purism)&usb3_phy0 {
825dde061b8SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
826eb4ea085SAngus Ainslie (Purism)	status = "okay";
827eb4ea085SAngus Ainslie (Purism)};
828eb4ea085SAngus Ainslie (Purism)
829eb4ea085SAngus Ainslie (Purism)&usb3_phy1 {
830eb4ea085SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
831eb4ea085SAngus Ainslie (Purism)	status = "okay";
832eb4ea085SAngus Ainslie (Purism)};
833eb4ea085SAngus Ainslie (Purism)
834eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 {
835eb4ea085SAngus Ainslie (Purism)	#address-cells = <1>;
836eb4ea085SAngus Ainslie (Purism)	#size-cells = <0>;
837eb4ea085SAngus Ainslie (Purism)	dr_mode = "otg";
838eb4ea085SAngus Ainslie (Purism)	status = "okay";
839eb4ea085SAngus Ainslie (Purism)
840eb4ea085SAngus Ainslie (Purism)	port@0 {
841eb4ea085SAngus Ainslie (Purism)		reg = <0>;
842eb4ea085SAngus Ainslie (Purism)
843eb4ea085SAngus Ainslie (Purism)		typec_hs: endpoint {
844eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_hs>;
845eb4ea085SAngus Ainslie (Purism)		};
846eb4ea085SAngus Ainslie (Purism)	};
847eb4ea085SAngus Ainslie (Purism)
848eb4ea085SAngus Ainslie (Purism)	port@1 {
849eb4ea085SAngus Ainslie (Purism)		reg = <1>;
850eb4ea085SAngus Ainslie (Purism)
851eb4ea085SAngus Ainslie (Purism)		typec_ss: endpoint {
852eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_ss>;
853eb4ea085SAngus Ainslie (Purism)		};
854eb4ea085SAngus Ainslie (Purism)	};
855eb4ea085SAngus Ainslie (Purism)};
856eb4ea085SAngus Ainslie (Purism)
857eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 {
858eb4ea085SAngus Ainslie (Purism)	dr_mode = "host";
859eb4ea085SAngus Ainslie (Purism)	status = "okay";
860eb4ea085SAngus Ainslie (Purism)};
861eb4ea085SAngus Ainslie (Purism)
862eb4ea085SAngus Ainslie (Purism)&usdhc1 {
863e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
864e045f044SAnson Huang	assigned-clock-rates = <400000000>;
865eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
866eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc1>;
867eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
868eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
869eb4ea085SAngus Ainslie (Purism)	bus-width = <8>;
870eb4ea085SAngus Ainslie (Purism)	non-removable;
871eb4ea085SAngus Ainslie (Purism)	status = "okay";
872eb4ea085SAngus Ainslie (Purism)};
873eb4ea085SAngus Ainslie (Purism)
874eb4ea085SAngus Ainslie (Purism)&usdhc2 {
875e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
876e045f044SAnson Huang	assigned-clock-rates = <200000000>;
877eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
878eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc2>;
879eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
880eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
881eb4ea085SAngus Ainslie (Purism)	bus-width = <4>;
882eb4ea085SAngus Ainslie (Purism)	vmmc-supply = <&reg_usdhc2_vmmc>;
883eb4ea085SAngus Ainslie (Purism)	power-supply = <&wifi_pwr_en>;
884eb4ea085SAngus Ainslie (Purism)	non-removable;
885eb4ea085SAngus Ainslie (Purism)	disable-wp;
886eb4ea085SAngus Ainslie (Purism)	cap-sdio-irq;
887eb4ea085SAngus Ainslie (Purism)	keep-power-in-suspend;
888eb4ea085SAngus Ainslie (Purism)	wakeup-source;
889eb4ea085SAngus Ainslie (Purism)	status = "okay";
890eb4ea085SAngus Ainslie (Purism)};
891eb4ea085SAngus Ainslie (Purism)
892eb4ea085SAngus Ainslie (Purism)&wdog1 {
893eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
894eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_wdog>;
895eb4ea085SAngus Ainslie (Purism)	fsl,ext-reset-output;
896eb4ea085SAngus Ainslie (Purism)	status = "okay";
897eb4ea085SAngus Ainslie (Purism)};
898