1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+
2eb4ea085SAngus Ainslie (Purism)/*
3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC
4eb4ea085SAngus Ainslie (Purism) */
5eb4ea085SAngus Ainslie (Purism)
6eb4ea085SAngus Ainslie (Purism)/dts-v1/;
7eb4ea085SAngus Ainslie (Purism)
8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h"
9eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h"
10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h"
11eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi"
12eb4ea085SAngus Ainslie (Purism)
13eb4ea085SAngus Ainslie (Purism)/ {
14eb4ea085SAngus Ainslie (Purism)	model = "Purism Librem 5 devkit";
15eb4ea085SAngus Ainslie (Purism)	compatible = "purism,librem5-devkit", "fsl,imx8mq";
16eb4ea085SAngus Ainslie (Purism)
17eb4ea085SAngus Ainslie (Purism)	backlight_dsi: backlight-dsi {
18eb4ea085SAngus Ainslie (Purism)		compatible = "pwm-backlight";
19eb4ea085SAngus Ainslie (Purism)		/* 200 Hz for the PAM2841 */
20eb4ea085SAngus Ainslie (Purism)		pwms = <&pwm1 0 5000000>;
21eb4ea085SAngus Ainslie (Purism)		brightness-levels = <0 100>;
22eb4ea085SAngus Ainslie (Purism)		num-interpolated-steps = <100>;
23eb4ea085SAngus Ainslie (Purism)		/* Default brightness level (index into the array defined by */
24eb4ea085SAngus Ainslie (Purism)		/* the "brightness-levels" property) */
25eb4ea085SAngus Ainslie (Purism)		default-brightness-level = <0>;
26eb4ea085SAngus Ainslie (Purism)		power-supply = <&reg_22v4_p>;
27eb4ea085SAngus Ainslie (Purism)	};
28eb4ea085SAngus Ainslie (Purism)
29eb4ea085SAngus Ainslie (Purism)	chosen {
30eb4ea085SAngus Ainslie (Purism)		stdout-path = &uart1;
31eb4ea085SAngus Ainslie (Purism)	};
32eb4ea085SAngus Ainslie (Purism)
33eb4ea085SAngus Ainslie (Purism)	gpio-keys {
34eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-keys";
35eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
36eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_keys>;
37eb4ea085SAngus Ainslie (Purism)
38eb4ea085SAngus Ainslie (Purism)		btn1 {
39eb4ea085SAngus Ainslie (Purism)			label = "VOL_UP";
40eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
41eb4ea085SAngus Ainslie (Purism)			wakeup-source;
42eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEUP>;
43eb4ea085SAngus Ainslie (Purism)		};
44eb4ea085SAngus Ainslie (Purism)
45eb4ea085SAngus Ainslie (Purism)		btn2 {
46eb4ea085SAngus Ainslie (Purism)			label = "VOL_DOWN";
47eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
48eb4ea085SAngus Ainslie (Purism)			wakeup-source;
49eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEDOWN>;
50eb4ea085SAngus Ainslie (Purism)		};
51eb4ea085SAngus Ainslie (Purism)
52eb4ea085SAngus Ainslie (Purism)		hp-det {
53eb4ea085SAngus Ainslie (Purism)			label = "HP_DET";
54eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
55eb4ea085SAngus Ainslie (Purism)			wakeup-source;
56eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_HP>;
57eb4ea085SAngus Ainslie (Purism)		};
583ef506b3SAngus Ainslie (Purism)
593ef506b3SAngus Ainslie (Purism)		wwan-wake {
603ef506b3SAngus Ainslie (Purism)			label = "WWAN_WAKE";
613ef506b3SAngus Ainslie (Purism)			gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
623ef506b3SAngus Ainslie (Purism)			interrupt-parent = <&gpio3>;
633ef506b3SAngus Ainslie (Purism)			interrupts = <8 GPIO_ACTIVE_LOW>;
643ef506b3SAngus Ainslie (Purism)			wakeup-source;
653ef506b3SAngus Ainslie (Purism)			linux,code = <KEY_PHONE>;
663ef506b3SAngus Ainslie (Purism)		};
67eb4ea085SAngus Ainslie (Purism)	};
68eb4ea085SAngus Ainslie (Purism)
69eb4ea085SAngus Ainslie (Purism)	leds {
70eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-leds";
71eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
72eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_leds>;
73eb4ea085SAngus Ainslie (Purism)
74eb4ea085SAngus Ainslie (Purism)		led1 {
75eb4ea085SAngus Ainslie (Purism)			label = "LED 1";
76eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
77eb4ea085SAngus Ainslie (Purism)			default-state = "off";
78eb4ea085SAngus Ainslie (Purism)		};
79eb4ea085SAngus Ainslie (Purism)	};
80eb4ea085SAngus Ainslie (Purism)
81eb4ea085SAngus Ainslie (Purism)	pmic_osc: clock-pmic {
82eb4ea085SAngus Ainslie (Purism)		compatible = "fixed-clock";
83eb4ea085SAngus Ainslie (Purism)		#clock-cells = <0>;
84eb4ea085SAngus Ainslie (Purism)		clock-frequency = <32768>;
85eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_osc";
86eb4ea085SAngus Ainslie (Purism)	};
87eb4ea085SAngus Ainslie (Purism)
88eb4ea085SAngus Ainslie (Purism)	reg_1v8_p: regulator-1v8-p {
89eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
90eb4ea085SAngus Ainslie (Purism)		regulator-name = "1v8_p";
91eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <1800000>;
92eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <1800000>;
93eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
94eb4ea085SAngus Ainslie (Purism)	};
95eb4ea085SAngus Ainslie (Purism)
96eb4ea085SAngus Ainslie (Purism)	reg_2v8_p: regulator-2v8-p {
97eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
98eb4ea085SAngus Ainslie (Purism)		regulator-name = "2v8_p";
99eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <2800000>;
100eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <2800000>;
101eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
102eb4ea085SAngus Ainslie (Purism)	};
103eb4ea085SAngus Ainslie (Purism)
104eb4ea085SAngus Ainslie (Purism)	reg_3v3_p: regulator-3v3-p {
105eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
106eb4ea085SAngus Ainslie (Purism)		regulator-name = "3v3_p";
107eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
108eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
109eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
110eb4ea085SAngus Ainslie (Purism)
111eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
112eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
113eb4ea085SAngus Ainslie (Purism)		};
114eb4ea085SAngus Ainslie (Purism)	};
115eb4ea085SAngus Ainslie (Purism)
116eb4ea085SAngus Ainslie (Purism)	reg_5v_p: regulator-5v-p {
117eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
118eb4ea085SAngus Ainslie (Purism)		regulator-name = "5v_p";
119eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <5000000>;
120eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <5000000>;
121eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
122eb4ea085SAngus Ainslie (Purism)
123eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
124eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
125eb4ea085SAngus Ainslie (Purism)		};
126eb4ea085SAngus Ainslie (Purism)	};
127eb4ea085SAngus Ainslie (Purism)
128eb4ea085SAngus Ainslie (Purism)	reg_22v4_p: regulator-22v4-p  {
129eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
130eb4ea085SAngus Ainslie (Purism)		regulator-name = "22v4_P";
131eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <22400000>;
132eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <22400000>;
133eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
134eb4ea085SAngus Ainslie (Purism)	};
135eb4ea085SAngus Ainslie (Purism)
136eb4ea085SAngus Ainslie (Purism)	reg_pwr_en: regulator-pwr-en {
137eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
138eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
139eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pwr_en>;
140eb4ea085SAngus Ainslie (Purism)		regulator-name = "PWR_EN";
141eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
142eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
143eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
144eb4ea085SAngus Ainslie (Purism)		enable-active-high;
145eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
146eb4ea085SAngus Ainslie (Purism)	};
147eb4ea085SAngus Ainslie (Purism)
148eb4ea085SAngus Ainslie (Purism)	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
149eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
150eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
151eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_usdhc2_pwr>;
152eb4ea085SAngus Ainslie (Purism)		regulator-name = "VSD_3V3";
153eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
154eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
155eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
156eb4ea085SAngus Ainslie (Purism)		enable-active-high;
157eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
158eb4ea085SAngus Ainslie (Purism)	};
159eb4ea085SAngus Ainslie (Purism)
1607f7b7997SAngus Ainslie (Purism)	wwan_codec: sound-wwan-codec {
1617f7b7997SAngus Ainslie (Purism)		compatible = "option,gtm601";
1627f7b7997SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
1637f7b7997SAngus Ainslie (Purism)	};
1647f7b7997SAngus Ainslie (Purism)
165c53f0166SAngus Ainslie (Purism)	sound {
166c53f0166SAngus Ainslie (Purism)		compatible = "simple-audio-card";
167c53f0166SAngus Ainslie (Purism)		simple-audio-card,name = "sgtl5000";
168c53f0166SAngus Ainslie (Purism)		simple-audio-card,format = "i2s";
169c53f0166SAngus Ainslie (Purism)		simple-audio-card,widgets =
170c53f0166SAngus Ainslie (Purism)			"Microphone", "Microphone Jack",
171c53f0166SAngus Ainslie (Purism)			"Headphone", "Headphone Jack",
172c53f0166SAngus Ainslie (Purism)			"Speaker", "Speaker Ext",
173c53f0166SAngus Ainslie (Purism)			"Line", "Line In Jack";
174c53f0166SAngus Ainslie (Purism)		simple-audio-card,routing =
175c53f0166SAngus Ainslie (Purism)			"MIC_IN", "Microphone Jack",
176c53f0166SAngus Ainslie (Purism)			"Microphone Jack", "Mic Bias",
177c53f0166SAngus Ainslie (Purism)			"LINE_IN", "Line In Jack",
178c53f0166SAngus Ainslie (Purism)			"Headphone Jack", "HP_OUT",
179c53f0166SAngus Ainslie (Purism)			"Speaker Ext", "LINE_OUT";
180c53f0166SAngus Ainslie (Purism)
181c53f0166SAngus Ainslie (Purism)		simple-audio-card,cpu {
182c53f0166SAngus Ainslie (Purism)			sound-dai = <&sai2>;
183c53f0166SAngus Ainslie (Purism)		};
184c53f0166SAngus Ainslie (Purism)
185c53f0166SAngus Ainslie (Purism)		simple-audio-card,codec {
186c53f0166SAngus Ainslie (Purism)			sound-dai = <&sgtl5000>;
187c53f0166SAngus Ainslie (Purism)			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
188c53f0166SAngus Ainslie (Purism)			frame-master;
189c53f0166SAngus Ainslie (Purism)			bitclock-master;
190c53f0166SAngus Ainslie (Purism)		};
191c53f0166SAngus Ainslie (Purism)	};
192c53f0166SAngus Ainslie (Purism)
1937f7b7997SAngus Ainslie (Purism)	sound-wwan {
1947f7b7997SAngus Ainslie (Purism)		compatible = "simple-audio-card";
1957f7b7997SAngus Ainslie (Purism)		simple-audio-card,name = "SIMCom SIM7100";
1967f7b7997SAngus Ainslie (Purism)		simple-audio-card,format = "dsp_a";
1977f7b7997SAngus Ainslie (Purism)
1987f7b7997SAngus Ainslie (Purism)		simple-audio-card,cpu {
1997f7b7997SAngus Ainslie (Purism)			sound-dai = <&sai6>;
2007f7b7997SAngus Ainslie (Purism)		};
2017f7b7997SAngus Ainslie (Purism)
2027f7b7997SAngus Ainslie (Purism)		telephony_link_master: simple-audio-card,codec {
2037f7b7997SAngus Ainslie (Purism)			sound-dai = <&wwan_codec>;
2047f7b7997SAngus Ainslie (Purism)			frame-master;
2057f7b7997SAngus Ainslie (Purism)			bitclock-master;
2067f7b7997SAngus Ainslie (Purism)		};
2077f7b7997SAngus Ainslie (Purism)	};
2087f7b7997SAngus Ainslie (Purism)
209eb4ea085SAngus Ainslie (Purism)	vibrator {
210eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-vibrator";
211eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
212eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_haptic>;
213eb4ea085SAngus Ainslie (Purism)	        enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
214eb4ea085SAngus Ainslie (Purism)		vcc-supply = <&reg_3v3_p>;
215eb4ea085SAngus Ainslie (Purism)	};
216eb4ea085SAngus Ainslie (Purism)
217eb4ea085SAngus Ainslie (Purism)	wifi_pwr_en: regulator-wifi-en {
218eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
219eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
220eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
221eb4ea085SAngus Ainslie (Purism)		regulator-name = "WIFI_EN";
222eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
223eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
224eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
225eb4ea085SAngus Ainslie (Purism)		enable-active-high;
226eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
227eb4ea085SAngus Ainslie (Purism)	};
228eb4ea085SAngus Ainslie (Purism)};
229eb4ea085SAngus Ainslie (Purism)
230a2e47ba2SAngus Ainslie (Purism)&A53_0 {
231a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
232a2e47ba2SAngus Ainslie (Purism)};
233a2e47ba2SAngus Ainslie (Purism)
234a2e47ba2SAngus Ainslie (Purism)&A53_1 {
235a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
236a2e47ba2SAngus Ainslie (Purism)};
237a2e47ba2SAngus Ainslie (Purism)
238a2e47ba2SAngus Ainslie (Purism)&A53_2 {
239a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
240a2e47ba2SAngus Ainslie (Purism)};
241a2e47ba2SAngus Ainslie (Purism)
242a2e47ba2SAngus Ainslie (Purism)&A53_3 {
243a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
244a2e47ba2SAngus Ainslie (Purism)};
245a2e47ba2SAngus Ainslie (Purism)
246eb4ea085SAngus Ainslie (Purism)&clk {
247eb4ea085SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
248eb4ea085SAngus Ainslie (Purism)	assigned-clock-rates = <786432000>, <722534400>;
249eb4ea085SAngus Ainslie (Purism)};
250eb4ea085SAngus Ainslie (Purism)
2519d9005a5SGuido Günther&dphy {
2529d9005a5SGuido Günther	status = "okay";
2539d9005a5SGuido Günther};
2549d9005a5SGuido Günther
255eb4ea085SAngus Ainslie (Purism)&fec1 {
256eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
257eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_fec1>;
258eb4ea085SAngus Ainslie (Purism)	phy-mode = "rgmii-id";
259eb4ea085SAngus Ainslie (Purism)	phy-handle = <&ethphy0>;
260eb4ea085SAngus Ainslie (Purism)	fsl,magic-packet;
261eb4ea085SAngus Ainslie (Purism)	phy-supply = <&reg_3v3_p>;
262eb4ea085SAngus Ainslie (Purism)	status = "okay";
263eb4ea085SAngus Ainslie (Purism)
264eb4ea085SAngus Ainslie (Purism)	mdio {
265eb4ea085SAngus Ainslie (Purism)		#address-cells = <1>;
266eb4ea085SAngus Ainslie (Purism)		#size-cells = <0>;
267eb4ea085SAngus Ainslie (Purism)
268eb4ea085SAngus Ainslie (Purism)		ethphy0: ethernet-phy@1 {
269eb4ea085SAngus Ainslie (Purism)			compatible = "ethernet-phy-ieee802.3-c22";
270eb4ea085SAngus Ainslie (Purism)			reg = <1>;
271eb4ea085SAngus Ainslie (Purism)		};
272eb4ea085SAngus Ainslie (Purism)	};
273eb4ea085SAngus Ainslie (Purism)};
274eb4ea085SAngus Ainslie (Purism)
275eb4ea085SAngus Ainslie (Purism)&i2c1 {
276eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
277eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
278eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c1>;
279eb4ea085SAngus Ainslie (Purism)	status = "okay";
280eb4ea085SAngus Ainslie (Purism)
281eb4ea085SAngus Ainslie (Purism)	pmic: pmic@4b {
282eb4ea085SAngus Ainslie (Purism)		compatible = "rohm,bd71837";
283eb4ea085SAngus Ainslie (Purism)		reg = <0x4b>;
284eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
285eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pmic>;
286eb4ea085SAngus Ainslie (Purism)		clocks = <&pmic_osc>;
287eb4ea085SAngus Ainslie (Purism)		clock-names = "osc";
288eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_clk";
289eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio1>;
290eb4ea085SAngus Ainslie (Purism)		interrupts = <3 GPIO_ACTIVE_LOW>;
291eb4ea085SAngus Ainslie (Purism)		interrupt-names = "irq";
292eb4ea085SAngus Ainslie (Purism)		rohm,reset-snvs-powered;
293eb4ea085SAngus Ainslie (Purism)
294eb4ea085SAngus Ainslie (Purism)		regulators {
295eb4ea085SAngus Ainslie (Purism)			buck1_reg: BUCK1 {
296eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck1";
297eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
298eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
299eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
300eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
301eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <900000>;
302eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <850000>;
303eb4ea085SAngus Ainslie (Purism)				rohm,dvs-suspend-voltage = <800000>;
304eb4ea085SAngus Ainslie (Purism)			};
305eb4ea085SAngus Ainslie (Purism)
306eb4ea085SAngus Ainslie (Purism)			buck2_reg: BUCK2 {
307eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck2";
308eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
309eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
310eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
311eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
312eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
313eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <900000>;
314eb4ea085SAngus Ainslie (Purism)			};
315eb4ea085SAngus Ainslie (Purism)
316eb4ea085SAngus Ainslie (Purism)			buck3_reg: BUCK3 {
317eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck3";
318eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
319eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
320eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
321eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
322eb4ea085SAngus Ainslie (Purism)			};
323eb4ea085SAngus Ainslie (Purism)
324eb4ea085SAngus Ainslie (Purism)			buck4_reg: BUCK4 {
325eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck4";
326eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
327eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
328eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
329eb4ea085SAngus Ainslie (Purism)			};
330eb4ea085SAngus Ainslie (Purism)
331eb4ea085SAngus Ainslie (Purism)			buck5_reg: BUCK5 {
332eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck5";
333eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
334eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1350000>;
335eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
336eb4ea085SAngus Ainslie (Purism)			};
337eb4ea085SAngus Ainslie (Purism)
338eb4ea085SAngus Ainslie (Purism)			buck6_reg: BUCK6 {
339eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck6";
340eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
341eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
342eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
343eb4ea085SAngus Ainslie (Purism)			};
344eb4ea085SAngus Ainslie (Purism)
345eb4ea085SAngus Ainslie (Purism)			buck7_reg: BUCK7 {
346eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck7";
347eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1605000>;
348eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1995000>;
349eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
350eb4ea085SAngus Ainslie (Purism)			};
351eb4ea085SAngus Ainslie (Purism)
352eb4ea085SAngus Ainslie (Purism)			buck8_reg: BUCK8 {
353eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck8";
354eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <800000>;
355eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1400000>;
356eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
357eb4ea085SAngus Ainslie (Purism)			};
358eb4ea085SAngus Ainslie (Purism)
359eb4ea085SAngus Ainslie (Purism)			ldo1_reg: LDO1 {
360eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo1";
361eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
362eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
363eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
364eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
365eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
366eb4ea085SAngus Ainslie (Purism)			};
367eb4ea085SAngus Ainslie (Purism)
368eb4ea085SAngus Ainslie (Purism)			ldo2_reg: LDO2 {
369eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo2";
370eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
371eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <900000>;
372eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
373eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
374eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
375eb4ea085SAngus Ainslie (Purism)			};
376eb4ea085SAngus Ainslie (Purism)
377eb4ea085SAngus Ainslie (Purism)			ldo3_reg: LDO3 {
378eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo3";
379eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
380eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
381eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
382eb4ea085SAngus Ainslie (Purism)			};
383eb4ea085SAngus Ainslie (Purism)
384eb4ea085SAngus Ainslie (Purism)			ldo4_reg: LDO4 {
385eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo4";
386eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
387eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
388eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
389eb4ea085SAngus Ainslie (Purism)			};
390eb4ea085SAngus Ainslie (Purism)
391eb4ea085SAngus Ainslie (Purism)			ldo5_reg: LDO5 {
392eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo5";
393eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
394eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
395eb4ea085SAngus Ainslie (Purism)			};
396eb4ea085SAngus Ainslie (Purism)
397eb4ea085SAngus Ainslie (Purism)			ldo6_reg: LDO6 {
398eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo6";
399eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
400eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
401eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
402eb4ea085SAngus Ainslie (Purism)			};
403eb4ea085SAngus Ainslie (Purism)
404eb4ea085SAngus Ainslie (Purism)			ldo7_reg: LDO7 {
405eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo7";
406eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
407eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
408eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
409eb4ea085SAngus Ainslie (Purism)			};
410eb4ea085SAngus Ainslie (Purism)		};
411eb4ea085SAngus Ainslie (Purism)	};
412eb4ea085SAngus Ainslie (Purism)
413eb4ea085SAngus Ainslie (Purism)	typec_ptn5100: usb_typec@52 {
414eb4ea085SAngus Ainslie (Purism)		compatible = "nxp,ptn5110";
415eb4ea085SAngus Ainslie (Purism)		reg = <0x52>;
416eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
417eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_typec>;
418eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
419eb4ea085SAngus Ainslie (Purism)		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
420eb4ea085SAngus Ainslie (Purism)
421eb4ea085SAngus Ainslie (Purism)		connector {
422eb4ea085SAngus Ainslie (Purism)			compatible = "usb-c-connector";
423eb4ea085SAngus Ainslie (Purism)			label = "USB-C";
424eb4ea085SAngus Ainslie (Purism)			data-role = "dual";
425eb4ea085SAngus Ainslie (Purism)			power-role = "dual";
426eb4ea085SAngus Ainslie (Purism)			try-power-role = "sink";
427eb4ea085SAngus Ainslie (Purism)			source-pdos = <PDO_FIXED(5000, 2000,
428eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_USB_COMM |
429eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
430eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )>;
431eb4ea085SAngus Ainslie (Purism)			sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM |
432eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
433eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )
4348155b786SAngus Ainslie (Purism)			     PDO_VAR(5000, 3000, 3000)>;
435eb4ea085SAngus Ainslie (Purism)			op-sink-microwatt = <10000000>;
436eb4ea085SAngus Ainslie (Purism)
437eb4ea085SAngus Ainslie (Purism)			ports {
438eb4ea085SAngus Ainslie (Purism)				#address-cells = <1>;
439eb4ea085SAngus Ainslie (Purism)				#size-cells = <0>;
440eb4ea085SAngus Ainslie (Purism)
441eb4ea085SAngus Ainslie (Purism)				port@0 {
442eb4ea085SAngus Ainslie (Purism)					reg = <0>;
443eb4ea085SAngus Ainslie (Purism)
444eb4ea085SAngus Ainslie (Purism)					usb_con_hs: endpoint {
445eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_hs>;
446eb4ea085SAngus Ainslie (Purism)					};
447eb4ea085SAngus Ainslie (Purism)				};
448eb4ea085SAngus Ainslie (Purism)
449eb4ea085SAngus Ainslie (Purism)				port@1 {
450eb4ea085SAngus Ainslie (Purism)					reg = <1>;
451eb4ea085SAngus Ainslie (Purism)
452eb4ea085SAngus Ainslie (Purism)					usb_con_ss: endpoint {
453eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_ss>;
454eb4ea085SAngus Ainslie (Purism)					};
455eb4ea085SAngus Ainslie (Purism)				};
456eb4ea085SAngus Ainslie (Purism)			};
457eb4ea085SAngus Ainslie (Purism)		};
458eb4ea085SAngus Ainslie (Purism)	};
459eb4ea085SAngus Ainslie (Purism)
460eb4ea085SAngus Ainslie (Purism)	rtc@68 {
461eb4ea085SAngus Ainslie (Purism)		compatible = "microcrystal,rv4162";
462eb4ea085SAngus Ainslie (Purism)		reg = <0x68>;
463eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
464eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_rtc>;
465eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio4>;
466eb4ea085SAngus Ainslie (Purism)		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
467eb4ea085SAngus Ainslie (Purism)	};
468eb4ea085SAngus Ainslie (Purism)
469eb4ea085SAngus Ainslie (Purism)	charger@6b { /* bq25896 */
470eb4ea085SAngus Ainslie (Purism)		compatible = "ti,bq25890";
471eb4ea085SAngus Ainslie (Purism)		reg = <0x6b>;
472eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
473eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_charger>;
474eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
475eb4ea085SAngus Ainslie (Purism)		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
476eb4ea085SAngus Ainslie (Purism)		ti,battery-regulation-voltage = <4192000>; /* 4.192V */
477eb4ea085SAngus Ainslie (Purism)		ti,charge-current = <1600000>; /* 1.6A */
478eb4ea085SAngus Ainslie (Purism)		ti,termination-current = <66000>;  /* 66mA */
479eb4ea085SAngus Ainslie (Purism)		ti,precharge-current = <130000>; /* 130mA */
480eb4ea085SAngus Ainslie (Purism)		ti,minimum-sys-voltage = <3000000>; /* 3V */
481eb4ea085SAngus Ainslie (Purism)		ti,boost-voltage = <5000000>; /* 5V */
482eb4ea085SAngus Ainslie (Purism)		ti,boost-max-current = <50000>; /* 50mA */
483eb4ea085SAngus Ainslie (Purism)	};
484eb4ea085SAngus Ainslie (Purism)};
485eb4ea085SAngus Ainslie (Purism)
486eb4ea085SAngus Ainslie (Purism)&i2c3 {
487eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
488eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
489eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c3>;
490eb4ea085SAngus Ainslie (Purism)	status = "okay";
491eb4ea085SAngus Ainslie (Purism)
492eb4ea085SAngus Ainslie (Purism)	magnetometer@1e	{
493eb4ea085SAngus Ainslie (Purism)		compatible = "st,lsm9ds1-magn";
494eb4ea085SAngus Ainslie (Purism)		reg = <0x1e>;
495eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
496eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_imu>;
497eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
498106f7b3bSAngus Ainslie (Purism)		interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
499eb4ea085SAngus Ainslie (Purism)		vdd-supply = <&reg_3v3_p>;
500eb4ea085SAngus Ainslie (Purism)		vddio-supply = <&reg_3v3_p>;
501eb4ea085SAngus Ainslie (Purism)	};
502eb4ea085SAngus Ainslie (Purism)
503c53f0166SAngus Ainslie (Purism)	sgtl5000: audio-codec@a {
504c53f0166SAngus Ainslie (Purism)		compatible = "fsl,sgtl5000";
505c53f0166SAngus Ainslie (Purism)		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
506c53f0166SAngus Ainslie (Purism)		assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
507c53f0166SAngus Ainslie (Purism)		assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
508c53f0166SAngus Ainslie (Purism)		assigned-clock-rates = <24576000>;
509c53f0166SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
510c53f0166SAngus Ainslie (Purism)		reg = <0x0a>;
511c53f0166SAngus Ainslie (Purism)		VDDD-supply = <&reg_1v8_p>;
512c53f0166SAngus Ainslie (Purism)		VDDIO-supply = <&reg_3v3_p>;
513c53f0166SAngus Ainslie (Purism)		VDDA-supply = <&reg_3v3_p>;
514c53f0166SAngus Ainslie (Purism)	};
515c53f0166SAngus Ainslie (Purism)
516eb4ea085SAngus Ainslie (Purism)	touchscreen@5d {
517eb4ea085SAngus Ainslie (Purism)		compatible = "goodix,gt5688";
518eb4ea085SAngus Ainslie (Purism)		reg = <0x5d>;
519eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
520eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_ts>;
521eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
522eb4ea085SAngus Ainslie (Purism)		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
523eb4ea085SAngus Ainslie (Purism)		reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
524eb4ea085SAngus Ainslie (Purism)		irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
525eb4ea085SAngus Ainslie (Purism)		touchscreen-size-x = <720>;
526eb4ea085SAngus Ainslie (Purism)		touchscreen-size-y = <1440>;
527eb4ea085SAngus Ainslie (Purism)		AVDD28-supply = <&reg_2v8_p>;
528eb4ea085SAngus Ainslie (Purism)		VDDIO-supply = <&reg_1v8_p>;
529eb4ea085SAngus Ainslie (Purism)	};
530537c00e3SMartin Kepplinger
531ea38ca9aSGuido Günther	proximity-sensor@60 {
532ea38ca9aSGuido Günther		compatible = "vishay,vcnl4040";
533ea38ca9aSGuido Günther		reg = <0x60>;
534ea38ca9aSGuido Günther		pinctrl-0 = <&pinctrl_prox>;
535ea38ca9aSGuido Günther	};
536ea38ca9aSGuido Günther
537537c00e3SMartin Kepplinger	accel-gyro@6a {
538537c00e3SMartin Kepplinger		compatible = "st,lsm9ds1-imu";
539537c00e3SMartin Kepplinger		reg = <0x6a>;
540537c00e3SMartin Kepplinger		vdd-supply = <&reg_3v3_p>;
541537c00e3SMartin Kepplinger		vddio-supply = <&reg_3v3_p>;
542537c00e3SMartin Kepplinger	};
543eb4ea085SAngus Ainslie (Purism)};
544eb4ea085SAngus Ainslie (Purism)
545eb4ea085SAngus Ainslie (Purism)&iomuxc {
546eb4ea085SAngus Ainslie (Purism)	pinctrl_bl: blgrp {
547eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
548eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT	0x6 /* DSI_BL_PWM */
549eb4ea085SAngus Ainslie (Purism)		>;
550eb4ea085SAngus Ainslie (Purism)	};
551eb4ea085SAngus Ainslie (Purism)
552eb4ea085SAngus Ainslie (Purism)	pinctrl_bt: btgrp {
553eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
554eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11	0x16 /* nBT_DISABLE */
555eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7	0x10 /* BT_HOST_WAKE */
556eb4ea085SAngus Ainslie (Purism)		>;
557eb4ea085SAngus Ainslie (Purism)	};
558eb4ea085SAngus Ainslie (Purism)
559eb4ea085SAngus Ainslie (Purism)	pinctrl_charger: chargergrp {
560eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
561eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x80 /* CHRG_nINT */
562eb4ea085SAngus Ainslie (Purism)		>;
563eb4ea085SAngus Ainslie (Purism)	};
564eb4ea085SAngus Ainslie (Purism)
565eb4ea085SAngus Ainslie (Purism)	pinctrl_fec1: fec1grp {
566eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
567eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
568eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
569eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
570eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
571eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
572eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
573eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
574eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
575eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
576eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
577eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
578eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
579eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
580eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
581eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
582eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x1f
583eb4ea085SAngus Ainslie (Purism)		>;
584eb4ea085SAngus Ainslie (Purism)	};
585eb4ea085SAngus Ainslie (Purism)
586eb4ea085SAngus Ainslie (Purism)	pinctrl_ts: tsgrp {
587eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
588eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0		0x16  /* TOUCH INT */
589eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19  /* TOUCH RST */
590eb4ea085SAngus Ainslie (Purism)		>;
591eb4ea085SAngus Ainslie (Purism)	};
592eb4ea085SAngus Ainslie (Purism)
593eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_leds: gpioledgrp {
594eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
595eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16
596eb4ea085SAngus Ainslie (Purism)		>;
597eb4ea085SAngus Ainslie (Purism)	};
598eb4ea085SAngus Ainslie (Purism)
599eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_keys: gpiokeygrp {
600eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
601eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x16
602eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22	0x16
603eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x180  /* HP_DET */
6043ef506b3SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80   /* nWoWWAN */
605eb4ea085SAngus Ainslie (Purism)		>;
606eb4ea085SAngus Ainslie (Purism)	};
607eb4ea085SAngus Ainslie (Purism)
608eb4ea085SAngus Ainslie (Purism)	pinctrl_haptic: hapticgrp {
609eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
610eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4		0xc6   /* nHAPTIC */
611eb4ea085SAngus Ainslie (Purism)		>;
612eb4ea085SAngus Ainslie (Purism)	};
613eb4ea085SAngus Ainslie (Purism)
614eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c1: i2c1grp {
615eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
616eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000001f
617eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000001f
618eb4ea085SAngus Ainslie (Purism)		>;
619eb4ea085SAngus Ainslie (Purism)	};
620eb4ea085SAngus Ainslie (Purism)
621eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c3: i2c3grp {
622eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
623eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x4000001f
624eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x4000001f
625eb4ea085SAngus Ainslie (Purism)		>;
626eb4ea085SAngus Ainslie (Purism)	};
627eb4ea085SAngus Ainslie (Purism)
628eb4ea085SAngus Ainslie (Purism)	pinctrl_imu: imugrp {
629eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
630eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x8  /* IMU_INT */
631eb4ea085SAngus Ainslie (Purism)		>;
632eb4ea085SAngus Ainslie (Purism)	};
633eb4ea085SAngus Ainslie (Purism)
634eb4ea085SAngus Ainslie (Purism)	pinctrl_pmic: pmicgrp {
635eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
636eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x80  /* PMIC intr */
637eb4ea085SAngus Ainslie (Purism)		>;
638eb4ea085SAngus Ainslie (Purism)	};
639eb4ea085SAngus Ainslie (Purism)
640ea38ca9aSGuido Günther	pinctrl_prox: proxgrp {
641ea38ca9aSGuido Günther		fsl,pins = <
642ea38ca9aSGuido Günther			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x80  /* prox intr */
643ea38ca9aSGuido Günther		>;
644ea38ca9aSGuido Günther	};
645ea38ca9aSGuido Günther
646eb4ea085SAngus Ainslie (Purism)	pinctrl_pwr_en: pwrengrp {
647eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
648eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x06
649eb4ea085SAngus Ainslie (Purism)		>;
650eb4ea085SAngus Ainslie (Purism)	};
651eb4ea085SAngus Ainslie (Purism)
652eb4ea085SAngus Ainslie (Purism)	pinctrl_rtc: rtcgrp {
653eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
654eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29	0x80  /* RTC intr */
655eb4ea085SAngus Ainslie (Purism)		>;
656eb4ea085SAngus Ainslie (Purism)	};
657eb4ea085SAngus Ainslie (Purism)
658c53f0166SAngus Ainslie (Purism)	pinctrl_sai2: sai2grp {
659c53f0166SAngus Ainslie (Purism)		fsl,pins = <
660c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
661c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
662c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
663c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6
664c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
665c53f0166SAngus Ainslie (Purism)		>;
666c53f0166SAngus Ainslie (Purism)	};
667c53f0166SAngus Ainslie (Purism)
6687f7b7997SAngus Ainslie (Purism)	pinctrl_sai6: sai6grp {
6697f7b7997SAngus Ainslie (Purism)		fsl,pins = <
6707f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0	0xd6
6717f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC	0xd6
6727f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK     0xd6
6737f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0	0xd6
6747f7b7997SAngus Ainslie (Purism)		>;
6757f7b7997SAngus Ainslie (Purism)	};
6767f7b7997SAngus Ainslie (Purism)
677eb4ea085SAngus Ainslie (Purism)	pinctrl_typec: typecgrp {
678eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
679eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x16
680eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x80
681eb4ea085SAngus Ainslie (Purism)		>;
682eb4ea085SAngus Ainslie (Purism)	};
683eb4ea085SAngus Ainslie (Purism)
684eb4ea085SAngus Ainslie (Purism)	pinctrl_uart1: uart1grp {
685eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
686eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
687eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
688eb4ea085SAngus Ainslie (Purism)		>;
689eb4ea085SAngus Ainslie (Purism)	};
690eb4ea085SAngus Ainslie (Purism)
691eb4ea085SAngus Ainslie (Purism)	pinctrl_uart2: uart2grp {
692eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
693eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
694eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
695eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
696eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
697eb4ea085SAngus Ainslie (Purism)		>;
698eb4ea085SAngus Ainslie (Purism)	};
699eb4ea085SAngus Ainslie (Purism)
700eb4ea085SAngus Ainslie (Purism)	pinctrl_uart3: uart3grp {
701eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
702eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
703eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
704eb4ea085SAngus Ainslie (Purism)		>;
705eb4ea085SAngus Ainslie (Purism)	};
706eb4ea085SAngus Ainslie (Purism)
707eb4ea085SAngus Ainslie (Purism)	pinctrl_uart4: uart4grp {
708eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
709eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
710eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
711eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x49
712eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49
713eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x49
714eb4ea085SAngus Ainslie (Purism)		>;
715eb4ea085SAngus Ainslie (Purism)	};
716eb4ea085SAngus Ainslie (Purism)
717eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1: usdhc1grp {
718eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
719eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
720eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
721eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
722eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
723eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
724eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
725eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
726eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
727eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
728eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
729eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
730eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
731eb4ea085SAngus Ainslie (Purism)		>;
732eb4ea085SAngus Ainslie (Purism)	};
733eb4ea085SAngus Ainslie (Purism)
734eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
735eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
736eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
737eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
738eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
739eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
740eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
741eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
742eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
743eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
744eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
745eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
746eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
747eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
748eb4ea085SAngus Ainslie (Purism)		>;
749eb4ea085SAngus Ainslie (Purism)	};
750eb4ea085SAngus Ainslie (Purism)
751eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
752eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
753eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
754eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
755eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
756eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
757eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
758eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
759eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
760eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
761eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
762eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
763eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
764eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
765eb4ea085SAngus Ainslie (Purism)		>;
766eb4ea085SAngus Ainslie (Purism)	};
767eb4ea085SAngus Ainslie (Purism)
768eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_pwr: usdhc2grppwr {
769eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
770eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
771eb4ea085SAngus Ainslie (Purism)		>;
772eb4ea085SAngus Ainslie (Purism)	};
773eb4ea085SAngus Ainslie (Purism)
774eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_gpio: usdhc2grpgpio {
775eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
776eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */
777eb4ea085SAngus Ainslie (Purism)		>;
778eb4ea085SAngus Ainslie (Purism)	};
779eb4ea085SAngus Ainslie (Purism)
780eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2: usdhc2grp {
781eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
782eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
783eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
784eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
785eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
786eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
787eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
788eb4ea085SAngus Ainslie (Purism)		>;
789eb4ea085SAngus Ainslie (Purism)	};
790eb4ea085SAngus Ainslie (Purism)
791eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
792eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
793eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d
794eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd
795eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcd
796eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcd
797eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcd
798eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcd
799eb4ea085SAngus Ainslie (Purism)		>;
800eb4ea085SAngus Ainslie (Purism)	};
801eb4ea085SAngus Ainslie (Purism)
802eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
803eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
804eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f
805eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf
806eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcf
807eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcf
808eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcf
809eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcf
810eb4ea085SAngus Ainslie (Purism)		>;
811eb4ea085SAngus Ainslie (Purism)	};
812eb4ea085SAngus Ainslie (Purism)
813eb4ea085SAngus Ainslie (Purism)	pinctrl_wdog: wdoggrp {
814eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
815eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
816eb4ea085SAngus Ainslie (Purism)		>;
817eb4ea085SAngus Ainslie (Purism)	};
818eb4ea085SAngus Ainslie (Purism)
819eb4ea085SAngus Ainslie (Purism)	pinctrl_wifi_pwr_en: wifipwrengrp {
820eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
821eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5         0x06
822eb4ea085SAngus Ainslie (Purism)		>;
823eb4ea085SAngus Ainslie (Purism)	};
824eb4ea085SAngus Ainslie (Purism)
825eb4ea085SAngus Ainslie (Purism)	pinctrl_wwan: wwangrp {
826eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
827eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x09 /* nWWAN_DISABLE */
828eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80 /* nWoWWAN */
829eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9	0x19 /* WWAN_RESET */
830eb4ea085SAngus Ainslie (Purism)		>;
831eb4ea085SAngus Ainslie (Purism)	};
832eb4ea085SAngus Ainslie (Purism)};
833eb4ea085SAngus Ainslie (Purism)
834eb4ea085SAngus Ainslie (Purism)&pgc_gpu {
835eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck3_reg>;
836eb4ea085SAngus Ainslie (Purism)};
837eb4ea085SAngus Ainslie (Purism)
838eb4ea085SAngus Ainslie (Purism)&pgc_vpu {
839eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck4_reg>;
840eb4ea085SAngus Ainslie (Purism)};
841eb4ea085SAngus Ainslie (Purism)
842eb4ea085SAngus Ainslie (Purism)&pwm1 {
843eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
844eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_bl>;
845eb4ea085SAngus Ainslie (Purism)	status = "okay";
846eb4ea085SAngus Ainslie (Purism)};
847eb4ea085SAngus Ainslie (Purism)
84801407158SAngus Ainslie (Purism)&snvs_pwrkey {
84901407158SAngus Ainslie (Purism)	status = "okay";
85001407158SAngus Ainslie (Purism)};
851eb4ea085SAngus Ainslie (Purism)
852c53f0166SAngus Ainslie (Purism)&sai2 {
853c53f0166SAngus Ainslie (Purism)	pinctrl-names = "default";
854c53f0166SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai2>;
855c53f0166SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
856c53f0166SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
857c53f0166SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
858c53f0166SAngus Ainslie (Purism)	status = "okay";
859c53f0166SAngus Ainslie (Purism)};
860c53f0166SAngus Ainslie (Purism)
8617f7b7997SAngus Ainslie (Purism)&sai6 {
8627f7b7997SAngus Ainslie (Purism)	pinctrl-names = "default";
8637f7b7997SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai6>;
8647f7b7997SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI6>;
8657f7b7997SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
8667f7b7997SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
8677f7b7997SAngus Ainslie (Purism)	fsl,sai-synchronous-rx;
8687f7b7997SAngus Ainslie (Purism)	status = "okay";
8697f7b7997SAngus Ainslie (Purism)};
8707f7b7997SAngus Ainslie (Purism)
871eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */
872eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
873eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart1>;
874eb4ea085SAngus Ainslie (Purism)	status = "okay";
875eb4ea085SAngus Ainslie (Purism)};
876eb4ea085SAngus Ainslie (Purism)
877eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */
878eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
879eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart3>;
880eb4ea085SAngus Ainslie (Purism)	status = "okay";
881eb4ea085SAngus Ainslie (Purism)};
882eb4ea085SAngus Ainslie (Purism)
883eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */
884eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
885eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
886eb4ea085SAngus Ainslie (Purism)	uart-has-rtscts;
887eb4ea085SAngus Ainslie (Purism)	status = "okay";
888eb4ea085SAngus Ainslie (Purism)};
889eb4ea085SAngus Ainslie (Purism)
890eb4ea085SAngus Ainslie (Purism)&usb3_phy0 {
891dde061b8SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
892eb4ea085SAngus Ainslie (Purism)	status = "okay";
893eb4ea085SAngus Ainslie (Purism)};
894eb4ea085SAngus Ainslie (Purism)
895eb4ea085SAngus Ainslie (Purism)&usb3_phy1 {
896eb4ea085SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
897eb4ea085SAngus Ainslie (Purism)	status = "okay";
898eb4ea085SAngus Ainslie (Purism)};
899eb4ea085SAngus Ainslie (Purism)
900eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 {
901eb4ea085SAngus Ainslie (Purism)	#address-cells = <1>;
902eb4ea085SAngus Ainslie (Purism)	#size-cells = <0>;
903eb4ea085SAngus Ainslie (Purism)	dr_mode = "otg";
904eb4ea085SAngus Ainslie (Purism)	status = "okay";
905eb4ea085SAngus Ainslie (Purism)
906eb4ea085SAngus Ainslie (Purism)	port@0 {
907eb4ea085SAngus Ainslie (Purism)		reg = <0>;
908eb4ea085SAngus Ainslie (Purism)
909eb4ea085SAngus Ainslie (Purism)		typec_hs: endpoint {
910eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_hs>;
911eb4ea085SAngus Ainslie (Purism)		};
912eb4ea085SAngus Ainslie (Purism)	};
913eb4ea085SAngus Ainslie (Purism)
914eb4ea085SAngus Ainslie (Purism)	port@1 {
915eb4ea085SAngus Ainslie (Purism)		reg = <1>;
916eb4ea085SAngus Ainslie (Purism)
917eb4ea085SAngus Ainslie (Purism)		typec_ss: endpoint {
918eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_ss>;
919eb4ea085SAngus Ainslie (Purism)		};
920eb4ea085SAngus Ainslie (Purism)	};
921eb4ea085SAngus Ainslie (Purism)};
922eb4ea085SAngus Ainslie (Purism)
923eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 {
924eb4ea085SAngus Ainslie (Purism)	dr_mode = "host";
925eb4ea085SAngus Ainslie (Purism)	status = "okay";
926eb4ea085SAngus Ainslie (Purism)};
927eb4ea085SAngus Ainslie (Purism)
928eb4ea085SAngus Ainslie (Purism)&usdhc1 {
929e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
930e045f044SAnson Huang	assigned-clock-rates = <400000000>;
931eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
932eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc1>;
933eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
934eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
935eb4ea085SAngus Ainslie (Purism)	bus-width = <8>;
936eb4ea085SAngus Ainslie (Purism)	non-removable;
937eb4ea085SAngus Ainslie (Purism)	status = "okay";
938eb4ea085SAngus Ainslie (Purism)};
939eb4ea085SAngus Ainslie (Purism)
940eb4ea085SAngus Ainslie (Purism)&usdhc2 {
941e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
942e045f044SAnson Huang	assigned-clock-rates = <200000000>;
943eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
944eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc2>;
945eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
946eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
947eb4ea085SAngus Ainslie (Purism)	bus-width = <4>;
948eb4ea085SAngus Ainslie (Purism)	vmmc-supply = <&reg_usdhc2_vmmc>;
949eb4ea085SAngus Ainslie (Purism)	power-supply = <&wifi_pwr_en>;
950eb4ea085SAngus Ainslie (Purism)	non-removable;
951eb4ea085SAngus Ainslie (Purism)	disable-wp;
952eb4ea085SAngus Ainslie (Purism)	cap-sdio-irq;
953eb4ea085SAngus Ainslie (Purism)	keep-power-in-suspend;
954eb4ea085SAngus Ainslie (Purism)	wakeup-source;
955eb4ea085SAngus Ainslie (Purism)	status = "okay";
956eb4ea085SAngus Ainslie (Purism)};
957eb4ea085SAngus Ainslie (Purism)
958eb4ea085SAngus Ainslie (Purism)&wdog1 {
959eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
960eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_wdog>;
961eb4ea085SAngus Ainslie (Purism)	fsl,ext-reset-output;
962eb4ea085SAngus Ainslie (Purism)	status = "okay";
963eb4ea085SAngus Ainslie (Purism)};
964