1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+ 2eb4ea085SAngus Ainslie (Purism)/* 3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC 4eb4ea085SAngus Ainslie (Purism) */ 5eb4ea085SAngus Ainslie (Purism) 6eb4ea085SAngus Ainslie (Purism)/dts-v1/; 7eb4ea085SAngus Ainslie (Purism) 8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h" 9eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h" 10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h" 11eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi" 12eb4ea085SAngus Ainslie (Purism) 13eb4ea085SAngus Ainslie (Purism)/ { 14eb4ea085SAngus Ainslie (Purism) model = "Purism Librem 5 devkit"; 15eb4ea085SAngus Ainslie (Purism) compatible = "purism,librem5-devkit", "fsl,imx8mq"; 16eb4ea085SAngus Ainslie (Purism) 17eb4ea085SAngus Ainslie (Purism) backlight_dsi: backlight-dsi { 18eb4ea085SAngus Ainslie (Purism) compatible = "pwm-backlight"; 19eb4ea085SAngus Ainslie (Purism) /* 200 Hz for the PAM2841 */ 20eb4ea085SAngus Ainslie (Purism) pwms = <&pwm1 0 5000000>; 21eb4ea085SAngus Ainslie (Purism) brightness-levels = <0 100>; 22eb4ea085SAngus Ainslie (Purism) num-interpolated-steps = <100>; 23eb4ea085SAngus Ainslie (Purism) /* Default brightness level (index into the array defined by */ 24eb4ea085SAngus Ainslie (Purism) /* the "brightness-levels" property) */ 25eb4ea085SAngus Ainslie (Purism) default-brightness-level = <0>; 26eb4ea085SAngus Ainslie (Purism) power-supply = <®_22v4_p>; 27eb4ea085SAngus Ainslie (Purism) }; 28eb4ea085SAngus Ainslie (Purism) 29eb4ea085SAngus Ainslie (Purism) chosen { 30eb4ea085SAngus Ainslie (Purism) stdout-path = &uart1; 31eb4ea085SAngus Ainslie (Purism) }; 32eb4ea085SAngus Ainslie (Purism) 33eb4ea085SAngus Ainslie (Purism) gpio-keys { 34eb4ea085SAngus Ainslie (Purism) compatible = "gpio-keys"; 35eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 36eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_keys>; 37eb4ea085SAngus Ainslie (Purism) 38eb4ea085SAngus Ainslie (Purism) btn1 { 39eb4ea085SAngus Ainslie (Purism) label = "VOL_UP"; 40eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 41eb4ea085SAngus Ainslie (Purism) wakeup-source; 42eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEUP>; 43eb4ea085SAngus Ainslie (Purism) }; 44eb4ea085SAngus Ainslie (Purism) 45eb4ea085SAngus Ainslie (Purism) btn2 { 46eb4ea085SAngus Ainslie (Purism) label = "VOL_DOWN"; 47eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 48eb4ea085SAngus Ainslie (Purism) wakeup-source; 49eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEDOWN>; 50eb4ea085SAngus Ainslie (Purism) }; 51eb4ea085SAngus Ainslie (Purism) 52eb4ea085SAngus Ainslie (Purism) hp-det { 53eb4ea085SAngus Ainslie (Purism) label = "HP_DET"; 54eb4ea085SAngus Ainslie (Purism) gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 55eb4ea085SAngus Ainslie (Purism) wakeup-source; 56eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_HP>; 57eb4ea085SAngus Ainslie (Purism) }; 58eb4ea085SAngus Ainslie (Purism) }; 59eb4ea085SAngus Ainslie (Purism) 60eb4ea085SAngus Ainslie (Purism) leds { 61eb4ea085SAngus Ainslie (Purism) compatible = "gpio-leds"; 62eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 63eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_leds>; 64eb4ea085SAngus Ainslie (Purism) 65eb4ea085SAngus Ainslie (Purism) led1 { 66eb4ea085SAngus Ainslie (Purism) label = "LED 1"; 67eb4ea085SAngus Ainslie (Purism) gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 68eb4ea085SAngus Ainslie (Purism) default-state = "off"; 69eb4ea085SAngus Ainslie (Purism) }; 70eb4ea085SAngus Ainslie (Purism) }; 71eb4ea085SAngus Ainslie (Purism) 72eb4ea085SAngus Ainslie (Purism) pmic_osc: clock-pmic { 73eb4ea085SAngus Ainslie (Purism) compatible = "fixed-clock"; 74eb4ea085SAngus Ainslie (Purism) #clock-cells = <0>; 75eb4ea085SAngus Ainslie (Purism) clock-frequency = <32768>; 76eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_osc"; 77eb4ea085SAngus Ainslie (Purism) }; 78eb4ea085SAngus Ainslie (Purism) 79eb4ea085SAngus Ainslie (Purism) reg_1v8_p: regulator-1v8-p { 80eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 81eb4ea085SAngus Ainslie (Purism) regulator-name = "1v8_p"; 82eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 83eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 84eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 85eb4ea085SAngus Ainslie (Purism) }; 86eb4ea085SAngus Ainslie (Purism) 87eb4ea085SAngus Ainslie (Purism) reg_2v8_p: regulator-2v8-p { 88eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 89eb4ea085SAngus Ainslie (Purism) regulator-name = "2v8_p"; 90eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <2800000>; 91eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <2800000>; 92eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 93eb4ea085SAngus Ainslie (Purism) }; 94eb4ea085SAngus Ainslie (Purism) 95eb4ea085SAngus Ainslie (Purism) reg_3v3_p: regulator-3v3-p { 96eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 97eb4ea085SAngus Ainslie (Purism) regulator-name = "3v3_p"; 98eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 99eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 100eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 101eb4ea085SAngus Ainslie (Purism) 102eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 103eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 104eb4ea085SAngus Ainslie (Purism) }; 105eb4ea085SAngus Ainslie (Purism) }; 106eb4ea085SAngus Ainslie (Purism) 107eb4ea085SAngus Ainslie (Purism) reg_5v_p: regulator-5v-p { 108eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 109eb4ea085SAngus Ainslie (Purism) regulator-name = "5v_p"; 110eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <5000000>; 111eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <5000000>; 112eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 113eb4ea085SAngus Ainslie (Purism) 114eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 115eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 116eb4ea085SAngus Ainslie (Purism) }; 117eb4ea085SAngus Ainslie (Purism) }; 118eb4ea085SAngus Ainslie (Purism) 119eb4ea085SAngus Ainslie (Purism) reg_22v4_p: regulator-22v4-p { 120eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 121eb4ea085SAngus Ainslie (Purism) regulator-name = "22v4_P"; 122eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <22400000>; 123eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <22400000>; 124eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 125eb4ea085SAngus Ainslie (Purism) }; 126eb4ea085SAngus Ainslie (Purism) 127eb4ea085SAngus Ainslie (Purism) reg_pwr_en: regulator-pwr-en { 128eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 129eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 130eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pwr_en>; 131eb4ea085SAngus Ainslie (Purism) regulator-name = "PWR_EN"; 132eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 133eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 134eb4ea085SAngus Ainslie (Purism) gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 135eb4ea085SAngus Ainslie (Purism) enable-active-high; 136eb4ea085SAngus Ainslie (Purism) regulator-always-on; 137eb4ea085SAngus Ainslie (Purism) }; 138eb4ea085SAngus Ainslie (Purism) 139eb4ea085SAngus Ainslie (Purism) reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 140eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 141eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 142eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2_pwr>; 143eb4ea085SAngus Ainslie (Purism) regulator-name = "VSD_3V3"; 144eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 145eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 146eb4ea085SAngus Ainslie (Purism) gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 147eb4ea085SAngus Ainslie (Purism) enable-active-high; 148eb4ea085SAngus Ainslie (Purism) regulator-always-on; 149eb4ea085SAngus Ainslie (Purism) }; 150eb4ea085SAngus Ainslie (Purism) 1517f7b7997SAngus Ainslie (Purism) wwan_codec: sound-wwan-codec { 1527f7b7997SAngus Ainslie (Purism) compatible = "option,gtm601"; 1537f7b7997SAngus Ainslie (Purism) #sound-dai-cells = <0>; 1547f7b7997SAngus Ainslie (Purism) }; 1557f7b7997SAngus Ainslie (Purism) 156c53f0166SAngus Ainslie (Purism) sound { 157c53f0166SAngus Ainslie (Purism) compatible = "simple-audio-card"; 158c53f0166SAngus Ainslie (Purism) simple-audio-card,name = "sgtl5000"; 159c53f0166SAngus Ainslie (Purism) simple-audio-card,format = "i2s"; 160c53f0166SAngus Ainslie (Purism) simple-audio-card,widgets = 161c53f0166SAngus Ainslie (Purism) "Microphone", "Microphone Jack", 162c53f0166SAngus Ainslie (Purism) "Headphone", "Headphone Jack", 163c53f0166SAngus Ainslie (Purism) "Speaker", "Speaker Ext", 164c53f0166SAngus Ainslie (Purism) "Line", "Line In Jack"; 165c53f0166SAngus Ainslie (Purism) simple-audio-card,routing = 166c53f0166SAngus Ainslie (Purism) "MIC_IN", "Microphone Jack", 167c53f0166SAngus Ainslie (Purism) "Microphone Jack", "Mic Bias", 168c53f0166SAngus Ainslie (Purism) "LINE_IN", "Line In Jack", 169c53f0166SAngus Ainslie (Purism) "Headphone Jack", "HP_OUT", 170c53f0166SAngus Ainslie (Purism) "Speaker Ext", "LINE_OUT"; 171c53f0166SAngus Ainslie (Purism) 172c53f0166SAngus Ainslie (Purism) simple-audio-card,cpu { 173c53f0166SAngus Ainslie (Purism) sound-dai = <&sai2>; 174c53f0166SAngus Ainslie (Purism) }; 175c53f0166SAngus Ainslie (Purism) 176c53f0166SAngus Ainslie (Purism) simple-audio-card,codec { 177c53f0166SAngus Ainslie (Purism) sound-dai = <&sgtl5000>; 178c53f0166SAngus Ainslie (Purism) clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 179c53f0166SAngus Ainslie (Purism) frame-master; 180c53f0166SAngus Ainslie (Purism) bitclock-master; 181c53f0166SAngus Ainslie (Purism) }; 182c53f0166SAngus Ainslie (Purism) }; 183c53f0166SAngus Ainslie (Purism) 1847f7b7997SAngus Ainslie (Purism) sound-wwan { 1857f7b7997SAngus Ainslie (Purism) compatible = "simple-audio-card"; 1867f7b7997SAngus Ainslie (Purism) simple-audio-card,name = "SIMCom SIM7100"; 1877f7b7997SAngus Ainslie (Purism) simple-audio-card,format = "dsp_a"; 1887f7b7997SAngus Ainslie (Purism) 1897f7b7997SAngus Ainslie (Purism) simple-audio-card,cpu { 1907f7b7997SAngus Ainslie (Purism) sound-dai = <&sai6>; 1917f7b7997SAngus Ainslie (Purism) }; 1927f7b7997SAngus Ainslie (Purism) 1937f7b7997SAngus Ainslie (Purism) telephony_link_master: simple-audio-card,codec { 1947f7b7997SAngus Ainslie (Purism) sound-dai = <&wwan_codec>; 1957f7b7997SAngus Ainslie (Purism) frame-master; 1967f7b7997SAngus Ainslie (Purism) bitclock-master; 1977f7b7997SAngus Ainslie (Purism) }; 1987f7b7997SAngus Ainslie (Purism) }; 1997f7b7997SAngus Ainslie (Purism) 200eb4ea085SAngus Ainslie (Purism) vibrator { 201eb4ea085SAngus Ainslie (Purism) compatible = "gpio-vibrator"; 202eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 203eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_haptic>; 204eb4ea085SAngus Ainslie (Purism) enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; 205eb4ea085SAngus Ainslie (Purism) vcc-supply = <®_3v3_p>; 206eb4ea085SAngus Ainslie (Purism) }; 207eb4ea085SAngus Ainslie (Purism) 208eb4ea085SAngus Ainslie (Purism) wifi_pwr_en: regulator-wifi-en { 209eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 210eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 211eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wifi_pwr_en>; 212eb4ea085SAngus Ainslie (Purism) regulator-name = "WIFI_EN"; 213eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 214eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 215eb4ea085SAngus Ainslie (Purism) gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 216eb4ea085SAngus Ainslie (Purism) enable-active-high; 217eb4ea085SAngus Ainslie (Purism) regulator-always-on; 218eb4ea085SAngus Ainslie (Purism) }; 219eb4ea085SAngus Ainslie (Purism)}; 220eb4ea085SAngus Ainslie (Purism) 221eb4ea085SAngus Ainslie (Purism)&clk { 222eb4ea085SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; 223eb4ea085SAngus Ainslie (Purism) assigned-clock-rates = <786432000>, <722534400>; 224eb4ea085SAngus Ainslie (Purism)}; 225eb4ea085SAngus Ainslie (Purism) 2269d9005a5SGuido Günther&dphy { 2279d9005a5SGuido Günther status = "okay"; 2289d9005a5SGuido Günther}; 2299d9005a5SGuido Günther 230eb4ea085SAngus Ainslie (Purism)&fec1 { 231eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 232eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_fec1>; 233eb4ea085SAngus Ainslie (Purism) phy-mode = "rgmii-id"; 234eb4ea085SAngus Ainslie (Purism) phy-handle = <ðphy0>; 235eb4ea085SAngus Ainslie (Purism) fsl,magic-packet; 236eb4ea085SAngus Ainslie (Purism) phy-supply = <®_3v3_p>; 237eb4ea085SAngus Ainslie (Purism) status = "okay"; 238eb4ea085SAngus Ainslie (Purism) 239eb4ea085SAngus Ainslie (Purism) mdio { 240eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 241eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 242eb4ea085SAngus Ainslie (Purism) 243eb4ea085SAngus Ainslie (Purism) ethphy0: ethernet-phy@1 { 244eb4ea085SAngus Ainslie (Purism) compatible = "ethernet-phy-ieee802.3-c22"; 245eb4ea085SAngus Ainslie (Purism) reg = <1>; 246eb4ea085SAngus Ainslie (Purism) }; 247eb4ea085SAngus Ainslie (Purism) }; 248eb4ea085SAngus Ainslie (Purism)}; 249eb4ea085SAngus Ainslie (Purism) 250eb4ea085SAngus Ainslie (Purism)&i2c1 { 251eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 252eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 253eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c1>; 254eb4ea085SAngus Ainslie (Purism) status = "okay"; 255eb4ea085SAngus Ainslie (Purism) 256eb4ea085SAngus Ainslie (Purism) pmic: pmic@4b { 257eb4ea085SAngus Ainslie (Purism) compatible = "rohm,bd71837"; 258eb4ea085SAngus Ainslie (Purism) reg = <0x4b>; 259eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 260eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pmic>; 261eb4ea085SAngus Ainslie (Purism) clocks = <&pmic_osc>; 262eb4ea085SAngus Ainslie (Purism) clock-names = "osc"; 263eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_clk"; 264eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio1>; 265eb4ea085SAngus Ainslie (Purism) interrupts = <3 GPIO_ACTIVE_LOW>; 266eb4ea085SAngus Ainslie (Purism) interrupt-names = "irq"; 267eb4ea085SAngus Ainslie (Purism) rohm,reset-snvs-powered; 268eb4ea085SAngus Ainslie (Purism) 269eb4ea085SAngus Ainslie (Purism) regulators { 270eb4ea085SAngus Ainslie (Purism) buck1_reg: BUCK1 { 271eb4ea085SAngus Ainslie (Purism) regulator-name = "buck1"; 272eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 273eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 274eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 275eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 276eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <900000>; 277eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <850000>; 278eb4ea085SAngus Ainslie (Purism) rohm,dvs-suspend-voltage = <800000>; 279eb4ea085SAngus Ainslie (Purism) }; 280eb4ea085SAngus Ainslie (Purism) 281eb4ea085SAngus Ainslie (Purism) buck2_reg: BUCK2 { 282eb4ea085SAngus Ainslie (Purism) regulator-name = "buck2"; 283eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 284eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 285eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 286eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 287eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 288eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <900000>; 289eb4ea085SAngus Ainslie (Purism) }; 290eb4ea085SAngus Ainslie (Purism) 291eb4ea085SAngus Ainslie (Purism) buck3_reg: BUCK3 { 292eb4ea085SAngus Ainslie (Purism) regulator-name = "buck3"; 293eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 294eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 295eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 296eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 297eb4ea085SAngus Ainslie (Purism) }; 298eb4ea085SAngus Ainslie (Purism) 299eb4ea085SAngus Ainslie (Purism) buck4_reg: BUCK4 { 300eb4ea085SAngus Ainslie (Purism) regulator-name = "buck4"; 301eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 302eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 303eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 304eb4ea085SAngus Ainslie (Purism) }; 305eb4ea085SAngus Ainslie (Purism) 306eb4ea085SAngus Ainslie (Purism) buck5_reg: BUCK5 { 307eb4ea085SAngus Ainslie (Purism) regulator-name = "buck5"; 308eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 309eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1350000>; 310eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 311eb4ea085SAngus Ainslie (Purism) }; 312eb4ea085SAngus Ainslie (Purism) 313eb4ea085SAngus Ainslie (Purism) buck6_reg: BUCK6 { 314eb4ea085SAngus Ainslie (Purism) regulator-name = "buck6"; 315eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 316eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 317eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 318eb4ea085SAngus Ainslie (Purism) }; 319eb4ea085SAngus Ainslie (Purism) 320eb4ea085SAngus Ainslie (Purism) buck7_reg: BUCK7 { 321eb4ea085SAngus Ainslie (Purism) regulator-name = "buck7"; 322eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1605000>; 323eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1995000>; 324eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 325eb4ea085SAngus Ainslie (Purism) }; 326eb4ea085SAngus Ainslie (Purism) 327eb4ea085SAngus Ainslie (Purism) buck8_reg: BUCK8 { 328eb4ea085SAngus Ainslie (Purism) regulator-name = "buck8"; 329eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <800000>; 330eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1400000>; 331eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 332eb4ea085SAngus Ainslie (Purism) }; 333eb4ea085SAngus Ainslie (Purism) 334eb4ea085SAngus Ainslie (Purism) ldo1_reg: LDO1 { 335eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo1"; 336eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 337eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 338eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 339eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 340eb4ea085SAngus Ainslie (Purism) regulator-always-on; 341eb4ea085SAngus Ainslie (Purism) }; 342eb4ea085SAngus Ainslie (Purism) 343eb4ea085SAngus Ainslie (Purism) ldo2_reg: LDO2 { 344eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo2"; 345eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 346eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <900000>; 347eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 348eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 349eb4ea085SAngus Ainslie (Purism) regulator-always-on; 350eb4ea085SAngus Ainslie (Purism) }; 351eb4ea085SAngus Ainslie (Purism) 352eb4ea085SAngus Ainslie (Purism) ldo3_reg: LDO3 { 353eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo3"; 354eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 355eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 356eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 357eb4ea085SAngus Ainslie (Purism) }; 358eb4ea085SAngus Ainslie (Purism) 359eb4ea085SAngus Ainslie (Purism) ldo4_reg: LDO4 { 360eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo4"; 361eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 362eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 363eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 364eb4ea085SAngus Ainslie (Purism) }; 365eb4ea085SAngus Ainslie (Purism) 366eb4ea085SAngus Ainslie (Purism) ldo5_reg: LDO5 { 367eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo5"; 368eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 369eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 370eb4ea085SAngus Ainslie (Purism) }; 371eb4ea085SAngus Ainslie (Purism) 372eb4ea085SAngus Ainslie (Purism) ldo6_reg: LDO6 { 373eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo6"; 374eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 375eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 376eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 377eb4ea085SAngus Ainslie (Purism) }; 378eb4ea085SAngus Ainslie (Purism) 379eb4ea085SAngus Ainslie (Purism) ldo7_reg: LDO7 { 380eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo7"; 381eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 382eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 383eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 384eb4ea085SAngus Ainslie (Purism) }; 385eb4ea085SAngus Ainslie (Purism) }; 386eb4ea085SAngus Ainslie (Purism) }; 387eb4ea085SAngus Ainslie (Purism) 388eb4ea085SAngus Ainslie (Purism) typec_ptn5100: usb_typec@52 { 389eb4ea085SAngus Ainslie (Purism) compatible = "nxp,ptn5110"; 390eb4ea085SAngus Ainslie (Purism) reg = <0x52>; 391eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 392eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_typec>; 393eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 394eb4ea085SAngus Ainslie (Purism) interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 395eb4ea085SAngus Ainslie (Purism) 396eb4ea085SAngus Ainslie (Purism) connector { 397eb4ea085SAngus Ainslie (Purism) compatible = "usb-c-connector"; 398eb4ea085SAngus Ainslie (Purism) label = "USB-C"; 399eb4ea085SAngus Ainslie (Purism) data-role = "dual"; 400eb4ea085SAngus Ainslie (Purism) power-role = "dual"; 401eb4ea085SAngus Ainslie (Purism) try-power-role = "sink"; 402eb4ea085SAngus Ainslie (Purism) source-pdos = <PDO_FIXED(5000, 2000, 403eb4ea085SAngus Ainslie (Purism) PDO_FIXED_USB_COMM | 404eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 405eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP )>; 406eb4ea085SAngus Ainslie (Purism) sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM | 407eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 408eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP ) 4098155b786SAngus Ainslie (Purism) PDO_VAR(5000, 3000, 3000)>; 410eb4ea085SAngus Ainslie (Purism) op-sink-microwatt = <10000000>; 411eb4ea085SAngus Ainslie (Purism) 412eb4ea085SAngus Ainslie (Purism) ports { 413eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 414eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 415eb4ea085SAngus Ainslie (Purism) 416eb4ea085SAngus Ainslie (Purism) port@0 { 417eb4ea085SAngus Ainslie (Purism) reg = <0>; 418eb4ea085SAngus Ainslie (Purism) 419eb4ea085SAngus Ainslie (Purism) usb_con_hs: endpoint { 420eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_hs>; 421eb4ea085SAngus Ainslie (Purism) }; 422eb4ea085SAngus Ainslie (Purism) }; 423eb4ea085SAngus Ainslie (Purism) 424eb4ea085SAngus Ainslie (Purism) port@1 { 425eb4ea085SAngus Ainslie (Purism) reg = <1>; 426eb4ea085SAngus Ainslie (Purism) 427eb4ea085SAngus Ainslie (Purism) usb_con_ss: endpoint { 428eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_ss>; 429eb4ea085SAngus Ainslie (Purism) }; 430eb4ea085SAngus Ainslie (Purism) }; 431eb4ea085SAngus Ainslie (Purism) }; 432eb4ea085SAngus Ainslie (Purism) }; 433eb4ea085SAngus Ainslie (Purism) }; 434eb4ea085SAngus Ainslie (Purism) 435eb4ea085SAngus Ainslie (Purism) rtc@68 { 436eb4ea085SAngus Ainslie (Purism) compatible = "microcrystal,rv4162"; 437eb4ea085SAngus Ainslie (Purism) reg = <0x68>; 438eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 439eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_rtc>; 440eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio4>; 441eb4ea085SAngus Ainslie (Purism) interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 442eb4ea085SAngus Ainslie (Purism) }; 443eb4ea085SAngus Ainslie (Purism) 444eb4ea085SAngus Ainslie (Purism) charger@6b { /* bq25896 */ 445eb4ea085SAngus Ainslie (Purism) compatible = "ti,bq25890"; 446eb4ea085SAngus Ainslie (Purism) reg = <0x6b>; 447eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 448eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_charger>; 449eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 450eb4ea085SAngus Ainslie (Purism) interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 451eb4ea085SAngus Ainslie (Purism) ti,battery-regulation-voltage = <4192000>; /* 4.192V */ 452eb4ea085SAngus Ainslie (Purism) ti,charge-current = <1600000>; /* 1.6A */ 453eb4ea085SAngus Ainslie (Purism) ti,termination-current = <66000>; /* 66mA */ 454eb4ea085SAngus Ainslie (Purism) ti,precharge-current = <130000>; /* 130mA */ 455eb4ea085SAngus Ainslie (Purism) ti,minimum-sys-voltage = <3000000>; /* 3V */ 456eb4ea085SAngus Ainslie (Purism) ti,boost-voltage = <5000000>; /* 5V */ 457eb4ea085SAngus Ainslie (Purism) ti,boost-max-current = <50000>; /* 50mA */ 458eb4ea085SAngus Ainslie (Purism) }; 459eb4ea085SAngus Ainslie (Purism)}; 460eb4ea085SAngus Ainslie (Purism) 461eb4ea085SAngus Ainslie (Purism)&i2c3 { 462eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 463eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 464eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c3>; 465eb4ea085SAngus Ainslie (Purism) status = "okay"; 466eb4ea085SAngus Ainslie (Purism) 467eb4ea085SAngus Ainslie (Purism) magnetometer@1e { 468eb4ea085SAngus Ainslie (Purism) compatible = "st,lsm9ds1-magn"; 469eb4ea085SAngus Ainslie (Purism) reg = <0x1e>; 470eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 471eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_imu>; 472eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 473106f7b3bSAngus Ainslie (Purism) interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 474eb4ea085SAngus Ainslie (Purism) vdd-supply = <®_3v3_p>; 475eb4ea085SAngus Ainslie (Purism) vddio-supply = <®_3v3_p>; 476eb4ea085SAngus Ainslie (Purism) }; 477eb4ea085SAngus Ainslie (Purism) 478c53f0166SAngus Ainslie (Purism) sgtl5000: audio-codec@a { 479c53f0166SAngus Ainslie (Purism) compatible = "fsl,sgtl5000"; 480c53f0166SAngus Ainslie (Purism) clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 481c53f0166SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 482c53f0166SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 483c53f0166SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 484c53f0166SAngus Ainslie (Purism) #sound-dai-cells = <0>; 485c53f0166SAngus Ainslie (Purism) reg = <0x0a>; 486c53f0166SAngus Ainslie (Purism) VDDD-supply = <®_1v8_p>; 487c53f0166SAngus Ainslie (Purism) VDDIO-supply = <®_3v3_p>; 488c53f0166SAngus Ainslie (Purism) VDDA-supply = <®_3v3_p>; 489c53f0166SAngus Ainslie (Purism) }; 490c53f0166SAngus Ainslie (Purism) 491eb4ea085SAngus Ainslie (Purism) touchscreen@5d { 492eb4ea085SAngus Ainslie (Purism) compatible = "goodix,gt5688"; 493eb4ea085SAngus Ainslie (Purism) reg = <0x5d>; 494eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 495eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_ts>; 496eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 497eb4ea085SAngus Ainslie (Purism) interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 498eb4ea085SAngus Ainslie (Purism) reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 499eb4ea085SAngus Ainslie (Purism) irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 500eb4ea085SAngus Ainslie (Purism) touchscreen-size-x = <720>; 501eb4ea085SAngus Ainslie (Purism) touchscreen-size-y = <1440>; 502eb4ea085SAngus Ainslie (Purism) AVDD28-supply = <®_2v8_p>; 503eb4ea085SAngus Ainslie (Purism) VDDIO-supply = <®_1v8_p>; 504eb4ea085SAngus Ainslie (Purism) }; 505537c00e3SMartin Kepplinger 506ea38ca9aSGuido Günther proximity-sensor@60 { 507ea38ca9aSGuido Günther compatible = "vishay,vcnl4040"; 508ea38ca9aSGuido Günther reg = <0x60>; 509ea38ca9aSGuido Günther pinctrl-0 = <&pinctrl_prox>; 510ea38ca9aSGuido Günther }; 511ea38ca9aSGuido Günther 512537c00e3SMartin Kepplinger accel-gyro@6a { 513537c00e3SMartin Kepplinger compatible = "st,lsm9ds1-imu"; 514537c00e3SMartin Kepplinger reg = <0x6a>; 515537c00e3SMartin Kepplinger vdd-supply = <®_3v3_p>; 516537c00e3SMartin Kepplinger vddio-supply = <®_3v3_p>; 517537c00e3SMartin Kepplinger }; 518eb4ea085SAngus Ainslie (Purism)}; 519eb4ea085SAngus Ainslie (Purism) 520eb4ea085SAngus Ainslie (Purism)&iomuxc { 521eb4ea085SAngus Ainslie (Purism) pinctrl_bl: blgrp { 522eb4ea085SAngus Ainslie (Purism) fsl,pins = < 523eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */ 524eb4ea085SAngus Ainslie (Purism) >; 525eb4ea085SAngus Ainslie (Purism) }; 526eb4ea085SAngus Ainslie (Purism) 527eb4ea085SAngus Ainslie (Purism) pinctrl_bt: btgrp { 528eb4ea085SAngus Ainslie (Purism) fsl,pins = < 529eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */ 530eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */ 531eb4ea085SAngus Ainslie (Purism) >; 532eb4ea085SAngus Ainslie (Purism) }; 533eb4ea085SAngus Ainslie (Purism) 534eb4ea085SAngus Ainslie (Purism) pinctrl_charger: chargergrp { 535eb4ea085SAngus Ainslie (Purism) fsl,pins = < 536eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */ 537eb4ea085SAngus Ainslie (Purism) >; 538eb4ea085SAngus Ainslie (Purism) }; 539eb4ea085SAngus Ainslie (Purism) 540eb4ea085SAngus Ainslie (Purism) pinctrl_fec1: fec1grp { 541eb4ea085SAngus Ainslie (Purism) fsl,pins = < 542eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 543eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 544eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 545eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 546eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 547eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 548eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 549eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 550eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 551eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 552eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 553eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 554eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 555eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 556eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 557eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f 558eb4ea085SAngus Ainslie (Purism) >; 559eb4ea085SAngus Ainslie (Purism) }; 560eb4ea085SAngus Ainslie (Purism) 561eb4ea085SAngus Ainslie (Purism) pinctrl_ts: tsgrp { 562eb4ea085SAngus Ainslie (Purism) fsl,pins = < 563eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */ 564eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ 565eb4ea085SAngus Ainslie (Purism) >; 566eb4ea085SAngus Ainslie (Purism) }; 567eb4ea085SAngus Ainslie (Purism) 568eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_leds: gpioledgrp { 569eb4ea085SAngus Ainslie (Purism) fsl,pins = < 570eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 571eb4ea085SAngus Ainslie (Purism) >; 572eb4ea085SAngus Ainslie (Purism) }; 573eb4ea085SAngus Ainslie (Purism) 574eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_keys: gpiokeygrp { 575eb4ea085SAngus Ainslie (Purism) fsl,pins = < 576eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 577eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16 578eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */ 579eb4ea085SAngus Ainslie (Purism) >; 580eb4ea085SAngus Ainslie (Purism) }; 581eb4ea085SAngus Ainslie (Purism) 582eb4ea085SAngus Ainslie (Purism) pinctrl_haptic: hapticgrp { 583eb4ea085SAngus Ainslie (Purism) fsl,pins = < 584eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ 585eb4ea085SAngus Ainslie (Purism) >; 586eb4ea085SAngus Ainslie (Purism) }; 587eb4ea085SAngus Ainslie (Purism) 588eb4ea085SAngus Ainslie (Purism) pinctrl_i2c1: i2c1grp { 589eb4ea085SAngus Ainslie (Purism) fsl,pins = < 590eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f 591eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f 592eb4ea085SAngus Ainslie (Purism) >; 593eb4ea085SAngus Ainslie (Purism) }; 594eb4ea085SAngus Ainslie (Purism) 595eb4ea085SAngus Ainslie (Purism) pinctrl_i2c3: i2c3grp { 596eb4ea085SAngus Ainslie (Purism) fsl,pins = < 597eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f 598eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f 599eb4ea085SAngus Ainslie (Purism) >; 600eb4ea085SAngus Ainslie (Purism) }; 601eb4ea085SAngus Ainslie (Purism) 602eb4ea085SAngus Ainslie (Purism) pinctrl_imu: imugrp { 603eb4ea085SAngus Ainslie (Purism) fsl,pins = < 604eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */ 605eb4ea085SAngus Ainslie (Purism) >; 606eb4ea085SAngus Ainslie (Purism) }; 607eb4ea085SAngus Ainslie (Purism) 608eb4ea085SAngus Ainslie (Purism) pinctrl_pmic: pmicgrp { 609eb4ea085SAngus Ainslie (Purism) fsl,pins = < 610eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */ 611eb4ea085SAngus Ainslie (Purism) >; 612eb4ea085SAngus Ainslie (Purism) }; 613eb4ea085SAngus Ainslie (Purism) 614ea38ca9aSGuido Günther pinctrl_prox: proxgrp { 615ea38ca9aSGuido Günther fsl,pins = < 616ea38ca9aSGuido Günther MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */ 617ea38ca9aSGuido Günther >; 618ea38ca9aSGuido Günther }; 619ea38ca9aSGuido Günther 620eb4ea085SAngus Ainslie (Purism) pinctrl_pwr_en: pwrengrp { 621eb4ea085SAngus Ainslie (Purism) fsl,pins = < 622eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06 623eb4ea085SAngus Ainslie (Purism) >; 624eb4ea085SAngus Ainslie (Purism) }; 625eb4ea085SAngus Ainslie (Purism) 626eb4ea085SAngus Ainslie (Purism) pinctrl_rtc: rtcgrp { 627eb4ea085SAngus Ainslie (Purism) fsl,pins = < 628eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */ 629eb4ea085SAngus Ainslie (Purism) >; 630eb4ea085SAngus Ainslie (Purism) }; 631eb4ea085SAngus Ainslie (Purism) 632c53f0166SAngus Ainslie (Purism) pinctrl_sai2: sai2grp { 633c53f0166SAngus Ainslie (Purism) fsl,pins = < 634c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 635c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 636c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 637c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 638c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 639c53f0166SAngus Ainslie (Purism) >; 640c53f0166SAngus Ainslie (Purism) }; 641c53f0166SAngus Ainslie (Purism) 6427f7b7997SAngus Ainslie (Purism) pinctrl_sai6: sai6grp { 6437f7b7997SAngus Ainslie (Purism) fsl,pins = < 6447f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 6457f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 6467f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 6477f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 6487f7b7997SAngus Ainslie (Purism) >; 6497f7b7997SAngus Ainslie (Purism) }; 6507f7b7997SAngus Ainslie (Purism) 651eb4ea085SAngus Ainslie (Purism) pinctrl_typec: typecgrp { 652eb4ea085SAngus Ainslie (Purism) fsl,pins = < 653eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 654eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80 655eb4ea085SAngus Ainslie (Purism) >; 656eb4ea085SAngus Ainslie (Purism) }; 657eb4ea085SAngus Ainslie (Purism) 658eb4ea085SAngus Ainslie (Purism) pinctrl_uart1: uart1grp { 659eb4ea085SAngus Ainslie (Purism) fsl,pins = < 660eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 661eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 662eb4ea085SAngus Ainslie (Purism) >; 663eb4ea085SAngus Ainslie (Purism) }; 664eb4ea085SAngus Ainslie (Purism) 665eb4ea085SAngus Ainslie (Purism) pinctrl_uart2: uart2grp { 666eb4ea085SAngus Ainslie (Purism) fsl,pins = < 667eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 668eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 669eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 670eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 671eb4ea085SAngus Ainslie (Purism) >; 672eb4ea085SAngus Ainslie (Purism) }; 673eb4ea085SAngus Ainslie (Purism) 674eb4ea085SAngus Ainslie (Purism) pinctrl_uart3: uart3grp { 675eb4ea085SAngus Ainslie (Purism) fsl,pins = < 676eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 677eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 678eb4ea085SAngus Ainslie (Purism) >; 679eb4ea085SAngus Ainslie (Purism) }; 680eb4ea085SAngus Ainslie (Purism) 681eb4ea085SAngus Ainslie (Purism) pinctrl_uart4: uart4grp { 682eb4ea085SAngus Ainslie (Purism) fsl,pins = < 683eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 684eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 685eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 686eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 687eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49 688eb4ea085SAngus Ainslie (Purism) >; 689eb4ea085SAngus Ainslie (Purism) }; 690eb4ea085SAngus Ainslie (Purism) 691eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc1: usdhc1grp { 692eb4ea085SAngus Ainslie (Purism) fsl,pins = < 693eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 694eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 695eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 696eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 697eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 698eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 699eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 700eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 701eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 702eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 703eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 704eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 705eb4ea085SAngus Ainslie (Purism) >; 706eb4ea085SAngus Ainslie (Purism) }; 707eb4ea085SAngus Ainslie (Purism) 708eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 709eb4ea085SAngus Ainslie (Purism) fsl,pins = < 710eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 711eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 712eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 713eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 714eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 715eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 716eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 717eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 718eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 719eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 720eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 721eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 722eb4ea085SAngus Ainslie (Purism) >; 723eb4ea085SAngus Ainslie (Purism) }; 724eb4ea085SAngus Ainslie (Purism) 725eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 726eb4ea085SAngus Ainslie (Purism) fsl,pins = < 727eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 728eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 729eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 730eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 731eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 732eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 733eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 734eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 735eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 736eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 737eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 738eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 739eb4ea085SAngus Ainslie (Purism) >; 740eb4ea085SAngus Ainslie (Purism) }; 741eb4ea085SAngus Ainslie (Purism) 742eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2_pwr: usdhc2grppwr { 743eb4ea085SAngus Ainslie (Purism) fsl,pins = < 744eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 745eb4ea085SAngus Ainslie (Purism) >; 746eb4ea085SAngus Ainslie (Purism) }; 747eb4ea085SAngus Ainslie (Purism) 748eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2_gpio: usdhc2grpgpio { 749eb4ea085SAngus Ainslie (Purism) fsl,pins = < 750eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ 751eb4ea085SAngus Ainslie (Purism) >; 752eb4ea085SAngus Ainslie (Purism) }; 753eb4ea085SAngus Ainslie (Purism) 754eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2: usdhc2grp { 755eb4ea085SAngus Ainslie (Purism) fsl,pins = < 756eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 757eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 758eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 759eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 760eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 761eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 762eb4ea085SAngus Ainslie (Purism) >; 763eb4ea085SAngus Ainslie (Purism) }; 764eb4ea085SAngus Ainslie (Purism) 765eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 766eb4ea085SAngus Ainslie (Purism) fsl,pins = < 767eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 768eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 769eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 770eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 771eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 772eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 773eb4ea085SAngus Ainslie (Purism) >; 774eb4ea085SAngus Ainslie (Purism) }; 775eb4ea085SAngus Ainslie (Purism) 776eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 777eb4ea085SAngus Ainslie (Purism) fsl,pins = < 778eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 779eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf 780eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf 781eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf 782eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf 783eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf 784eb4ea085SAngus Ainslie (Purism) >; 785eb4ea085SAngus Ainslie (Purism) }; 786eb4ea085SAngus Ainslie (Purism) 787eb4ea085SAngus Ainslie (Purism) pinctrl_wdog: wdoggrp { 788eb4ea085SAngus Ainslie (Purism) fsl,pins = < 789eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 790eb4ea085SAngus Ainslie (Purism) >; 791eb4ea085SAngus Ainslie (Purism) }; 792eb4ea085SAngus Ainslie (Purism) 793eb4ea085SAngus Ainslie (Purism) pinctrl_wifi_pwr_en: wifipwrengrp { 794eb4ea085SAngus Ainslie (Purism) fsl,pins = < 795eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 796eb4ea085SAngus Ainslie (Purism) >; 797eb4ea085SAngus Ainslie (Purism) }; 798eb4ea085SAngus Ainslie (Purism) 799eb4ea085SAngus Ainslie (Purism) pinctrl_wwan: wwangrp { 800eb4ea085SAngus Ainslie (Purism) fsl,pins = < 801eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */ 802eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ 803eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */ 804eb4ea085SAngus Ainslie (Purism) >; 805eb4ea085SAngus Ainslie (Purism) }; 806eb4ea085SAngus Ainslie (Purism)}; 807eb4ea085SAngus Ainslie (Purism) 808eb4ea085SAngus Ainslie (Purism)&pgc_gpu { 809eb4ea085SAngus Ainslie (Purism) power-supply = <&buck3_reg>; 810eb4ea085SAngus Ainslie (Purism)}; 811eb4ea085SAngus Ainslie (Purism) 812eb4ea085SAngus Ainslie (Purism)&pgc_vpu { 813eb4ea085SAngus Ainslie (Purism) power-supply = <&buck4_reg>; 814eb4ea085SAngus Ainslie (Purism)}; 815eb4ea085SAngus Ainslie (Purism) 816eb4ea085SAngus Ainslie (Purism)&pwm1 { 817eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 818eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_bl>; 819eb4ea085SAngus Ainslie (Purism) status = "okay"; 820eb4ea085SAngus Ainslie (Purism)}; 821eb4ea085SAngus Ainslie (Purism) 82201407158SAngus Ainslie (Purism)&snvs_pwrkey { 82301407158SAngus Ainslie (Purism) status = "okay"; 82401407158SAngus Ainslie (Purism)}; 825eb4ea085SAngus Ainslie (Purism) 826c53f0166SAngus Ainslie (Purism)&sai2 { 827c53f0166SAngus Ainslie (Purism) pinctrl-names = "default"; 828c53f0166SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_sai2>; 829c53f0166SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 830c53f0166SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 831c53f0166SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 832c53f0166SAngus Ainslie (Purism) status = "okay"; 833c53f0166SAngus Ainslie (Purism)}; 834c53f0166SAngus Ainslie (Purism) 8357f7b7997SAngus Ainslie (Purism)&sai6 { 8367f7b7997SAngus Ainslie (Purism) pinctrl-names = "default"; 8377f7b7997SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_sai6>; 8387f7b7997SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; 8397f7b7997SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 8407f7b7997SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 8417f7b7997SAngus Ainslie (Purism) fsl,sai-synchronous-rx; 8427f7b7997SAngus Ainslie (Purism) status = "okay"; 8437f7b7997SAngus Ainslie (Purism)}; 8447f7b7997SAngus Ainslie (Purism) 845eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */ 846eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 847eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart1>; 848eb4ea085SAngus Ainslie (Purism) status = "okay"; 849eb4ea085SAngus Ainslie (Purism)}; 850eb4ea085SAngus Ainslie (Purism) 851eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */ 852eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 853eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart3>; 854eb4ea085SAngus Ainslie (Purism) status = "okay"; 855eb4ea085SAngus Ainslie (Purism)}; 856eb4ea085SAngus Ainslie (Purism) 857eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */ 858eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 859eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; 860eb4ea085SAngus Ainslie (Purism) uart-has-rtscts; 861eb4ea085SAngus Ainslie (Purism) status = "okay"; 862eb4ea085SAngus Ainslie (Purism)}; 863eb4ea085SAngus Ainslie (Purism) 864eb4ea085SAngus Ainslie (Purism)&usb3_phy0 { 865dde061b8SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 866eb4ea085SAngus Ainslie (Purism) status = "okay"; 867eb4ea085SAngus Ainslie (Purism)}; 868eb4ea085SAngus Ainslie (Purism) 869eb4ea085SAngus Ainslie (Purism)&usb3_phy1 { 870eb4ea085SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 871eb4ea085SAngus Ainslie (Purism) status = "okay"; 872eb4ea085SAngus Ainslie (Purism)}; 873eb4ea085SAngus Ainslie (Purism) 874eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 { 875eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 876eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 877eb4ea085SAngus Ainslie (Purism) dr_mode = "otg"; 878eb4ea085SAngus Ainslie (Purism) status = "okay"; 879eb4ea085SAngus Ainslie (Purism) 880eb4ea085SAngus Ainslie (Purism) port@0 { 881eb4ea085SAngus Ainslie (Purism) reg = <0>; 882eb4ea085SAngus Ainslie (Purism) 883eb4ea085SAngus Ainslie (Purism) typec_hs: endpoint { 884eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_hs>; 885eb4ea085SAngus Ainslie (Purism) }; 886eb4ea085SAngus Ainslie (Purism) }; 887eb4ea085SAngus Ainslie (Purism) 888eb4ea085SAngus Ainslie (Purism) port@1 { 889eb4ea085SAngus Ainslie (Purism) reg = <1>; 890eb4ea085SAngus Ainslie (Purism) 891eb4ea085SAngus Ainslie (Purism) typec_ss: endpoint { 892eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_ss>; 893eb4ea085SAngus Ainslie (Purism) }; 894eb4ea085SAngus Ainslie (Purism) }; 895eb4ea085SAngus Ainslie (Purism)}; 896eb4ea085SAngus Ainslie (Purism) 897eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 { 898eb4ea085SAngus Ainslie (Purism) dr_mode = "host"; 899eb4ea085SAngus Ainslie (Purism) status = "okay"; 900eb4ea085SAngus Ainslie (Purism)}; 901eb4ea085SAngus Ainslie (Purism) 902eb4ea085SAngus Ainslie (Purism)&usdhc1 { 903e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 904e045f044SAnson Huang assigned-clock-rates = <400000000>; 905eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 906eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc1>; 907eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 908eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 909eb4ea085SAngus Ainslie (Purism) bus-width = <8>; 910eb4ea085SAngus Ainslie (Purism) non-removable; 911eb4ea085SAngus Ainslie (Purism) status = "okay"; 912eb4ea085SAngus Ainslie (Purism)}; 913eb4ea085SAngus Ainslie (Purism) 914eb4ea085SAngus Ainslie (Purism)&usdhc2 { 915e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 916e045f044SAnson Huang assigned-clock-rates = <200000000>; 917eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 918eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2>; 919eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 920eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 921eb4ea085SAngus Ainslie (Purism) bus-width = <4>; 922eb4ea085SAngus Ainslie (Purism) vmmc-supply = <®_usdhc2_vmmc>; 923eb4ea085SAngus Ainslie (Purism) power-supply = <&wifi_pwr_en>; 924eb4ea085SAngus Ainslie (Purism) non-removable; 925eb4ea085SAngus Ainslie (Purism) disable-wp; 926eb4ea085SAngus Ainslie (Purism) cap-sdio-irq; 927eb4ea085SAngus Ainslie (Purism) keep-power-in-suspend; 928eb4ea085SAngus Ainslie (Purism) wakeup-source; 929eb4ea085SAngus Ainslie (Purism) status = "okay"; 930eb4ea085SAngus Ainslie (Purism)}; 931eb4ea085SAngus Ainslie (Purism) 932eb4ea085SAngus Ainslie (Purism)&wdog1 { 933eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 934eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wdog>; 935eb4ea085SAngus Ainslie (Purism) fsl,ext-reset-output; 936eb4ea085SAngus Ainslie (Purism) status = "okay"; 937eb4ea085SAngus Ainslie (Purism)}; 938