1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+ 2eb4ea085SAngus Ainslie (Purism)/* 3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC 4eb4ea085SAngus Ainslie (Purism) */ 5eb4ea085SAngus Ainslie (Purism) 6eb4ea085SAngus Ainslie (Purism)/dts-v1/; 7eb4ea085SAngus Ainslie (Purism) 8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h" 9d8fa4792SKrzysztof Kozlowski#include <dt-bindings/interrupt-controller/irq.h> 10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h" 11eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h" 12eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi" 13eb4ea085SAngus Ainslie (Purism) 14eb4ea085SAngus Ainslie (Purism)/ { 15eb4ea085SAngus Ainslie (Purism) model = "Purism Librem 5 devkit"; 16eb4ea085SAngus Ainslie (Purism) compatible = "purism,librem5-devkit", "fsl,imx8mq"; 17eb4ea085SAngus Ainslie (Purism) 18eb4ea085SAngus Ainslie (Purism) backlight_dsi: backlight-dsi { 19eb4ea085SAngus Ainslie (Purism) compatible = "pwm-backlight"; 20eb4ea085SAngus Ainslie (Purism) /* 200 Hz for the PAM2841 */ 21eb4ea085SAngus Ainslie (Purism) pwms = <&pwm1 0 5000000>; 22eb4ea085SAngus Ainslie (Purism) brightness-levels = <0 100>; 23eb4ea085SAngus Ainslie (Purism) num-interpolated-steps = <100>; 24eb4ea085SAngus Ainslie (Purism) /* Default brightness level (index into the array defined by */ 25eb4ea085SAngus Ainslie (Purism) /* the "brightness-levels" property) */ 26eb4ea085SAngus Ainslie (Purism) default-brightness-level = <0>; 27eb4ea085SAngus Ainslie (Purism) power-supply = <®_22v4_p>; 28eb4ea085SAngus Ainslie (Purism) }; 29eb4ea085SAngus Ainslie (Purism) 30eb4ea085SAngus Ainslie (Purism) chosen { 31eb4ea085SAngus Ainslie (Purism) stdout-path = &uart1; 32eb4ea085SAngus Ainslie (Purism) }; 33eb4ea085SAngus Ainslie (Purism) 34eb4ea085SAngus Ainslie (Purism) gpio-keys { 35eb4ea085SAngus Ainslie (Purism) compatible = "gpio-keys"; 36eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 37eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_keys>; 38eb4ea085SAngus Ainslie (Purism) 39eb4ea085SAngus Ainslie (Purism) btn1 { 40eb4ea085SAngus Ainslie (Purism) label = "VOL_UP"; 41eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 42eb4ea085SAngus Ainslie (Purism) wakeup-source; 43eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEUP>; 44eb4ea085SAngus Ainslie (Purism) }; 45eb4ea085SAngus Ainslie (Purism) 46eb4ea085SAngus Ainslie (Purism) btn2 { 47eb4ea085SAngus Ainslie (Purism) label = "VOL_DOWN"; 48eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 49eb4ea085SAngus Ainslie (Purism) wakeup-source; 50eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEDOWN>; 51eb4ea085SAngus Ainslie (Purism) }; 52eb4ea085SAngus Ainslie (Purism) 53eb4ea085SAngus Ainslie (Purism) hp-det { 54eb4ea085SAngus Ainslie (Purism) label = "HP_DET"; 55eb4ea085SAngus Ainslie (Purism) gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 56eb4ea085SAngus Ainslie (Purism) wakeup-source; 57eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_HP>; 58eb4ea085SAngus Ainslie (Purism) }; 593ef506b3SAngus Ainslie (Purism) 603ef506b3SAngus Ainslie (Purism) wwan-wake { 613ef506b3SAngus Ainslie (Purism) label = "WWAN_WAKE"; 623ef506b3SAngus Ainslie (Purism) gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; 633ef506b3SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 64d8fa4792SKrzysztof Kozlowski interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 653ef506b3SAngus Ainslie (Purism) wakeup-source; 663ef506b3SAngus Ainslie (Purism) linux,code = <KEY_PHONE>; 673ef506b3SAngus Ainslie (Purism) }; 68eb4ea085SAngus Ainslie (Purism) }; 69eb4ea085SAngus Ainslie (Purism) 70eb4ea085SAngus Ainslie (Purism) leds { 71eb4ea085SAngus Ainslie (Purism) compatible = "gpio-leds"; 72eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 73eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_leds>; 74eb4ea085SAngus Ainslie (Purism) 75eb4ea085SAngus Ainslie (Purism) led1 { 76eb4ea085SAngus Ainslie (Purism) label = "LED 1"; 77eb4ea085SAngus Ainslie (Purism) gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 78eb4ea085SAngus Ainslie (Purism) default-state = "off"; 79eb4ea085SAngus Ainslie (Purism) }; 80eb4ea085SAngus Ainslie (Purism) }; 81eb4ea085SAngus Ainslie (Purism) 82eb4ea085SAngus Ainslie (Purism) pmic_osc: clock-pmic { 83eb4ea085SAngus Ainslie (Purism) compatible = "fixed-clock"; 84eb4ea085SAngus Ainslie (Purism) #clock-cells = <0>; 85eb4ea085SAngus Ainslie (Purism) clock-frequency = <32768>; 86eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_osc"; 87eb4ea085SAngus Ainslie (Purism) }; 88eb4ea085SAngus Ainslie (Purism) 89eb4ea085SAngus Ainslie (Purism) reg_1v8_p: regulator-1v8-p { 90eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 91eb4ea085SAngus Ainslie (Purism) regulator-name = "1v8_p"; 92eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 93eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 94eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 95eb4ea085SAngus Ainslie (Purism) }; 96eb4ea085SAngus Ainslie (Purism) 97eb4ea085SAngus Ainslie (Purism) reg_2v8_p: regulator-2v8-p { 98eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 99eb4ea085SAngus Ainslie (Purism) regulator-name = "2v8_p"; 100eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <2800000>; 101eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <2800000>; 102eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 103eb4ea085SAngus Ainslie (Purism) }; 104eb4ea085SAngus Ainslie (Purism) 105eb4ea085SAngus Ainslie (Purism) reg_3v3_p: regulator-3v3-p { 106eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 107eb4ea085SAngus Ainslie (Purism) regulator-name = "3v3_p"; 108eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 109eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 110eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 111eb4ea085SAngus Ainslie (Purism) 112eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 113eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 114eb4ea085SAngus Ainslie (Purism) }; 115eb4ea085SAngus Ainslie (Purism) }; 116eb4ea085SAngus Ainslie (Purism) 117eb4ea085SAngus Ainslie (Purism) reg_5v_p: regulator-5v-p { 118eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 119eb4ea085SAngus Ainslie (Purism) regulator-name = "5v_p"; 120eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <5000000>; 121eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <5000000>; 122eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 123eb4ea085SAngus Ainslie (Purism) 124eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 125eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 126eb4ea085SAngus Ainslie (Purism) }; 127eb4ea085SAngus Ainslie (Purism) }; 128eb4ea085SAngus Ainslie (Purism) 129eb4ea085SAngus Ainslie (Purism) reg_22v4_p: regulator-22v4-p { 130eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 131eb4ea085SAngus Ainslie (Purism) regulator-name = "22v4_P"; 132eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <22400000>; 133eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <22400000>; 134eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 135eb4ea085SAngus Ainslie (Purism) }; 136eb4ea085SAngus Ainslie (Purism) 137eb4ea085SAngus Ainslie (Purism) reg_pwr_en: regulator-pwr-en { 138eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 139eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 140eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pwr_en>; 141eb4ea085SAngus Ainslie (Purism) regulator-name = "PWR_EN"; 142eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 143eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 144eb4ea085SAngus Ainslie (Purism) gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 145eb4ea085SAngus Ainslie (Purism) enable-active-high; 146eb4ea085SAngus Ainslie (Purism) regulator-always-on; 147eb4ea085SAngus Ainslie (Purism) }; 148eb4ea085SAngus Ainslie (Purism) 149eb4ea085SAngus Ainslie (Purism) reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 150eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 151eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 152eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2_pwr>; 153eb4ea085SAngus Ainslie (Purism) regulator-name = "VSD_3V3"; 154eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 155eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 156eb4ea085SAngus Ainslie (Purism) gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 157eb4ea085SAngus Ainslie (Purism) enable-active-high; 158eb4ea085SAngus Ainslie (Purism) regulator-always-on; 159eb4ea085SAngus Ainslie (Purism) }; 160eb4ea085SAngus Ainslie (Purism) 1617f7b7997SAngus Ainslie (Purism) wwan_codec: sound-wwan-codec { 1627f7b7997SAngus Ainslie (Purism) compatible = "option,gtm601"; 1637f7b7997SAngus Ainslie (Purism) #sound-dai-cells = <0>; 1647f7b7997SAngus Ainslie (Purism) }; 1657f7b7997SAngus Ainslie (Purism) 166c53f0166SAngus Ainslie (Purism) sound { 167c53f0166SAngus Ainslie (Purism) compatible = "simple-audio-card"; 168*6f46f7ffSGuido Günther simple-audio-card,aux-devs = <&speaker_amp>; 1695b65f39dSGuido Günther simple-audio-card,name = "Librem 5 Devkit"; 170c53f0166SAngus Ainslie (Purism) simple-audio-card,format = "i2s"; 171c53f0166SAngus Ainslie (Purism) simple-audio-card,widgets = 172c53f0166SAngus Ainslie (Purism) "Microphone", "Microphone Jack", 173c53f0166SAngus Ainslie (Purism) "Headphone", "Headphone Jack", 174*6f46f7ffSGuido Günther "Speaker", "Builtin Speaker", 175c53f0166SAngus Ainslie (Purism) "Line", "Line In Jack"; 176c53f0166SAngus Ainslie (Purism) simple-audio-card,routing = 177c53f0166SAngus Ainslie (Purism) "MIC_IN", "Microphone Jack", 178c53f0166SAngus Ainslie (Purism) "Microphone Jack", "Mic Bias", 179c53f0166SAngus Ainslie (Purism) "LINE_IN", "Line In Jack", 180c53f0166SAngus Ainslie (Purism) "Headphone Jack", "HP_OUT", 181*6f46f7ffSGuido Günther "Builtin Speaker", "Speaker Amp OUTR", 182*6f46f7ffSGuido Günther "Speaker Amp INR", "LINE_OUT"; 183c53f0166SAngus Ainslie (Purism) 184c53f0166SAngus Ainslie (Purism) simple-audio-card,cpu { 185c53f0166SAngus Ainslie (Purism) sound-dai = <&sai2>; 186c53f0166SAngus Ainslie (Purism) }; 187c53f0166SAngus Ainslie (Purism) 188c53f0166SAngus Ainslie (Purism) simple-audio-card,codec { 189c53f0166SAngus Ainslie (Purism) sound-dai = <&sgtl5000>; 190c53f0166SAngus Ainslie (Purism) clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 191c53f0166SAngus Ainslie (Purism) frame-master; 192c53f0166SAngus Ainslie (Purism) bitclock-master; 193c53f0166SAngus Ainslie (Purism) }; 194c53f0166SAngus Ainslie (Purism) }; 195c53f0166SAngus Ainslie (Purism) 1967f7b7997SAngus Ainslie (Purism) sound-wwan { 1977f7b7997SAngus Ainslie (Purism) compatible = "simple-audio-card"; 1987f7b7997SAngus Ainslie (Purism) simple-audio-card,name = "SIMCom SIM7100"; 1997f7b7997SAngus Ainslie (Purism) simple-audio-card,format = "dsp_a"; 2007f7b7997SAngus Ainslie (Purism) 2017f7b7997SAngus Ainslie (Purism) simple-audio-card,cpu { 2027f7b7997SAngus Ainslie (Purism) sound-dai = <&sai6>; 2037f7b7997SAngus Ainslie (Purism) }; 2047f7b7997SAngus Ainslie (Purism) 2057f7b7997SAngus Ainslie (Purism) telephony_link_master: simple-audio-card,codec { 2067f7b7997SAngus Ainslie (Purism) sound-dai = <&wwan_codec>; 2077f7b7997SAngus Ainslie (Purism) frame-master; 2087f7b7997SAngus Ainslie (Purism) bitclock-master; 2097f7b7997SAngus Ainslie (Purism) }; 2107f7b7997SAngus Ainslie (Purism) }; 2117f7b7997SAngus Ainslie (Purism) 212*6f46f7ffSGuido Günther speaker_amp: speaker-amp { 213*6f46f7ffSGuido Günther compatible = "simple-audio-amplifier"; 214*6f46f7ffSGuido Günther pinctrl-names = "default"; 215*6f46f7ffSGuido Günther pinctrl-0 = <&pinctrl_spkamp>; 216*6f46f7ffSGuido Günther VCC-supply = <®_3v3_p>; 217*6f46f7ffSGuido Günther sound-name-prefix = "Speaker Amp"; 218*6f46f7ffSGuido Günther enable-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 219*6f46f7ffSGuido Günther }; 220*6f46f7ffSGuido Günther 221eb4ea085SAngus Ainslie (Purism) vibrator { 222eb4ea085SAngus Ainslie (Purism) compatible = "gpio-vibrator"; 223eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 224eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_haptic>; 225eb4ea085SAngus Ainslie (Purism) enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; 226eb4ea085SAngus Ainslie (Purism) vcc-supply = <®_3v3_p>; 227eb4ea085SAngus Ainslie (Purism) }; 228eb4ea085SAngus Ainslie (Purism) 229eb4ea085SAngus Ainslie (Purism) wifi_pwr_en: regulator-wifi-en { 230eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 231eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 232eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wifi_pwr_en>; 233eb4ea085SAngus Ainslie (Purism) regulator-name = "WIFI_EN"; 234eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 235eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 236eb4ea085SAngus Ainslie (Purism) gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 237eb4ea085SAngus Ainslie (Purism) enable-active-high; 238eb4ea085SAngus Ainslie (Purism) regulator-always-on; 239eb4ea085SAngus Ainslie (Purism) }; 240eb4ea085SAngus Ainslie (Purism)}; 241eb4ea085SAngus Ainslie (Purism) 242a2e47ba2SAngus Ainslie (Purism)&A53_0 { 243a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 244a2e47ba2SAngus Ainslie (Purism)}; 245a2e47ba2SAngus Ainslie (Purism) 246a2e47ba2SAngus Ainslie (Purism)&A53_1 { 247a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 248a2e47ba2SAngus Ainslie (Purism)}; 249a2e47ba2SAngus Ainslie (Purism) 250a2e47ba2SAngus Ainslie (Purism)&A53_2 { 251a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 252a2e47ba2SAngus Ainslie (Purism)}; 253a2e47ba2SAngus Ainslie (Purism) 254a2e47ba2SAngus Ainslie (Purism)&A53_3 { 255a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 256a2e47ba2SAngus Ainslie (Purism)}; 257a2e47ba2SAngus Ainslie (Purism) 2589d9005a5SGuido Günther&dphy { 2599d9005a5SGuido Günther status = "okay"; 2609d9005a5SGuido Günther}; 2619d9005a5SGuido Günther 262eb4ea085SAngus Ainslie (Purism)&fec1 { 263eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 264eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_fec1>; 265eb4ea085SAngus Ainslie (Purism) phy-mode = "rgmii-id"; 266eb4ea085SAngus Ainslie (Purism) phy-handle = <ðphy0>; 267eb4ea085SAngus Ainslie (Purism) fsl,magic-packet; 268eb4ea085SAngus Ainslie (Purism) phy-supply = <®_3v3_p>; 269eb4ea085SAngus Ainslie (Purism) status = "okay"; 270eb4ea085SAngus Ainslie (Purism) 271eb4ea085SAngus Ainslie (Purism) mdio { 272eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 273eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 274eb4ea085SAngus Ainslie (Purism) 275eb4ea085SAngus Ainslie (Purism) ethphy0: ethernet-phy@1 { 276eb4ea085SAngus Ainslie (Purism) compatible = "ethernet-phy-ieee802.3-c22"; 277eb4ea085SAngus Ainslie (Purism) reg = <1>; 278eb4ea085SAngus Ainslie (Purism) }; 279eb4ea085SAngus Ainslie (Purism) }; 280eb4ea085SAngus Ainslie (Purism)}; 281eb4ea085SAngus Ainslie (Purism) 282eb4ea085SAngus Ainslie (Purism)&i2c1 { 283eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 284eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 285eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c1>; 286eb4ea085SAngus Ainslie (Purism) status = "okay"; 287eb4ea085SAngus Ainslie (Purism) 288eb4ea085SAngus Ainslie (Purism) pmic: pmic@4b { 289eb4ea085SAngus Ainslie (Purism) compatible = "rohm,bd71837"; 290eb4ea085SAngus Ainslie (Purism) reg = <0x4b>; 291eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 292eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pmic>; 293eb4ea085SAngus Ainslie (Purism) clocks = <&pmic_osc>; 294eb4ea085SAngus Ainslie (Purism) clock-names = "osc"; 295a4a3550eSKrzysztof Kozlowski #clock-cells = <0>; 296eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_clk"; 297eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio1>; 298d8fa4792SKrzysztof Kozlowski interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 299eb4ea085SAngus Ainslie (Purism) rohm,reset-snvs-powered; 300eb4ea085SAngus Ainslie (Purism) 301eb4ea085SAngus Ainslie (Purism) regulators { 302eb4ea085SAngus Ainslie (Purism) buck1_reg: BUCK1 { 303eb4ea085SAngus Ainslie (Purism) regulator-name = "buck1"; 304eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 305eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 306eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 307edb93de4SGuido Günther regulator-always-on; 308eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 309eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <900000>; 310eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <850000>; 311eb4ea085SAngus Ainslie (Purism) rohm,dvs-suspend-voltage = <800000>; 312eb4ea085SAngus Ainslie (Purism) }; 313eb4ea085SAngus Ainslie (Purism) 314eb4ea085SAngus Ainslie (Purism) buck2_reg: BUCK2 { 315eb4ea085SAngus Ainslie (Purism) regulator-name = "buck2"; 316eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 317eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 318eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 319eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 320eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 321eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <900000>; 322eb4ea085SAngus Ainslie (Purism) }; 323eb4ea085SAngus Ainslie (Purism) 324eb4ea085SAngus Ainslie (Purism) buck3_reg: BUCK3 { 325eb4ea085SAngus Ainslie (Purism) regulator-name = "buck3"; 326eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 327eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 328eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 32976eceb0fSGuido Günther rohm,dvs-run-voltage = <900000>; 330eb4ea085SAngus Ainslie (Purism) }; 331eb4ea085SAngus Ainslie (Purism) 332eb4ea085SAngus Ainslie (Purism) buck4_reg: BUCK4 { 333eb4ea085SAngus Ainslie (Purism) regulator-name = "buck4"; 334eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 335eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 336eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 337eb4ea085SAngus Ainslie (Purism) }; 338eb4ea085SAngus Ainslie (Purism) 339eb4ea085SAngus Ainslie (Purism) buck5_reg: BUCK5 { 340eb4ea085SAngus Ainslie (Purism) regulator-name = "buck5"; 341eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 342eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1350000>; 343eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 344edb93de4SGuido Günther regulator-always-on; 345eb4ea085SAngus Ainslie (Purism) }; 346eb4ea085SAngus Ainslie (Purism) 347eb4ea085SAngus Ainslie (Purism) buck6_reg: BUCK6 { 348eb4ea085SAngus Ainslie (Purism) regulator-name = "buck6"; 349eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 350eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 351eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 352edb93de4SGuido Günther regulator-always-on; 353eb4ea085SAngus Ainslie (Purism) }; 354eb4ea085SAngus Ainslie (Purism) 355eb4ea085SAngus Ainslie (Purism) buck7_reg: BUCK7 { 356eb4ea085SAngus Ainslie (Purism) regulator-name = "buck7"; 357eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1605000>; 358eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1995000>; 359eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 360edb93de4SGuido Günther regulator-always-on; 361eb4ea085SAngus Ainslie (Purism) }; 362eb4ea085SAngus Ainslie (Purism) 363eb4ea085SAngus Ainslie (Purism) buck8_reg: BUCK8 { 364eb4ea085SAngus Ainslie (Purism) regulator-name = "buck8"; 365eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <800000>; 366eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1400000>; 367eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 368edb93de4SGuido Günther regulator-always-on; 369eb4ea085SAngus Ainslie (Purism) }; 370eb4ea085SAngus Ainslie (Purism) 371eb4ea085SAngus Ainslie (Purism) ldo1_reg: LDO1 { 372eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo1"; 373eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 374eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 375eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 376eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 377eb4ea085SAngus Ainslie (Purism) regulator-always-on; 378eb4ea085SAngus Ainslie (Purism) }; 379eb4ea085SAngus Ainslie (Purism) 380eb4ea085SAngus Ainslie (Purism) ldo2_reg: LDO2 { 381eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo2"; 382eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 383eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <900000>; 384eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 385eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 386eb4ea085SAngus Ainslie (Purism) regulator-always-on; 387eb4ea085SAngus Ainslie (Purism) }; 388eb4ea085SAngus Ainslie (Purism) 389eb4ea085SAngus Ainslie (Purism) ldo3_reg: LDO3 { 390eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo3"; 391eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 392eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 393eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 394edb93de4SGuido Günther regulator-always-on; 395eb4ea085SAngus Ainslie (Purism) }; 396eb4ea085SAngus Ainslie (Purism) 397eb4ea085SAngus Ainslie (Purism) ldo4_reg: LDO4 { 398eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo4"; 399eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 400eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 401eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 402edb93de4SGuido Günther regulator-always-on; 403eb4ea085SAngus Ainslie (Purism) }; 404eb4ea085SAngus Ainslie (Purism) 405eb4ea085SAngus Ainslie (Purism) ldo5_reg: LDO5 { 406eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo5"; 407eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 408eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 409edb93de4SGuido Günther regulator-always-on; 410eb4ea085SAngus Ainslie (Purism) }; 411eb4ea085SAngus Ainslie (Purism) 412eb4ea085SAngus Ainslie (Purism) ldo6_reg: LDO6 { 413eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo6"; 414eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 415eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 416eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 417edb93de4SGuido Günther regulator-always-on; 418eb4ea085SAngus Ainslie (Purism) }; 419eb4ea085SAngus Ainslie (Purism) 420eb4ea085SAngus Ainslie (Purism) ldo7_reg: LDO7 { 421eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo7"; 422eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 423eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 424eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 425edb93de4SGuido Günther regulator-always-on; 426eb4ea085SAngus Ainslie (Purism) }; 427eb4ea085SAngus Ainslie (Purism) }; 428eb4ea085SAngus Ainslie (Purism) }; 429eb4ea085SAngus Ainslie (Purism) 4309251dad3SGuido Günther typec_ptn5100: usb-typec@52 { 431eb4ea085SAngus Ainslie (Purism) compatible = "nxp,ptn5110"; 432eb4ea085SAngus Ainslie (Purism) reg = <0x52>; 433eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 434eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_typec>; 435eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 436eb4ea085SAngus Ainslie (Purism) interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 437eb4ea085SAngus Ainslie (Purism) 438eb4ea085SAngus Ainslie (Purism) connector { 439eb4ea085SAngus Ainslie (Purism) compatible = "usb-c-connector"; 440eb4ea085SAngus Ainslie (Purism) label = "USB-C"; 441eb4ea085SAngus Ainslie (Purism) data-role = "dual"; 442eb4ea085SAngus Ainslie (Purism) power-role = "dual"; 443eb4ea085SAngus Ainslie (Purism) try-power-role = "sink"; 444eb4ea085SAngus Ainslie (Purism) source-pdos = <PDO_FIXED(5000, 2000, 445eb4ea085SAngus Ainslie (Purism) PDO_FIXED_USB_COMM | 446eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 447eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP )>; 4485369d191SAngus Ainslie (Purism) sink-pdos = <PDO_FIXED(5000, 3500, PDO_FIXED_USB_COMM | 449eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 450eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP ) 4515369d191SAngus Ainslie (Purism) PDO_VAR(5000, 5000, 3500)>; 452eb4ea085SAngus Ainslie (Purism) op-sink-microwatt = <10000000>; 453eb4ea085SAngus Ainslie (Purism) 454eb4ea085SAngus Ainslie (Purism) ports { 455eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 456eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 457eb4ea085SAngus Ainslie (Purism) 458eb4ea085SAngus Ainslie (Purism) port@0 { 459eb4ea085SAngus Ainslie (Purism) reg = <0>; 460eb4ea085SAngus Ainslie (Purism) 461eb4ea085SAngus Ainslie (Purism) usb_con_hs: endpoint { 462eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_hs>; 463eb4ea085SAngus Ainslie (Purism) }; 464eb4ea085SAngus Ainslie (Purism) }; 465eb4ea085SAngus Ainslie (Purism) 466eb4ea085SAngus Ainslie (Purism) port@1 { 467eb4ea085SAngus Ainslie (Purism) reg = <1>; 468eb4ea085SAngus Ainslie (Purism) 469eb4ea085SAngus Ainslie (Purism) usb_con_ss: endpoint { 470eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_ss>; 471eb4ea085SAngus Ainslie (Purism) }; 472eb4ea085SAngus Ainslie (Purism) }; 473eb4ea085SAngus Ainslie (Purism) }; 474eb4ea085SAngus Ainslie (Purism) }; 475eb4ea085SAngus Ainslie (Purism) }; 476eb4ea085SAngus Ainslie (Purism) 477eb4ea085SAngus Ainslie (Purism) rtc@68 { 478eb4ea085SAngus Ainslie (Purism) compatible = "microcrystal,rv4162"; 479eb4ea085SAngus Ainslie (Purism) reg = <0x68>; 480eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 481eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_rtc>; 482eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio4>; 483eb4ea085SAngus Ainslie (Purism) interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 484eb4ea085SAngus Ainslie (Purism) }; 485eb4ea085SAngus Ainslie (Purism) 486eb4ea085SAngus Ainslie (Purism) charger@6b { /* bq25896 */ 487eb4ea085SAngus Ainslie (Purism) compatible = "ti,bq25890"; 488eb4ea085SAngus Ainslie (Purism) reg = <0x6b>; 489eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 490eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_charger>; 491eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 492eb4ea085SAngus Ainslie (Purism) interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 493eb4ea085SAngus Ainslie (Purism) ti,battery-regulation-voltage = <4192000>; /* 4.192V */ 494eb4ea085SAngus Ainslie (Purism) ti,charge-current = <1600000>; /* 1.6A */ 495eb4ea085SAngus Ainslie (Purism) ti,termination-current = <66000>; /* 66mA */ 496eb4ea085SAngus Ainslie (Purism) ti,precharge-current = <130000>; /* 130mA */ 497eb4ea085SAngus Ainslie (Purism) ti,minimum-sys-voltage = <3000000>; /* 3V */ 498eb4ea085SAngus Ainslie (Purism) ti,boost-voltage = <5000000>; /* 5V */ 499eb4ea085SAngus Ainslie (Purism) ti,boost-max-current = <50000>; /* 50mA */ 500eb4ea085SAngus Ainslie (Purism) }; 501eb4ea085SAngus Ainslie (Purism)}; 502eb4ea085SAngus Ainslie (Purism) 503eb4ea085SAngus Ainslie (Purism)&i2c3 { 504eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 505eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 506eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c3>; 507eb4ea085SAngus Ainslie (Purism) status = "okay"; 508eb4ea085SAngus Ainslie (Purism) 509eb4ea085SAngus Ainslie (Purism) magnetometer@1e { 510eb4ea085SAngus Ainslie (Purism) compatible = "st,lsm9ds1-magn"; 511eb4ea085SAngus Ainslie (Purism) reg = <0x1e>; 512eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 513eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_imu>; 514eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 515106f7b3bSAngus Ainslie (Purism) interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 516eb4ea085SAngus Ainslie (Purism) vdd-supply = <®_3v3_p>; 517eb4ea085SAngus Ainslie (Purism) vddio-supply = <®_3v3_p>; 518eb4ea085SAngus Ainslie (Purism) }; 519eb4ea085SAngus Ainslie (Purism) 520c53f0166SAngus Ainslie (Purism) sgtl5000: audio-codec@a { 521c53f0166SAngus Ainslie (Purism) compatible = "fsl,sgtl5000"; 522c53f0166SAngus Ainslie (Purism) clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 523c53f0166SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 524c53f0166SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 525c53f0166SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 526c53f0166SAngus Ainslie (Purism) #sound-dai-cells = <0>; 527c53f0166SAngus Ainslie (Purism) reg = <0x0a>; 528c53f0166SAngus Ainslie (Purism) VDDD-supply = <®_1v8_p>; 529c53f0166SAngus Ainslie (Purism) VDDIO-supply = <®_3v3_p>; 530c53f0166SAngus Ainslie (Purism) VDDA-supply = <®_3v3_p>; 531c53f0166SAngus Ainslie (Purism) }; 532c53f0166SAngus Ainslie (Purism) 533eb4ea085SAngus Ainslie (Purism) touchscreen@5d { 534eb4ea085SAngus Ainslie (Purism) compatible = "goodix,gt5688"; 535eb4ea085SAngus Ainslie (Purism) reg = <0x5d>; 536eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 537eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_ts>; 538eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 539eb4ea085SAngus Ainslie (Purism) interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 540eb4ea085SAngus Ainslie (Purism) reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 541eb4ea085SAngus Ainslie (Purism) irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 542eb4ea085SAngus Ainslie (Purism) touchscreen-size-x = <720>; 543eb4ea085SAngus Ainslie (Purism) touchscreen-size-y = <1440>; 544eb4ea085SAngus Ainslie (Purism) AVDD28-supply = <®_2v8_p>; 545eb4ea085SAngus Ainslie (Purism) VDDIO-supply = <®_1v8_p>; 546eb4ea085SAngus Ainslie (Purism) }; 547537c00e3SMartin Kepplinger 548ea38ca9aSGuido Günther proximity-sensor@60 { 549ea38ca9aSGuido Günther compatible = "vishay,vcnl4040"; 550ea38ca9aSGuido Günther reg = <0x60>; 551ea38ca9aSGuido Günther pinctrl-0 = <&pinctrl_prox>; 552ea38ca9aSGuido Günther }; 553ea38ca9aSGuido Günther 554537c00e3SMartin Kepplinger accel-gyro@6a { 555537c00e3SMartin Kepplinger compatible = "st,lsm9ds1-imu"; 556537c00e3SMartin Kepplinger reg = <0x6a>; 557537c00e3SMartin Kepplinger vdd-supply = <®_3v3_p>; 558537c00e3SMartin Kepplinger vddio-supply = <®_3v3_p>; 559eef22bb1SMartin Kepplinger mount-matrix = "1", "0", "0", 560eef22bb1SMartin Kepplinger "0", "1", "0", 561eef22bb1SMartin Kepplinger "0", "0", "-1"; 562537c00e3SMartin Kepplinger }; 563eb4ea085SAngus Ainslie (Purism)}; 564eb4ea085SAngus Ainslie (Purism) 565eb4ea085SAngus Ainslie (Purism)&iomuxc { 566eb4ea085SAngus Ainslie (Purism) pinctrl_bl: blgrp { 567eb4ea085SAngus Ainslie (Purism) fsl,pins = < 568eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */ 569eb4ea085SAngus Ainslie (Purism) >; 570eb4ea085SAngus Ainslie (Purism) }; 571eb4ea085SAngus Ainslie (Purism) 572eb4ea085SAngus Ainslie (Purism) pinctrl_bt: btgrp { 573eb4ea085SAngus Ainslie (Purism) fsl,pins = < 574eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */ 575eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */ 576eb4ea085SAngus Ainslie (Purism) >; 577eb4ea085SAngus Ainslie (Purism) }; 578eb4ea085SAngus Ainslie (Purism) 579eb4ea085SAngus Ainslie (Purism) pinctrl_charger: chargergrp { 580eb4ea085SAngus Ainslie (Purism) fsl,pins = < 581eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */ 582eb4ea085SAngus Ainslie (Purism) >; 583eb4ea085SAngus Ainslie (Purism) }; 584eb4ea085SAngus Ainslie (Purism) 585eb4ea085SAngus Ainslie (Purism) pinctrl_fec1: fec1grp { 586eb4ea085SAngus Ainslie (Purism) fsl,pins = < 587eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 588eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 589eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 590eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 591eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 592eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 593eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 594eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 595eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 596eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 597eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 598eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 599eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 600eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 601eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 602eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f 603eb4ea085SAngus Ainslie (Purism) >; 604eb4ea085SAngus Ainslie (Purism) }; 605eb4ea085SAngus Ainslie (Purism) 606eb4ea085SAngus Ainslie (Purism) pinctrl_ts: tsgrp { 607eb4ea085SAngus Ainslie (Purism) fsl,pins = < 608eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */ 609eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ 610eb4ea085SAngus Ainslie (Purism) >; 611eb4ea085SAngus Ainslie (Purism) }; 612eb4ea085SAngus Ainslie (Purism) 613eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_leds: gpioledgrp { 614eb4ea085SAngus Ainslie (Purism) fsl,pins = < 615eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 616eb4ea085SAngus Ainslie (Purism) >; 617eb4ea085SAngus Ainslie (Purism) }; 618eb4ea085SAngus Ainslie (Purism) 619eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_keys: gpiokeygrp { 620eb4ea085SAngus Ainslie (Purism) fsl,pins = < 621eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 622eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16 623eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */ 6243ef506b3SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ 625eb4ea085SAngus Ainslie (Purism) >; 626eb4ea085SAngus Ainslie (Purism) }; 627eb4ea085SAngus Ainslie (Purism) 628eb4ea085SAngus Ainslie (Purism) pinctrl_haptic: hapticgrp { 629eb4ea085SAngus Ainslie (Purism) fsl,pins = < 630eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ 631eb4ea085SAngus Ainslie (Purism) >; 632eb4ea085SAngus Ainslie (Purism) }; 633eb4ea085SAngus Ainslie (Purism) 634eb4ea085SAngus Ainslie (Purism) pinctrl_i2c1: i2c1grp { 635eb4ea085SAngus Ainslie (Purism) fsl,pins = < 636eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f 637eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f 638eb4ea085SAngus Ainslie (Purism) >; 639eb4ea085SAngus Ainslie (Purism) }; 640eb4ea085SAngus Ainslie (Purism) 641eb4ea085SAngus Ainslie (Purism) pinctrl_i2c3: i2c3grp { 642eb4ea085SAngus Ainslie (Purism) fsl,pins = < 643eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f 644eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f 645eb4ea085SAngus Ainslie (Purism) >; 646eb4ea085SAngus Ainslie (Purism) }; 647eb4ea085SAngus Ainslie (Purism) 648eb4ea085SAngus Ainslie (Purism) pinctrl_imu: imugrp { 649eb4ea085SAngus Ainslie (Purism) fsl,pins = < 650eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */ 651eb4ea085SAngus Ainslie (Purism) >; 652eb4ea085SAngus Ainslie (Purism) }; 653eb4ea085SAngus Ainslie (Purism) 654*6f46f7ffSGuido Günther pinctrl_spkamp: spkamp { 655*6f46f7ffSGuido Günther fsl,pins = < 656*6f46f7ffSGuido Günther MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x81 /* MUTE */ 657*6f46f7ffSGuido Günther >; 658*6f46f7ffSGuido Günther }; 659*6f46f7ffSGuido Günther 660eb4ea085SAngus Ainslie (Purism) pinctrl_pmic: pmicgrp { 661eb4ea085SAngus Ainslie (Purism) fsl,pins = < 662eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */ 663eb4ea085SAngus Ainslie (Purism) >; 664eb4ea085SAngus Ainslie (Purism) }; 665eb4ea085SAngus Ainslie (Purism) 666ea38ca9aSGuido Günther pinctrl_prox: proxgrp { 667ea38ca9aSGuido Günther fsl,pins = < 668ea38ca9aSGuido Günther MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */ 669ea38ca9aSGuido Günther >; 670ea38ca9aSGuido Günther }; 671ea38ca9aSGuido Günther 672eb4ea085SAngus Ainslie (Purism) pinctrl_pwr_en: pwrengrp { 673eb4ea085SAngus Ainslie (Purism) fsl,pins = < 674eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06 675eb4ea085SAngus Ainslie (Purism) >; 676eb4ea085SAngus Ainslie (Purism) }; 677eb4ea085SAngus Ainslie (Purism) 678eb4ea085SAngus Ainslie (Purism) pinctrl_rtc: rtcgrp { 679eb4ea085SAngus Ainslie (Purism) fsl,pins = < 680eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */ 681eb4ea085SAngus Ainslie (Purism) >; 682eb4ea085SAngus Ainslie (Purism) }; 683eb4ea085SAngus Ainslie (Purism) 684c53f0166SAngus Ainslie (Purism) pinctrl_sai2: sai2grp { 685c53f0166SAngus Ainslie (Purism) fsl,pins = < 686c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 687c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 688c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 689c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 690c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 691c53f0166SAngus Ainslie (Purism) >; 692c53f0166SAngus Ainslie (Purism) }; 693c53f0166SAngus Ainslie (Purism) 6947f7b7997SAngus Ainslie (Purism) pinctrl_sai6: sai6grp { 6957f7b7997SAngus Ainslie (Purism) fsl,pins = < 6967f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 6977f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 6987f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 6997f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 7007f7b7997SAngus Ainslie (Purism) >; 7017f7b7997SAngus Ainslie (Purism) }; 7027f7b7997SAngus Ainslie (Purism) 703eb4ea085SAngus Ainslie (Purism) pinctrl_typec: typecgrp { 704eb4ea085SAngus Ainslie (Purism) fsl,pins = < 705eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 706eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80 707eb4ea085SAngus Ainslie (Purism) >; 708eb4ea085SAngus Ainslie (Purism) }; 709eb4ea085SAngus Ainslie (Purism) 710eb4ea085SAngus Ainslie (Purism) pinctrl_uart1: uart1grp { 711eb4ea085SAngus Ainslie (Purism) fsl,pins = < 712eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 713eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 714eb4ea085SAngus Ainslie (Purism) >; 715eb4ea085SAngus Ainslie (Purism) }; 716eb4ea085SAngus Ainslie (Purism) 717eb4ea085SAngus Ainslie (Purism) pinctrl_uart2: uart2grp { 718eb4ea085SAngus Ainslie (Purism) fsl,pins = < 719eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 720eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 721eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 722eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 723eb4ea085SAngus Ainslie (Purism) >; 724eb4ea085SAngus Ainslie (Purism) }; 725eb4ea085SAngus Ainslie (Purism) 726eb4ea085SAngus Ainslie (Purism) pinctrl_uart3: uart3grp { 727eb4ea085SAngus Ainslie (Purism) fsl,pins = < 728eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 729eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 730eb4ea085SAngus Ainslie (Purism) >; 731eb4ea085SAngus Ainslie (Purism) }; 732eb4ea085SAngus Ainslie (Purism) 733eb4ea085SAngus Ainslie (Purism) pinctrl_uart4: uart4grp { 734eb4ea085SAngus Ainslie (Purism) fsl,pins = < 735eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 736eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 737eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 738eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 739eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49 740eb4ea085SAngus Ainslie (Purism) >; 741eb4ea085SAngus Ainslie (Purism) }; 742eb4ea085SAngus Ainslie (Purism) 743eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc1: usdhc1grp { 744eb4ea085SAngus Ainslie (Purism) fsl,pins = < 745eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 746eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 747eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 748eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 749eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 750eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 751eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 752eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 753eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 754eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 755eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 756eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 757eb4ea085SAngus Ainslie (Purism) >; 758eb4ea085SAngus Ainslie (Purism) }; 759eb4ea085SAngus Ainslie (Purism) 760ae560c43SKrzysztof Kozlowski pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 761eb4ea085SAngus Ainslie (Purism) fsl,pins = < 762eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 763eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 764eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 765eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 766eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 767eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 768eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 769eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 770eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 771eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 772eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 773eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 774eb4ea085SAngus Ainslie (Purism) >; 775eb4ea085SAngus Ainslie (Purism) }; 776eb4ea085SAngus Ainslie (Purism) 777ae560c43SKrzysztof Kozlowski pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 778eb4ea085SAngus Ainslie (Purism) fsl,pins = < 779eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 780eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 781eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 782eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 783eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 784eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 785eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 786eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 787eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 788eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 789eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 790eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 791eb4ea085SAngus Ainslie (Purism) >; 792eb4ea085SAngus Ainslie (Purism) }; 793eb4ea085SAngus Ainslie (Purism) 794ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_pwr: usdhc2pwrgrp { 795eb4ea085SAngus Ainslie (Purism) fsl,pins = < 796eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 797eb4ea085SAngus Ainslie (Purism) >; 798eb4ea085SAngus Ainslie (Purism) }; 799eb4ea085SAngus Ainslie (Purism) 800ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_gpio: usdhc2gpiogrp { 801eb4ea085SAngus Ainslie (Purism) fsl,pins = < 802eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ 803eb4ea085SAngus Ainslie (Purism) >; 804eb4ea085SAngus Ainslie (Purism) }; 805eb4ea085SAngus Ainslie (Purism) 806eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2: usdhc2grp { 807eb4ea085SAngus Ainslie (Purism) fsl,pins = < 808eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 809eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 810eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 811eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 812eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 813eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 814eb4ea085SAngus Ainslie (Purism) >; 815eb4ea085SAngus Ainslie (Purism) }; 816eb4ea085SAngus Ainslie (Purism) 817ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 818eb4ea085SAngus Ainslie (Purism) fsl,pins = < 819eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 820eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 821eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 822eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 823eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 824eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 825eb4ea085SAngus Ainslie (Purism) >; 826eb4ea085SAngus Ainslie (Purism) }; 827eb4ea085SAngus Ainslie (Purism) 828ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 829eb4ea085SAngus Ainslie (Purism) fsl,pins = < 830eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 831eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf 832eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf 833eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf 834eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf 835eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf 836eb4ea085SAngus Ainslie (Purism) >; 837eb4ea085SAngus Ainslie (Purism) }; 838eb4ea085SAngus Ainslie (Purism) 839eb4ea085SAngus Ainslie (Purism) pinctrl_wdog: wdoggrp { 840eb4ea085SAngus Ainslie (Purism) fsl,pins = < 841eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 842eb4ea085SAngus Ainslie (Purism) >; 843eb4ea085SAngus Ainslie (Purism) }; 844eb4ea085SAngus Ainslie (Purism) 845eb4ea085SAngus Ainslie (Purism) pinctrl_wifi_pwr_en: wifipwrengrp { 846eb4ea085SAngus Ainslie (Purism) fsl,pins = < 847eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 848eb4ea085SAngus Ainslie (Purism) >; 849eb4ea085SAngus Ainslie (Purism) }; 850eb4ea085SAngus Ainslie (Purism) 851eb4ea085SAngus Ainslie (Purism) pinctrl_wwan: wwangrp { 852eb4ea085SAngus Ainslie (Purism) fsl,pins = < 853eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */ 854eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ 855eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */ 856eb4ea085SAngus Ainslie (Purism) >; 857eb4ea085SAngus Ainslie (Purism) }; 858eb4ea085SAngus Ainslie (Purism)}; 859eb4ea085SAngus Ainslie (Purism) 860e8151ef3SGuido Günther&lcdif { 861e8151ef3SGuido Günther status = "okay"; 862e8151ef3SGuido Günther}; 863e8151ef3SGuido Günther 864e8151ef3SGuido Günther&mipi_dsi { 865e8151ef3SGuido Günther status = "okay"; 866e8151ef3SGuido Günther #address-cells = <1>; 867e8151ef3SGuido Günther #size-cells = <0>; 868e8151ef3SGuido Günther 869e8151ef3SGuido Günther panel@0 { 870e8151ef3SGuido Günther compatible = "rocktech,jh057n00900"; 871e8151ef3SGuido Günther reg = <0>; 872e8151ef3SGuido Günther backlight = <&backlight_dsi>; 873e8151ef3SGuido Günther reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; 874e8151ef3SGuido Günther iovcc-supply = <®_1v8_p>; 875e8151ef3SGuido Günther vcc-supply = <®_2v8_p>; 876e8151ef3SGuido Günther port { 877e8151ef3SGuido Günther panel_in: endpoint { 878e8151ef3SGuido Günther remote-endpoint = <&mipi_dsi_out>; 879e8151ef3SGuido Günther }; 880e8151ef3SGuido Günther }; 881e8151ef3SGuido Günther }; 882e8151ef3SGuido Günther 883e8151ef3SGuido Günther ports { 884e8151ef3SGuido Günther port@1 { 885e8151ef3SGuido Günther reg = <1>; 886e8151ef3SGuido Günther mipi_dsi_out: endpoint { 887e8151ef3SGuido Günther remote-endpoint = <&panel_in>; 888e8151ef3SGuido Günther }; 889e8151ef3SGuido Günther }; 890e8151ef3SGuido Günther }; 891e8151ef3SGuido Günther}; 892e8151ef3SGuido Günther 893eb4ea085SAngus Ainslie (Purism)&pgc_gpu { 894eb4ea085SAngus Ainslie (Purism) power-supply = <&buck3_reg>; 895eb4ea085SAngus Ainslie (Purism)}; 896eb4ea085SAngus Ainslie (Purism) 897eb4ea085SAngus Ainslie (Purism)&pgc_vpu { 898eb4ea085SAngus Ainslie (Purism) power-supply = <&buck4_reg>; 899eb4ea085SAngus Ainslie (Purism)}; 900eb4ea085SAngus Ainslie (Purism) 901eb4ea085SAngus Ainslie (Purism)&pwm1 { 902eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 903eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_bl>; 904eb4ea085SAngus Ainslie (Purism) status = "okay"; 905eb4ea085SAngus Ainslie (Purism)}; 906eb4ea085SAngus Ainslie (Purism) 90701407158SAngus Ainslie (Purism)&snvs_pwrkey { 90801407158SAngus Ainslie (Purism) status = "okay"; 90901407158SAngus Ainslie (Purism)}; 910eb4ea085SAngus Ainslie (Purism) 911ff38c1ddSGuido Günther&snvs_rtc { 912ff38c1ddSGuido Günther status = "disabled"; 913ff38c1ddSGuido Günther}; 914ff38c1ddSGuido Günther 915c53f0166SAngus Ainslie (Purism)&sai2 { 916c53f0166SAngus Ainslie (Purism) pinctrl-names = "default"; 917c53f0166SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_sai2>; 918c53f0166SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 919c53f0166SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 920c53f0166SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 921c53f0166SAngus Ainslie (Purism) status = "okay"; 922c53f0166SAngus Ainslie (Purism)}; 923c53f0166SAngus Ainslie (Purism) 9247f7b7997SAngus Ainslie (Purism)&sai6 { 9257f7b7997SAngus Ainslie (Purism) pinctrl-names = "default"; 9267f7b7997SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_sai6>; 9277f7b7997SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; 9287f7b7997SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 9297f7b7997SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 9307f7b7997SAngus Ainslie (Purism) fsl,sai-synchronous-rx; 9317f7b7997SAngus Ainslie (Purism) status = "okay"; 9327f7b7997SAngus Ainslie (Purism)}; 9337f7b7997SAngus Ainslie (Purism) 934eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */ 935eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 936eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart1>; 937eb4ea085SAngus Ainslie (Purism) status = "okay"; 938eb4ea085SAngus Ainslie (Purism)}; 939eb4ea085SAngus Ainslie (Purism) 940eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */ 941eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 942eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart3>; 943eb4ea085SAngus Ainslie (Purism) status = "okay"; 944eb4ea085SAngus Ainslie (Purism)}; 945eb4ea085SAngus Ainslie (Purism) 946eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */ 947eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 948eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; 949eb4ea085SAngus Ainslie (Purism) uart-has-rtscts; 950eb4ea085SAngus Ainslie (Purism) status = "okay"; 951eb4ea085SAngus Ainslie (Purism)}; 952eb4ea085SAngus Ainslie (Purism) 953eb4ea085SAngus Ainslie (Purism)&usb3_phy0 { 954dde061b8SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 955eb4ea085SAngus Ainslie (Purism) status = "okay"; 956eb4ea085SAngus Ainslie (Purism)}; 957eb4ea085SAngus Ainslie (Purism) 958eb4ea085SAngus Ainslie (Purism)&usb3_phy1 { 959eb4ea085SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 960eb4ea085SAngus Ainslie (Purism) status = "okay"; 961eb4ea085SAngus Ainslie (Purism)}; 962eb4ea085SAngus Ainslie (Purism) 963eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 { 964eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 965eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 966eb4ea085SAngus Ainslie (Purism) dr_mode = "otg"; 967eb4ea085SAngus Ainslie (Purism) status = "okay"; 968eb4ea085SAngus Ainslie (Purism) 969eb4ea085SAngus Ainslie (Purism) port@0 { 970eb4ea085SAngus Ainslie (Purism) reg = <0>; 971eb4ea085SAngus Ainslie (Purism) 972eb4ea085SAngus Ainslie (Purism) typec_hs: endpoint { 973eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_hs>; 974eb4ea085SAngus Ainslie (Purism) }; 975eb4ea085SAngus Ainslie (Purism) }; 976eb4ea085SAngus Ainslie (Purism) 977eb4ea085SAngus Ainslie (Purism) port@1 { 978eb4ea085SAngus Ainslie (Purism) reg = <1>; 979eb4ea085SAngus Ainslie (Purism) 980eb4ea085SAngus Ainslie (Purism) typec_ss: endpoint { 981eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_ss>; 982eb4ea085SAngus Ainslie (Purism) }; 983eb4ea085SAngus Ainslie (Purism) }; 984eb4ea085SAngus Ainslie (Purism)}; 985eb4ea085SAngus Ainslie (Purism) 986eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 { 987eb4ea085SAngus Ainslie (Purism) dr_mode = "host"; 988eb4ea085SAngus Ainslie (Purism) status = "okay"; 989eb4ea085SAngus Ainslie (Purism)}; 990eb4ea085SAngus Ainslie (Purism) 991eb4ea085SAngus Ainslie (Purism)&usdhc1 { 992e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 993e045f044SAnson Huang assigned-clock-rates = <400000000>; 994eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 995eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc1>; 996eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 997eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 998eb4ea085SAngus Ainslie (Purism) bus-width = <8>; 999eb4ea085SAngus Ainslie (Purism) non-removable; 1000eb4ea085SAngus Ainslie (Purism) status = "okay"; 1001eb4ea085SAngus Ainslie (Purism)}; 1002eb4ea085SAngus Ainslie (Purism) 1003eb4ea085SAngus Ainslie (Purism)&usdhc2 { 1004e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 1005e045f044SAnson Huang assigned-clock-rates = <200000000>; 1006eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1007eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2>; 1008eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 1009eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 1010eb4ea085SAngus Ainslie (Purism) bus-width = <4>; 1011eb4ea085SAngus Ainslie (Purism) vmmc-supply = <®_usdhc2_vmmc>; 1012eb4ea085SAngus Ainslie (Purism) power-supply = <&wifi_pwr_en>; 10139dae8563SAngus Ainslie (Purism) broken-cd; 1014eb4ea085SAngus Ainslie (Purism) disable-wp; 1015eb4ea085SAngus Ainslie (Purism) cap-sdio-irq; 1016eb4ea085SAngus Ainslie (Purism) keep-power-in-suspend; 1017eb4ea085SAngus Ainslie (Purism) wakeup-source; 1018eb4ea085SAngus Ainslie (Purism) status = "okay"; 1019eb4ea085SAngus Ainslie (Purism)}; 1020eb4ea085SAngus Ainslie (Purism) 1021eb4ea085SAngus Ainslie (Purism)&wdog1 { 1022eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 1023eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wdog>; 1024eb4ea085SAngus Ainslie (Purism) fsl,ext-reset-output; 1025eb4ea085SAngus Ainslie (Purism) status = "okay"; 1026eb4ea085SAngus Ainslie (Purism)}; 1027