1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+ 2eb4ea085SAngus Ainslie (Purism)/* 3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC 4eb4ea085SAngus Ainslie (Purism) */ 5eb4ea085SAngus Ainslie (Purism) 6eb4ea085SAngus Ainslie (Purism)/dts-v1/; 7eb4ea085SAngus Ainslie (Purism) 8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h" 9d8fa4792SKrzysztof Kozlowski#include <dt-bindings/interrupt-controller/irq.h> 10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h" 11eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h" 12eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi" 13eb4ea085SAngus Ainslie (Purism) 14eb4ea085SAngus Ainslie (Purism)/ { 15eb4ea085SAngus Ainslie (Purism) model = "Purism Librem 5 devkit"; 16eb4ea085SAngus Ainslie (Purism) compatible = "purism,librem5-devkit", "fsl,imx8mq"; 17eb4ea085SAngus Ainslie (Purism) 18eb4ea085SAngus Ainslie (Purism) backlight_dsi: backlight-dsi { 19eb4ea085SAngus Ainslie (Purism) compatible = "pwm-backlight"; 20eb4ea085SAngus Ainslie (Purism) /* 200 Hz for the PAM2841 */ 21eb4ea085SAngus Ainslie (Purism) pwms = <&pwm1 0 5000000>; 22eb4ea085SAngus Ainslie (Purism) brightness-levels = <0 100>; 23eb4ea085SAngus Ainslie (Purism) num-interpolated-steps = <100>; 24eb4ea085SAngus Ainslie (Purism) /* Default brightness level (index into the array defined by */ 25eb4ea085SAngus Ainslie (Purism) /* the "brightness-levels" property) */ 26eb4ea085SAngus Ainslie (Purism) default-brightness-level = <0>; 27eb4ea085SAngus Ainslie (Purism) power-supply = <®_22v4_p>; 28eb4ea085SAngus Ainslie (Purism) }; 29eb4ea085SAngus Ainslie (Purism) 30eb4ea085SAngus Ainslie (Purism) chosen { 31eb4ea085SAngus Ainslie (Purism) stdout-path = &uart1; 32eb4ea085SAngus Ainslie (Purism) }; 33eb4ea085SAngus Ainslie (Purism) 34eb4ea085SAngus Ainslie (Purism) gpio-keys { 35eb4ea085SAngus Ainslie (Purism) compatible = "gpio-keys"; 36eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 37eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_keys>; 38eb4ea085SAngus Ainslie (Purism) 39eb4ea085SAngus Ainslie (Purism) btn1 { 40eb4ea085SAngus Ainslie (Purism) label = "VOL_UP"; 41eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 42eb4ea085SAngus Ainslie (Purism) wakeup-source; 43eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEUP>; 44eb4ea085SAngus Ainslie (Purism) }; 45eb4ea085SAngus Ainslie (Purism) 46eb4ea085SAngus Ainslie (Purism) btn2 { 47eb4ea085SAngus Ainslie (Purism) label = "VOL_DOWN"; 48eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 49eb4ea085SAngus Ainslie (Purism) wakeup-source; 50eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEDOWN>; 51eb4ea085SAngus Ainslie (Purism) }; 52eb4ea085SAngus Ainslie (Purism) 53eb4ea085SAngus Ainslie (Purism) hp-det { 54eb4ea085SAngus Ainslie (Purism) label = "HP_DET"; 55eb4ea085SAngus Ainslie (Purism) gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 56eb4ea085SAngus Ainslie (Purism) wakeup-source; 57eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_HP>; 58eb4ea085SAngus Ainslie (Purism) }; 593ef506b3SAngus Ainslie (Purism) 603ef506b3SAngus Ainslie (Purism) wwan-wake { 613ef506b3SAngus Ainslie (Purism) label = "WWAN_WAKE"; 623ef506b3SAngus Ainslie (Purism) gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; 633ef506b3SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 64d8fa4792SKrzysztof Kozlowski interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 653ef506b3SAngus Ainslie (Purism) wakeup-source; 663ef506b3SAngus Ainslie (Purism) linux,code = <KEY_PHONE>; 673ef506b3SAngus Ainslie (Purism) }; 68eb4ea085SAngus Ainslie (Purism) }; 69eb4ea085SAngus Ainslie (Purism) 70eb4ea085SAngus Ainslie (Purism) leds { 71eb4ea085SAngus Ainslie (Purism) compatible = "gpio-leds"; 72eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 73eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_leds>; 74eb4ea085SAngus Ainslie (Purism) 75eb4ea085SAngus Ainslie (Purism) led1 { 76eb4ea085SAngus Ainslie (Purism) label = "LED 1"; 77eb4ea085SAngus Ainslie (Purism) gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 78eb4ea085SAngus Ainslie (Purism) default-state = "off"; 79eb4ea085SAngus Ainslie (Purism) }; 80eb4ea085SAngus Ainslie (Purism) }; 81eb4ea085SAngus Ainslie (Purism) 82eb4ea085SAngus Ainslie (Purism) pmic_osc: clock-pmic { 83eb4ea085SAngus Ainslie (Purism) compatible = "fixed-clock"; 84eb4ea085SAngus Ainslie (Purism) #clock-cells = <0>; 85eb4ea085SAngus Ainslie (Purism) clock-frequency = <32768>; 86eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_osc"; 87eb4ea085SAngus Ainslie (Purism) }; 88eb4ea085SAngus Ainslie (Purism) 89eb4ea085SAngus Ainslie (Purism) reg_1v8_p: regulator-1v8-p { 90eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 91eb4ea085SAngus Ainslie (Purism) regulator-name = "1v8_p"; 92eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 93eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 94eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 95eb4ea085SAngus Ainslie (Purism) }; 96eb4ea085SAngus Ainslie (Purism) 97eb4ea085SAngus Ainslie (Purism) reg_2v8_p: regulator-2v8-p { 98eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 99eb4ea085SAngus Ainslie (Purism) regulator-name = "2v8_p"; 100eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <2800000>; 101eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <2800000>; 102eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 103eb4ea085SAngus Ainslie (Purism) }; 104eb4ea085SAngus Ainslie (Purism) 105eb4ea085SAngus Ainslie (Purism) reg_3v3_p: regulator-3v3-p { 106eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 107eb4ea085SAngus Ainslie (Purism) regulator-name = "3v3_p"; 108eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 109eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 110eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 111eb4ea085SAngus Ainslie (Purism) 112eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 113eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 114eb4ea085SAngus Ainslie (Purism) }; 115eb4ea085SAngus Ainslie (Purism) }; 116eb4ea085SAngus Ainslie (Purism) 117eb4ea085SAngus Ainslie (Purism) reg_5v_p: regulator-5v-p { 118eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 119eb4ea085SAngus Ainslie (Purism) regulator-name = "5v_p"; 120eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <5000000>; 121eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <5000000>; 122eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 123eb4ea085SAngus Ainslie (Purism) 124eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 125eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 126eb4ea085SAngus Ainslie (Purism) }; 127eb4ea085SAngus Ainslie (Purism) }; 128eb4ea085SAngus Ainslie (Purism) 129eb4ea085SAngus Ainslie (Purism) reg_22v4_p: regulator-22v4-p { 130eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 131eb4ea085SAngus Ainslie (Purism) regulator-name = "22v4_P"; 132eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <22400000>; 133eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <22400000>; 134eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 135eb4ea085SAngus Ainslie (Purism) }; 136eb4ea085SAngus Ainslie (Purism) 137eb4ea085SAngus Ainslie (Purism) reg_pwr_en: regulator-pwr-en { 138eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 139eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 140eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pwr_en>; 141eb4ea085SAngus Ainslie (Purism) regulator-name = "PWR_EN"; 142eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 143eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 144eb4ea085SAngus Ainslie (Purism) gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 145eb4ea085SAngus Ainslie (Purism) enable-active-high; 146eb4ea085SAngus Ainslie (Purism) regulator-always-on; 147eb4ea085SAngus Ainslie (Purism) }; 148eb4ea085SAngus Ainslie (Purism) 149eb4ea085SAngus Ainslie (Purism) reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 150eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 151eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 152eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2_pwr>; 153eb4ea085SAngus Ainslie (Purism) regulator-name = "VSD_3V3"; 154eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 155eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 156eb4ea085SAngus Ainslie (Purism) gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 157eb4ea085SAngus Ainslie (Purism) enable-active-high; 158eb4ea085SAngus Ainslie (Purism) regulator-always-on; 159eb4ea085SAngus Ainslie (Purism) }; 160eb4ea085SAngus Ainslie (Purism) 1617f7b7997SAngus Ainslie (Purism) wwan_codec: sound-wwan-codec { 1627f7b7997SAngus Ainslie (Purism) compatible = "option,gtm601"; 1637f7b7997SAngus Ainslie (Purism) #sound-dai-cells = <0>; 1647f7b7997SAngus Ainslie (Purism) }; 1657f7b7997SAngus Ainslie (Purism) 166c53f0166SAngus Ainslie (Purism) sound { 167c53f0166SAngus Ainslie (Purism) compatible = "simple-audio-card"; 168*5b65f39dSGuido Günther simple-audio-card,name = "Librem 5 Devkit"; 169c53f0166SAngus Ainslie (Purism) simple-audio-card,format = "i2s"; 170c53f0166SAngus Ainslie (Purism) simple-audio-card,widgets = 171c53f0166SAngus Ainslie (Purism) "Microphone", "Microphone Jack", 172c53f0166SAngus Ainslie (Purism) "Headphone", "Headphone Jack", 173c53f0166SAngus Ainslie (Purism) "Speaker", "Speaker Ext", 174c53f0166SAngus Ainslie (Purism) "Line", "Line In Jack"; 175c53f0166SAngus Ainslie (Purism) simple-audio-card,routing = 176c53f0166SAngus Ainslie (Purism) "MIC_IN", "Microphone Jack", 177c53f0166SAngus Ainslie (Purism) "Microphone Jack", "Mic Bias", 178c53f0166SAngus Ainslie (Purism) "LINE_IN", "Line In Jack", 179c53f0166SAngus Ainslie (Purism) "Headphone Jack", "HP_OUT", 180c53f0166SAngus Ainslie (Purism) "Speaker Ext", "LINE_OUT"; 181c53f0166SAngus Ainslie (Purism) 182c53f0166SAngus Ainslie (Purism) simple-audio-card,cpu { 183c53f0166SAngus Ainslie (Purism) sound-dai = <&sai2>; 184c53f0166SAngus Ainslie (Purism) }; 185c53f0166SAngus Ainslie (Purism) 186c53f0166SAngus Ainslie (Purism) simple-audio-card,codec { 187c53f0166SAngus Ainslie (Purism) sound-dai = <&sgtl5000>; 188c53f0166SAngus Ainslie (Purism) clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 189c53f0166SAngus Ainslie (Purism) frame-master; 190c53f0166SAngus Ainslie (Purism) bitclock-master; 191c53f0166SAngus Ainslie (Purism) }; 192c53f0166SAngus Ainslie (Purism) }; 193c53f0166SAngus Ainslie (Purism) 1947f7b7997SAngus Ainslie (Purism) sound-wwan { 1957f7b7997SAngus Ainslie (Purism) compatible = "simple-audio-card"; 1967f7b7997SAngus Ainslie (Purism) simple-audio-card,name = "SIMCom SIM7100"; 1977f7b7997SAngus Ainslie (Purism) simple-audio-card,format = "dsp_a"; 1987f7b7997SAngus Ainslie (Purism) 1997f7b7997SAngus Ainslie (Purism) simple-audio-card,cpu { 2007f7b7997SAngus Ainslie (Purism) sound-dai = <&sai6>; 2017f7b7997SAngus Ainslie (Purism) }; 2027f7b7997SAngus Ainslie (Purism) 2037f7b7997SAngus Ainslie (Purism) telephony_link_master: simple-audio-card,codec { 2047f7b7997SAngus Ainslie (Purism) sound-dai = <&wwan_codec>; 2057f7b7997SAngus Ainslie (Purism) frame-master; 2067f7b7997SAngus Ainslie (Purism) bitclock-master; 2077f7b7997SAngus Ainslie (Purism) }; 2087f7b7997SAngus Ainslie (Purism) }; 2097f7b7997SAngus Ainslie (Purism) 210eb4ea085SAngus Ainslie (Purism) vibrator { 211eb4ea085SAngus Ainslie (Purism) compatible = "gpio-vibrator"; 212eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 213eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_haptic>; 214eb4ea085SAngus Ainslie (Purism) enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; 215eb4ea085SAngus Ainslie (Purism) vcc-supply = <®_3v3_p>; 216eb4ea085SAngus Ainslie (Purism) }; 217eb4ea085SAngus Ainslie (Purism) 218eb4ea085SAngus Ainslie (Purism) wifi_pwr_en: regulator-wifi-en { 219eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 220eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 221eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wifi_pwr_en>; 222eb4ea085SAngus Ainslie (Purism) regulator-name = "WIFI_EN"; 223eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 224eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 225eb4ea085SAngus Ainslie (Purism) gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 226eb4ea085SAngus Ainslie (Purism) enable-active-high; 227eb4ea085SAngus Ainslie (Purism) regulator-always-on; 228eb4ea085SAngus Ainslie (Purism) }; 229eb4ea085SAngus Ainslie (Purism)}; 230eb4ea085SAngus Ainslie (Purism) 231a2e47ba2SAngus Ainslie (Purism)&A53_0 { 232a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 233a2e47ba2SAngus Ainslie (Purism)}; 234a2e47ba2SAngus Ainslie (Purism) 235a2e47ba2SAngus Ainslie (Purism)&A53_1 { 236a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 237a2e47ba2SAngus Ainslie (Purism)}; 238a2e47ba2SAngus Ainslie (Purism) 239a2e47ba2SAngus Ainslie (Purism)&A53_2 { 240a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 241a2e47ba2SAngus Ainslie (Purism)}; 242a2e47ba2SAngus Ainslie (Purism) 243a2e47ba2SAngus Ainslie (Purism)&A53_3 { 244a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 245a2e47ba2SAngus Ainslie (Purism)}; 246a2e47ba2SAngus Ainslie (Purism) 2479d9005a5SGuido Günther&dphy { 2489d9005a5SGuido Günther status = "okay"; 2499d9005a5SGuido Günther}; 2509d9005a5SGuido Günther 251eb4ea085SAngus Ainslie (Purism)&fec1 { 252eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 253eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_fec1>; 254eb4ea085SAngus Ainslie (Purism) phy-mode = "rgmii-id"; 255eb4ea085SAngus Ainslie (Purism) phy-handle = <ðphy0>; 256eb4ea085SAngus Ainslie (Purism) fsl,magic-packet; 257eb4ea085SAngus Ainslie (Purism) phy-supply = <®_3v3_p>; 258eb4ea085SAngus Ainslie (Purism) status = "okay"; 259eb4ea085SAngus Ainslie (Purism) 260eb4ea085SAngus Ainslie (Purism) mdio { 261eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 262eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 263eb4ea085SAngus Ainslie (Purism) 264eb4ea085SAngus Ainslie (Purism) ethphy0: ethernet-phy@1 { 265eb4ea085SAngus Ainslie (Purism) compatible = "ethernet-phy-ieee802.3-c22"; 266eb4ea085SAngus Ainslie (Purism) reg = <1>; 267eb4ea085SAngus Ainslie (Purism) }; 268eb4ea085SAngus Ainslie (Purism) }; 269eb4ea085SAngus Ainslie (Purism)}; 270eb4ea085SAngus Ainslie (Purism) 271eb4ea085SAngus Ainslie (Purism)&i2c1 { 272eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 273eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 274eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c1>; 275eb4ea085SAngus Ainslie (Purism) status = "okay"; 276eb4ea085SAngus Ainslie (Purism) 277eb4ea085SAngus Ainslie (Purism) pmic: pmic@4b { 278eb4ea085SAngus Ainslie (Purism) compatible = "rohm,bd71837"; 279eb4ea085SAngus Ainslie (Purism) reg = <0x4b>; 280eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 281eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pmic>; 282eb4ea085SAngus Ainslie (Purism) clocks = <&pmic_osc>; 283eb4ea085SAngus Ainslie (Purism) clock-names = "osc"; 284a4a3550eSKrzysztof Kozlowski #clock-cells = <0>; 285eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_clk"; 286eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio1>; 287d8fa4792SKrzysztof Kozlowski interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 288eb4ea085SAngus Ainslie (Purism) rohm,reset-snvs-powered; 289eb4ea085SAngus Ainslie (Purism) 290eb4ea085SAngus Ainslie (Purism) regulators { 291eb4ea085SAngus Ainslie (Purism) buck1_reg: BUCK1 { 292eb4ea085SAngus Ainslie (Purism) regulator-name = "buck1"; 293eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 294eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 295eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 296edb93de4SGuido Günther regulator-always-on; 297eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 298eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <900000>; 299eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <850000>; 300eb4ea085SAngus Ainslie (Purism) rohm,dvs-suspend-voltage = <800000>; 301eb4ea085SAngus Ainslie (Purism) }; 302eb4ea085SAngus Ainslie (Purism) 303eb4ea085SAngus Ainslie (Purism) buck2_reg: BUCK2 { 304eb4ea085SAngus Ainslie (Purism) regulator-name = "buck2"; 305eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 306eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 307eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 308eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 309eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 310eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <900000>; 311eb4ea085SAngus Ainslie (Purism) }; 312eb4ea085SAngus Ainslie (Purism) 313eb4ea085SAngus Ainslie (Purism) buck3_reg: BUCK3 { 314eb4ea085SAngus Ainslie (Purism) regulator-name = "buck3"; 315eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 316eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 317eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 31876eceb0fSGuido Günther rohm,dvs-run-voltage = <900000>; 319eb4ea085SAngus Ainslie (Purism) }; 320eb4ea085SAngus Ainslie (Purism) 321eb4ea085SAngus Ainslie (Purism) buck4_reg: BUCK4 { 322eb4ea085SAngus Ainslie (Purism) regulator-name = "buck4"; 323eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 324eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 325eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 326eb4ea085SAngus Ainslie (Purism) }; 327eb4ea085SAngus Ainslie (Purism) 328eb4ea085SAngus Ainslie (Purism) buck5_reg: BUCK5 { 329eb4ea085SAngus Ainslie (Purism) regulator-name = "buck5"; 330eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 331eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1350000>; 332eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 333edb93de4SGuido Günther regulator-always-on; 334eb4ea085SAngus Ainslie (Purism) }; 335eb4ea085SAngus Ainslie (Purism) 336eb4ea085SAngus Ainslie (Purism) buck6_reg: BUCK6 { 337eb4ea085SAngus Ainslie (Purism) regulator-name = "buck6"; 338eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 339eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 340eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 341edb93de4SGuido Günther regulator-always-on; 342eb4ea085SAngus Ainslie (Purism) }; 343eb4ea085SAngus Ainslie (Purism) 344eb4ea085SAngus Ainslie (Purism) buck7_reg: BUCK7 { 345eb4ea085SAngus Ainslie (Purism) regulator-name = "buck7"; 346eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1605000>; 347eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1995000>; 348eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 349edb93de4SGuido Günther regulator-always-on; 350eb4ea085SAngus Ainslie (Purism) }; 351eb4ea085SAngus Ainslie (Purism) 352eb4ea085SAngus Ainslie (Purism) buck8_reg: BUCK8 { 353eb4ea085SAngus Ainslie (Purism) regulator-name = "buck8"; 354eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <800000>; 355eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1400000>; 356eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 357edb93de4SGuido Günther regulator-always-on; 358eb4ea085SAngus Ainslie (Purism) }; 359eb4ea085SAngus Ainslie (Purism) 360eb4ea085SAngus Ainslie (Purism) ldo1_reg: LDO1 { 361eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo1"; 362eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 363eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 364eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 365eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 366eb4ea085SAngus Ainslie (Purism) regulator-always-on; 367eb4ea085SAngus Ainslie (Purism) }; 368eb4ea085SAngus Ainslie (Purism) 369eb4ea085SAngus Ainslie (Purism) ldo2_reg: LDO2 { 370eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo2"; 371eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 372eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <900000>; 373eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 374eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 375eb4ea085SAngus Ainslie (Purism) regulator-always-on; 376eb4ea085SAngus Ainslie (Purism) }; 377eb4ea085SAngus Ainslie (Purism) 378eb4ea085SAngus Ainslie (Purism) ldo3_reg: LDO3 { 379eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo3"; 380eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 381eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 382eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 383edb93de4SGuido Günther regulator-always-on; 384eb4ea085SAngus Ainslie (Purism) }; 385eb4ea085SAngus Ainslie (Purism) 386eb4ea085SAngus Ainslie (Purism) ldo4_reg: LDO4 { 387eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo4"; 388eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 389eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 390eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 391edb93de4SGuido Günther regulator-always-on; 392eb4ea085SAngus Ainslie (Purism) }; 393eb4ea085SAngus Ainslie (Purism) 394eb4ea085SAngus Ainslie (Purism) ldo5_reg: LDO5 { 395eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo5"; 396eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 397eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 398edb93de4SGuido Günther regulator-always-on; 399eb4ea085SAngus Ainslie (Purism) }; 400eb4ea085SAngus Ainslie (Purism) 401eb4ea085SAngus Ainslie (Purism) ldo6_reg: LDO6 { 402eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo6"; 403eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 404eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 405eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 406edb93de4SGuido Günther regulator-always-on; 407eb4ea085SAngus Ainslie (Purism) }; 408eb4ea085SAngus Ainslie (Purism) 409eb4ea085SAngus Ainslie (Purism) ldo7_reg: LDO7 { 410eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo7"; 411eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 412eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 413eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 414edb93de4SGuido Günther regulator-always-on; 415eb4ea085SAngus Ainslie (Purism) }; 416eb4ea085SAngus Ainslie (Purism) }; 417eb4ea085SAngus Ainslie (Purism) }; 418eb4ea085SAngus Ainslie (Purism) 4199251dad3SGuido Günther typec_ptn5100: usb-typec@52 { 420eb4ea085SAngus Ainslie (Purism) compatible = "nxp,ptn5110"; 421eb4ea085SAngus Ainslie (Purism) reg = <0x52>; 422eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 423eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_typec>; 424eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 425eb4ea085SAngus Ainslie (Purism) interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 426eb4ea085SAngus Ainslie (Purism) 427eb4ea085SAngus Ainslie (Purism) connector { 428eb4ea085SAngus Ainslie (Purism) compatible = "usb-c-connector"; 429eb4ea085SAngus Ainslie (Purism) label = "USB-C"; 430eb4ea085SAngus Ainslie (Purism) data-role = "dual"; 431eb4ea085SAngus Ainslie (Purism) power-role = "dual"; 432eb4ea085SAngus Ainslie (Purism) try-power-role = "sink"; 433eb4ea085SAngus Ainslie (Purism) source-pdos = <PDO_FIXED(5000, 2000, 434eb4ea085SAngus Ainslie (Purism) PDO_FIXED_USB_COMM | 435eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 436eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP )>; 4375369d191SAngus Ainslie (Purism) sink-pdos = <PDO_FIXED(5000, 3500, PDO_FIXED_USB_COMM | 438eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 439eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP ) 4405369d191SAngus Ainslie (Purism) PDO_VAR(5000, 5000, 3500)>; 441eb4ea085SAngus Ainslie (Purism) op-sink-microwatt = <10000000>; 442eb4ea085SAngus Ainslie (Purism) 443eb4ea085SAngus Ainslie (Purism) ports { 444eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 445eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 446eb4ea085SAngus Ainslie (Purism) 447eb4ea085SAngus Ainslie (Purism) port@0 { 448eb4ea085SAngus Ainslie (Purism) reg = <0>; 449eb4ea085SAngus Ainslie (Purism) 450eb4ea085SAngus Ainslie (Purism) usb_con_hs: endpoint { 451eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_hs>; 452eb4ea085SAngus Ainslie (Purism) }; 453eb4ea085SAngus Ainslie (Purism) }; 454eb4ea085SAngus Ainslie (Purism) 455eb4ea085SAngus Ainslie (Purism) port@1 { 456eb4ea085SAngus Ainslie (Purism) reg = <1>; 457eb4ea085SAngus Ainslie (Purism) 458eb4ea085SAngus Ainslie (Purism) usb_con_ss: endpoint { 459eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_ss>; 460eb4ea085SAngus Ainslie (Purism) }; 461eb4ea085SAngus Ainslie (Purism) }; 462eb4ea085SAngus Ainslie (Purism) }; 463eb4ea085SAngus Ainslie (Purism) }; 464eb4ea085SAngus Ainslie (Purism) }; 465eb4ea085SAngus Ainslie (Purism) 466eb4ea085SAngus Ainslie (Purism) rtc@68 { 467eb4ea085SAngus Ainslie (Purism) compatible = "microcrystal,rv4162"; 468eb4ea085SAngus Ainslie (Purism) reg = <0x68>; 469eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 470eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_rtc>; 471eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio4>; 472eb4ea085SAngus Ainslie (Purism) interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 473eb4ea085SAngus Ainslie (Purism) }; 474eb4ea085SAngus Ainslie (Purism) 475eb4ea085SAngus Ainslie (Purism) charger@6b { /* bq25896 */ 476eb4ea085SAngus Ainslie (Purism) compatible = "ti,bq25890"; 477eb4ea085SAngus Ainslie (Purism) reg = <0x6b>; 478eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 479eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_charger>; 480eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 481eb4ea085SAngus Ainslie (Purism) interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 482eb4ea085SAngus Ainslie (Purism) ti,battery-regulation-voltage = <4192000>; /* 4.192V */ 483eb4ea085SAngus Ainslie (Purism) ti,charge-current = <1600000>; /* 1.6A */ 484eb4ea085SAngus Ainslie (Purism) ti,termination-current = <66000>; /* 66mA */ 485eb4ea085SAngus Ainslie (Purism) ti,precharge-current = <130000>; /* 130mA */ 486eb4ea085SAngus Ainslie (Purism) ti,minimum-sys-voltage = <3000000>; /* 3V */ 487eb4ea085SAngus Ainslie (Purism) ti,boost-voltage = <5000000>; /* 5V */ 488eb4ea085SAngus Ainslie (Purism) ti,boost-max-current = <50000>; /* 50mA */ 489eb4ea085SAngus Ainslie (Purism) }; 490eb4ea085SAngus Ainslie (Purism)}; 491eb4ea085SAngus Ainslie (Purism) 492eb4ea085SAngus Ainslie (Purism)&i2c3 { 493eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 494eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 495eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c3>; 496eb4ea085SAngus Ainslie (Purism) status = "okay"; 497eb4ea085SAngus Ainslie (Purism) 498eb4ea085SAngus Ainslie (Purism) magnetometer@1e { 499eb4ea085SAngus Ainslie (Purism) compatible = "st,lsm9ds1-magn"; 500eb4ea085SAngus Ainslie (Purism) reg = <0x1e>; 501eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 502eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_imu>; 503eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 504106f7b3bSAngus Ainslie (Purism) interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 505eb4ea085SAngus Ainslie (Purism) vdd-supply = <®_3v3_p>; 506eb4ea085SAngus Ainslie (Purism) vddio-supply = <®_3v3_p>; 507eb4ea085SAngus Ainslie (Purism) }; 508eb4ea085SAngus Ainslie (Purism) 509c53f0166SAngus Ainslie (Purism) sgtl5000: audio-codec@a { 510c53f0166SAngus Ainslie (Purism) compatible = "fsl,sgtl5000"; 511c53f0166SAngus Ainslie (Purism) clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 512c53f0166SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 513c53f0166SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 514c53f0166SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 515c53f0166SAngus Ainslie (Purism) #sound-dai-cells = <0>; 516c53f0166SAngus Ainslie (Purism) reg = <0x0a>; 517c53f0166SAngus Ainslie (Purism) VDDD-supply = <®_1v8_p>; 518c53f0166SAngus Ainslie (Purism) VDDIO-supply = <®_3v3_p>; 519c53f0166SAngus Ainslie (Purism) VDDA-supply = <®_3v3_p>; 520c53f0166SAngus Ainslie (Purism) }; 521c53f0166SAngus Ainslie (Purism) 522eb4ea085SAngus Ainslie (Purism) touchscreen@5d { 523eb4ea085SAngus Ainslie (Purism) compatible = "goodix,gt5688"; 524eb4ea085SAngus Ainslie (Purism) reg = <0x5d>; 525eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 526eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_ts>; 527eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 528eb4ea085SAngus Ainslie (Purism) interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 529eb4ea085SAngus Ainslie (Purism) reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 530eb4ea085SAngus Ainslie (Purism) irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 531eb4ea085SAngus Ainslie (Purism) touchscreen-size-x = <720>; 532eb4ea085SAngus Ainslie (Purism) touchscreen-size-y = <1440>; 533eb4ea085SAngus Ainslie (Purism) AVDD28-supply = <®_2v8_p>; 534eb4ea085SAngus Ainslie (Purism) VDDIO-supply = <®_1v8_p>; 535eb4ea085SAngus Ainslie (Purism) }; 536537c00e3SMartin Kepplinger 537ea38ca9aSGuido Günther proximity-sensor@60 { 538ea38ca9aSGuido Günther compatible = "vishay,vcnl4040"; 539ea38ca9aSGuido Günther reg = <0x60>; 540ea38ca9aSGuido Günther pinctrl-0 = <&pinctrl_prox>; 541ea38ca9aSGuido Günther }; 542ea38ca9aSGuido Günther 543537c00e3SMartin Kepplinger accel-gyro@6a { 544537c00e3SMartin Kepplinger compatible = "st,lsm9ds1-imu"; 545537c00e3SMartin Kepplinger reg = <0x6a>; 546537c00e3SMartin Kepplinger vdd-supply = <®_3v3_p>; 547537c00e3SMartin Kepplinger vddio-supply = <®_3v3_p>; 548eef22bb1SMartin Kepplinger mount-matrix = "1", "0", "0", 549eef22bb1SMartin Kepplinger "0", "1", "0", 550eef22bb1SMartin Kepplinger "0", "0", "-1"; 551537c00e3SMartin Kepplinger }; 552eb4ea085SAngus Ainslie (Purism)}; 553eb4ea085SAngus Ainslie (Purism) 554eb4ea085SAngus Ainslie (Purism)&iomuxc { 555eb4ea085SAngus Ainslie (Purism) pinctrl_bl: blgrp { 556eb4ea085SAngus Ainslie (Purism) fsl,pins = < 557eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */ 558eb4ea085SAngus Ainslie (Purism) >; 559eb4ea085SAngus Ainslie (Purism) }; 560eb4ea085SAngus Ainslie (Purism) 561eb4ea085SAngus Ainslie (Purism) pinctrl_bt: btgrp { 562eb4ea085SAngus Ainslie (Purism) fsl,pins = < 563eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */ 564eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */ 565eb4ea085SAngus Ainslie (Purism) >; 566eb4ea085SAngus Ainslie (Purism) }; 567eb4ea085SAngus Ainslie (Purism) 568eb4ea085SAngus Ainslie (Purism) pinctrl_charger: chargergrp { 569eb4ea085SAngus Ainslie (Purism) fsl,pins = < 570eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */ 571eb4ea085SAngus Ainslie (Purism) >; 572eb4ea085SAngus Ainslie (Purism) }; 573eb4ea085SAngus Ainslie (Purism) 574eb4ea085SAngus Ainslie (Purism) pinctrl_fec1: fec1grp { 575eb4ea085SAngus Ainslie (Purism) fsl,pins = < 576eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 577eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 578eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 579eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 580eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 581eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 582eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 583eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 584eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 585eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 586eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 587eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 588eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 589eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 590eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 591eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f 592eb4ea085SAngus Ainslie (Purism) >; 593eb4ea085SAngus Ainslie (Purism) }; 594eb4ea085SAngus Ainslie (Purism) 595eb4ea085SAngus Ainslie (Purism) pinctrl_ts: tsgrp { 596eb4ea085SAngus Ainslie (Purism) fsl,pins = < 597eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */ 598eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ 599eb4ea085SAngus Ainslie (Purism) >; 600eb4ea085SAngus Ainslie (Purism) }; 601eb4ea085SAngus Ainslie (Purism) 602eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_leds: gpioledgrp { 603eb4ea085SAngus Ainslie (Purism) fsl,pins = < 604eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 605eb4ea085SAngus Ainslie (Purism) >; 606eb4ea085SAngus Ainslie (Purism) }; 607eb4ea085SAngus Ainslie (Purism) 608eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_keys: gpiokeygrp { 609eb4ea085SAngus Ainslie (Purism) fsl,pins = < 610eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 611eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16 612eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180 /* HP_DET */ 6133ef506b3SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ 614eb4ea085SAngus Ainslie (Purism) >; 615eb4ea085SAngus Ainslie (Purism) }; 616eb4ea085SAngus Ainslie (Purism) 617eb4ea085SAngus Ainslie (Purism) pinctrl_haptic: hapticgrp { 618eb4ea085SAngus Ainslie (Purism) fsl,pins = < 619eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ 620eb4ea085SAngus Ainslie (Purism) >; 621eb4ea085SAngus Ainslie (Purism) }; 622eb4ea085SAngus Ainslie (Purism) 623eb4ea085SAngus Ainslie (Purism) pinctrl_i2c1: i2c1grp { 624eb4ea085SAngus Ainslie (Purism) fsl,pins = < 625eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f 626eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f 627eb4ea085SAngus Ainslie (Purism) >; 628eb4ea085SAngus Ainslie (Purism) }; 629eb4ea085SAngus Ainslie (Purism) 630eb4ea085SAngus Ainslie (Purism) pinctrl_i2c3: i2c3grp { 631eb4ea085SAngus Ainslie (Purism) fsl,pins = < 632eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f 633eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f 634eb4ea085SAngus Ainslie (Purism) >; 635eb4ea085SAngus Ainslie (Purism) }; 636eb4ea085SAngus Ainslie (Purism) 637eb4ea085SAngus Ainslie (Purism) pinctrl_imu: imugrp { 638eb4ea085SAngus Ainslie (Purism) fsl,pins = < 639eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */ 640eb4ea085SAngus Ainslie (Purism) >; 641eb4ea085SAngus Ainslie (Purism) }; 642eb4ea085SAngus Ainslie (Purism) 643eb4ea085SAngus Ainslie (Purism) pinctrl_pmic: pmicgrp { 644eb4ea085SAngus Ainslie (Purism) fsl,pins = < 645eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */ 646eb4ea085SAngus Ainslie (Purism) >; 647eb4ea085SAngus Ainslie (Purism) }; 648eb4ea085SAngus Ainslie (Purism) 649ea38ca9aSGuido Günther pinctrl_prox: proxgrp { 650ea38ca9aSGuido Günther fsl,pins = < 651ea38ca9aSGuido Günther MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */ 652ea38ca9aSGuido Günther >; 653ea38ca9aSGuido Günther }; 654ea38ca9aSGuido Günther 655eb4ea085SAngus Ainslie (Purism) pinctrl_pwr_en: pwrengrp { 656eb4ea085SAngus Ainslie (Purism) fsl,pins = < 657eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06 658eb4ea085SAngus Ainslie (Purism) >; 659eb4ea085SAngus Ainslie (Purism) }; 660eb4ea085SAngus Ainslie (Purism) 661eb4ea085SAngus Ainslie (Purism) pinctrl_rtc: rtcgrp { 662eb4ea085SAngus Ainslie (Purism) fsl,pins = < 663eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */ 664eb4ea085SAngus Ainslie (Purism) >; 665eb4ea085SAngus Ainslie (Purism) }; 666eb4ea085SAngus Ainslie (Purism) 667c53f0166SAngus Ainslie (Purism) pinctrl_sai2: sai2grp { 668c53f0166SAngus Ainslie (Purism) fsl,pins = < 669c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 670c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 671c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 672c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 673c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 674c53f0166SAngus Ainslie (Purism) >; 675c53f0166SAngus Ainslie (Purism) }; 676c53f0166SAngus Ainslie (Purism) 6777f7b7997SAngus Ainslie (Purism) pinctrl_sai6: sai6grp { 6787f7b7997SAngus Ainslie (Purism) fsl,pins = < 6797f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 6807f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 6817f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 6827f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 6837f7b7997SAngus Ainslie (Purism) >; 6847f7b7997SAngus Ainslie (Purism) }; 6857f7b7997SAngus Ainslie (Purism) 686eb4ea085SAngus Ainslie (Purism) pinctrl_typec: typecgrp { 687eb4ea085SAngus Ainslie (Purism) fsl,pins = < 688eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 689eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80 690eb4ea085SAngus Ainslie (Purism) >; 691eb4ea085SAngus Ainslie (Purism) }; 692eb4ea085SAngus Ainslie (Purism) 693eb4ea085SAngus Ainslie (Purism) pinctrl_uart1: uart1grp { 694eb4ea085SAngus Ainslie (Purism) fsl,pins = < 695eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 696eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 697eb4ea085SAngus Ainslie (Purism) >; 698eb4ea085SAngus Ainslie (Purism) }; 699eb4ea085SAngus Ainslie (Purism) 700eb4ea085SAngus Ainslie (Purism) pinctrl_uart2: uart2grp { 701eb4ea085SAngus Ainslie (Purism) fsl,pins = < 702eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 703eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 704eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 705eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 706eb4ea085SAngus Ainslie (Purism) >; 707eb4ea085SAngus Ainslie (Purism) }; 708eb4ea085SAngus Ainslie (Purism) 709eb4ea085SAngus Ainslie (Purism) pinctrl_uart3: uart3grp { 710eb4ea085SAngus Ainslie (Purism) fsl,pins = < 711eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 712eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 713eb4ea085SAngus Ainslie (Purism) >; 714eb4ea085SAngus Ainslie (Purism) }; 715eb4ea085SAngus Ainslie (Purism) 716eb4ea085SAngus Ainslie (Purism) pinctrl_uart4: uart4grp { 717eb4ea085SAngus Ainslie (Purism) fsl,pins = < 718eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 719eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 720eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 721eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 722eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49 723eb4ea085SAngus Ainslie (Purism) >; 724eb4ea085SAngus Ainslie (Purism) }; 725eb4ea085SAngus Ainslie (Purism) 726eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc1: usdhc1grp { 727eb4ea085SAngus Ainslie (Purism) fsl,pins = < 728eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 729eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 730eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 731eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 732eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 733eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 734eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 735eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 736eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 737eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 738eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 739eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 740eb4ea085SAngus Ainslie (Purism) >; 741eb4ea085SAngus Ainslie (Purism) }; 742eb4ea085SAngus Ainslie (Purism) 743ae560c43SKrzysztof Kozlowski pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 744eb4ea085SAngus Ainslie (Purism) fsl,pins = < 745eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 746eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 747eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 748eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 749eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 750eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 751eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 752eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 753eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 754eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 755eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 756eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 757eb4ea085SAngus Ainslie (Purism) >; 758eb4ea085SAngus Ainslie (Purism) }; 759eb4ea085SAngus Ainslie (Purism) 760ae560c43SKrzysztof Kozlowski pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 761eb4ea085SAngus Ainslie (Purism) fsl,pins = < 762eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 763eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 764eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 765eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 766eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 767eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 768eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 769eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 770eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 771eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 772eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 773eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 774eb4ea085SAngus Ainslie (Purism) >; 775eb4ea085SAngus Ainslie (Purism) }; 776eb4ea085SAngus Ainslie (Purism) 777ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_pwr: usdhc2pwrgrp { 778eb4ea085SAngus Ainslie (Purism) fsl,pins = < 779eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 780eb4ea085SAngus Ainslie (Purism) >; 781eb4ea085SAngus Ainslie (Purism) }; 782eb4ea085SAngus Ainslie (Purism) 783ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_gpio: usdhc2gpiogrp { 784eb4ea085SAngus Ainslie (Purism) fsl,pins = < 785eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ 786eb4ea085SAngus Ainslie (Purism) >; 787eb4ea085SAngus Ainslie (Purism) }; 788eb4ea085SAngus Ainslie (Purism) 789eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2: usdhc2grp { 790eb4ea085SAngus Ainslie (Purism) fsl,pins = < 791eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 792eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 793eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 794eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 795eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 796eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 797eb4ea085SAngus Ainslie (Purism) >; 798eb4ea085SAngus Ainslie (Purism) }; 799eb4ea085SAngus Ainslie (Purism) 800ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 801eb4ea085SAngus Ainslie (Purism) fsl,pins = < 802eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 803eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 804eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 805eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 806eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 807eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 808eb4ea085SAngus Ainslie (Purism) >; 809eb4ea085SAngus Ainslie (Purism) }; 810eb4ea085SAngus Ainslie (Purism) 811ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 812eb4ea085SAngus Ainslie (Purism) fsl,pins = < 813eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 814eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf 815eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf 816eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf 817eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf 818eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf 819eb4ea085SAngus Ainslie (Purism) >; 820eb4ea085SAngus Ainslie (Purism) }; 821eb4ea085SAngus Ainslie (Purism) 822eb4ea085SAngus Ainslie (Purism) pinctrl_wdog: wdoggrp { 823eb4ea085SAngus Ainslie (Purism) fsl,pins = < 824eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 825eb4ea085SAngus Ainslie (Purism) >; 826eb4ea085SAngus Ainslie (Purism) }; 827eb4ea085SAngus Ainslie (Purism) 828eb4ea085SAngus Ainslie (Purism) pinctrl_wifi_pwr_en: wifipwrengrp { 829eb4ea085SAngus Ainslie (Purism) fsl,pins = < 830eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 831eb4ea085SAngus Ainslie (Purism) >; 832eb4ea085SAngus Ainslie (Purism) }; 833eb4ea085SAngus Ainslie (Purism) 834eb4ea085SAngus Ainslie (Purism) pinctrl_wwan: wwangrp { 835eb4ea085SAngus Ainslie (Purism) fsl,pins = < 836eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */ 837eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ 838eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */ 839eb4ea085SAngus Ainslie (Purism) >; 840eb4ea085SAngus Ainslie (Purism) }; 841eb4ea085SAngus Ainslie (Purism)}; 842eb4ea085SAngus Ainslie (Purism) 843e8151ef3SGuido Günther&lcdif { 844e8151ef3SGuido Günther status = "okay"; 845e8151ef3SGuido Günther}; 846e8151ef3SGuido Günther 847e8151ef3SGuido Günther&mipi_dsi { 848e8151ef3SGuido Günther status = "okay"; 849e8151ef3SGuido Günther #address-cells = <1>; 850e8151ef3SGuido Günther #size-cells = <0>; 851e8151ef3SGuido Günther 852e8151ef3SGuido Günther panel@0 { 853e8151ef3SGuido Günther compatible = "rocktech,jh057n00900"; 854e8151ef3SGuido Günther reg = <0>; 855e8151ef3SGuido Günther backlight = <&backlight_dsi>; 856e8151ef3SGuido Günther reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; 857e8151ef3SGuido Günther iovcc-supply = <®_1v8_p>; 858e8151ef3SGuido Günther vcc-supply = <®_2v8_p>; 859e8151ef3SGuido Günther port { 860e8151ef3SGuido Günther panel_in: endpoint { 861e8151ef3SGuido Günther remote-endpoint = <&mipi_dsi_out>; 862e8151ef3SGuido Günther }; 863e8151ef3SGuido Günther }; 864e8151ef3SGuido Günther }; 865e8151ef3SGuido Günther 866e8151ef3SGuido Günther ports { 867e8151ef3SGuido Günther port@1 { 868e8151ef3SGuido Günther reg = <1>; 869e8151ef3SGuido Günther mipi_dsi_out: endpoint { 870e8151ef3SGuido Günther remote-endpoint = <&panel_in>; 871e8151ef3SGuido Günther }; 872e8151ef3SGuido Günther }; 873e8151ef3SGuido Günther }; 874e8151ef3SGuido Günther}; 875e8151ef3SGuido Günther 876eb4ea085SAngus Ainslie (Purism)&pgc_gpu { 877eb4ea085SAngus Ainslie (Purism) power-supply = <&buck3_reg>; 878eb4ea085SAngus Ainslie (Purism)}; 879eb4ea085SAngus Ainslie (Purism) 880eb4ea085SAngus Ainslie (Purism)&pgc_vpu { 881eb4ea085SAngus Ainslie (Purism) power-supply = <&buck4_reg>; 882eb4ea085SAngus Ainslie (Purism)}; 883eb4ea085SAngus Ainslie (Purism) 884eb4ea085SAngus Ainslie (Purism)&pwm1 { 885eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 886eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_bl>; 887eb4ea085SAngus Ainslie (Purism) status = "okay"; 888eb4ea085SAngus Ainslie (Purism)}; 889eb4ea085SAngus Ainslie (Purism) 89001407158SAngus Ainslie (Purism)&snvs_pwrkey { 89101407158SAngus Ainslie (Purism) status = "okay"; 89201407158SAngus Ainslie (Purism)}; 893eb4ea085SAngus Ainslie (Purism) 894ff38c1ddSGuido Günther&snvs_rtc { 895ff38c1ddSGuido Günther status = "disabled"; 896ff38c1ddSGuido Günther}; 897ff38c1ddSGuido Günther 898c53f0166SAngus Ainslie (Purism)&sai2 { 899c53f0166SAngus Ainslie (Purism) pinctrl-names = "default"; 900c53f0166SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_sai2>; 901c53f0166SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 902c53f0166SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 903c53f0166SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 904c53f0166SAngus Ainslie (Purism) status = "okay"; 905c53f0166SAngus Ainslie (Purism)}; 906c53f0166SAngus Ainslie (Purism) 9077f7b7997SAngus Ainslie (Purism)&sai6 { 9087f7b7997SAngus Ainslie (Purism) pinctrl-names = "default"; 9097f7b7997SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_sai6>; 9107f7b7997SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; 9117f7b7997SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 9127f7b7997SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 9137f7b7997SAngus Ainslie (Purism) fsl,sai-synchronous-rx; 9147f7b7997SAngus Ainslie (Purism) status = "okay"; 9157f7b7997SAngus Ainslie (Purism)}; 9167f7b7997SAngus Ainslie (Purism) 917eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */ 918eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 919eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart1>; 920eb4ea085SAngus Ainslie (Purism) status = "okay"; 921eb4ea085SAngus Ainslie (Purism)}; 922eb4ea085SAngus Ainslie (Purism) 923eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */ 924eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 925eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart3>; 926eb4ea085SAngus Ainslie (Purism) status = "okay"; 927eb4ea085SAngus Ainslie (Purism)}; 928eb4ea085SAngus Ainslie (Purism) 929eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */ 930eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 931eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; 932eb4ea085SAngus Ainslie (Purism) uart-has-rtscts; 933eb4ea085SAngus Ainslie (Purism) status = "okay"; 934eb4ea085SAngus Ainslie (Purism)}; 935eb4ea085SAngus Ainslie (Purism) 936eb4ea085SAngus Ainslie (Purism)&usb3_phy0 { 937dde061b8SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 938eb4ea085SAngus Ainslie (Purism) status = "okay"; 939eb4ea085SAngus Ainslie (Purism)}; 940eb4ea085SAngus Ainslie (Purism) 941eb4ea085SAngus Ainslie (Purism)&usb3_phy1 { 942eb4ea085SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 943eb4ea085SAngus Ainslie (Purism) status = "okay"; 944eb4ea085SAngus Ainslie (Purism)}; 945eb4ea085SAngus Ainslie (Purism) 946eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 { 947eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 948eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 949eb4ea085SAngus Ainslie (Purism) dr_mode = "otg"; 950eb4ea085SAngus Ainslie (Purism) status = "okay"; 951eb4ea085SAngus Ainslie (Purism) 952eb4ea085SAngus Ainslie (Purism) port@0 { 953eb4ea085SAngus Ainslie (Purism) reg = <0>; 954eb4ea085SAngus Ainslie (Purism) 955eb4ea085SAngus Ainslie (Purism) typec_hs: endpoint { 956eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_hs>; 957eb4ea085SAngus Ainslie (Purism) }; 958eb4ea085SAngus Ainslie (Purism) }; 959eb4ea085SAngus Ainslie (Purism) 960eb4ea085SAngus Ainslie (Purism) port@1 { 961eb4ea085SAngus Ainslie (Purism) reg = <1>; 962eb4ea085SAngus Ainslie (Purism) 963eb4ea085SAngus Ainslie (Purism) typec_ss: endpoint { 964eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_ss>; 965eb4ea085SAngus Ainslie (Purism) }; 966eb4ea085SAngus Ainslie (Purism) }; 967eb4ea085SAngus Ainslie (Purism)}; 968eb4ea085SAngus Ainslie (Purism) 969eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 { 970eb4ea085SAngus Ainslie (Purism) dr_mode = "host"; 971eb4ea085SAngus Ainslie (Purism) status = "okay"; 972eb4ea085SAngus Ainslie (Purism)}; 973eb4ea085SAngus Ainslie (Purism) 974eb4ea085SAngus Ainslie (Purism)&usdhc1 { 975e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 976e045f044SAnson Huang assigned-clock-rates = <400000000>; 977eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 978eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc1>; 979eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 980eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 981eb4ea085SAngus Ainslie (Purism) bus-width = <8>; 982eb4ea085SAngus Ainslie (Purism) non-removable; 983eb4ea085SAngus Ainslie (Purism) status = "okay"; 984eb4ea085SAngus Ainslie (Purism)}; 985eb4ea085SAngus Ainslie (Purism) 986eb4ea085SAngus Ainslie (Purism)&usdhc2 { 987e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 988e045f044SAnson Huang assigned-clock-rates = <200000000>; 989eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 990eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2>; 991eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 992eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 993eb4ea085SAngus Ainslie (Purism) bus-width = <4>; 994eb4ea085SAngus Ainslie (Purism) vmmc-supply = <®_usdhc2_vmmc>; 995eb4ea085SAngus Ainslie (Purism) power-supply = <&wifi_pwr_en>; 9969dae8563SAngus Ainslie (Purism) broken-cd; 997eb4ea085SAngus Ainslie (Purism) disable-wp; 998eb4ea085SAngus Ainslie (Purism) cap-sdio-irq; 999eb4ea085SAngus Ainslie (Purism) keep-power-in-suspend; 1000eb4ea085SAngus Ainslie (Purism) wakeup-source; 1001eb4ea085SAngus Ainslie (Purism) status = "okay"; 1002eb4ea085SAngus Ainslie (Purism)}; 1003eb4ea085SAngus Ainslie (Purism) 1004eb4ea085SAngus Ainslie (Purism)&wdog1 { 1005eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 1006eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wdog>; 1007eb4ea085SAngus Ainslie (Purism) fsl,ext-reset-output; 1008eb4ea085SAngus Ainslie (Purism) status = "okay"; 1009eb4ea085SAngus Ainslie (Purism)}; 1010