1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+
2eb4ea085SAngus Ainslie (Purism)/*
3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC
4eb4ea085SAngus Ainslie (Purism) */
5eb4ea085SAngus Ainslie (Purism)
6eb4ea085SAngus Ainslie (Purism)/dts-v1/;
7eb4ea085SAngus Ainslie (Purism)
8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h"
9eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h"
10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h"
11eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi"
12eb4ea085SAngus Ainslie (Purism)
13eb4ea085SAngus Ainslie (Purism)/ {
14eb4ea085SAngus Ainslie (Purism)	model = "Purism Librem 5 devkit";
15eb4ea085SAngus Ainslie (Purism)	compatible = "purism,librem5-devkit", "fsl,imx8mq";
16eb4ea085SAngus Ainslie (Purism)
17eb4ea085SAngus Ainslie (Purism)	backlight_dsi: backlight-dsi {
18eb4ea085SAngus Ainslie (Purism)		compatible = "pwm-backlight";
19eb4ea085SAngus Ainslie (Purism)		/* 200 Hz for the PAM2841 */
20eb4ea085SAngus Ainslie (Purism)		pwms = <&pwm1 0 5000000>;
21eb4ea085SAngus Ainslie (Purism)		brightness-levels = <0 100>;
22eb4ea085SAngus Ainslie (Purism)		num-interpolated-steps = <100>;
23eb4ea085SAngus Ainslie (Purism)		/* Default brightness level (index into the array defined by */
24eb4ea085SAngus Ainslie (Purism)		/* the "brightness-levels" property) */
25eb4ea085SAngus Ainslie (Purism)		default-brightness-level = <0>;
26eb4ea085SAngus Ainslie (Purism)		power-supply = <&reg_22v4_p>;
27eb4ea085SAngus Ainslie (Purism)	};
28eb4ea085SAngus Ainslie (Purism)
29eb4ea085SAngus Ainslie (Purism)	chosen {
30eb4ea085SAngus Ainslie (Purism)		stdout-path = &uart1;
31eb4ea085SAngus Ainslie (Purism)	};
32eb4ea085SAngus Ainslie (Purism)
33eb4ea085SAngus Ainslie (Purism)	gpio-keys {
34eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-keys";
35eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
36eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_keys>;
37eb4ea085SAngus Ainslie (Purism)
38eb4ea085SAngus Ainslie (Purism)		btn1 {
39eb4ea085SAngus Ainslie (Purism)			label = "VOL_UP";
40eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
41eb4ea085SAngus Ainslie (Purism)			wakeup-source;
42eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEUP>;
43eb4ea085SAngus Ainslie (Purism)		};
44eb4ea085SAngus Ainslie (Purism)
45eb4ea085SAngus Ainslie (Purism)		btn2 {
46eb4ea085SAngus Ainslie (Purism)			label = "VOL_DOWN";
47eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
48eb4ea085SAngus Ainslie (Purism)			wakeup-source;
49eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEDOWN>;
50eb4ea085SAngus Ainslie (Purism)		};
51eb4ea085SAngus Ainslie (Purism)
52eb4ea085SAngus Ainslie (Purism)		hp-det {
53eb4ea085SAngus Ainslie (Purism)			label = "HP_DET";
54eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
55eb4ea085SAngus Ainslie (Purism)			wakeup-source;
56eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_HP>;
57eb4ea085SAngus Ainslie (Purism)		};
583ef506b3SAngus Ainslie (Purism)
593ef506b3SAngus Ainslie (Purism)		wwan-wake {
603ef506b3SAngus Ainslie (Purism)			label = "WWAN_WAKE";
613ef506b3SAngus Ainslie (Purism)			gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
623ef506b3SAngus Ainslie (Purism)			interrupt-parent = <&gpio3>;
633ef506b3SAngus Ainslie (Purism)			interrupts = <8 GPIO_ACTIVE_LOW>;
643ef506b3SAngus Ainslie (Purism)			wakeup-source;
653ef506b3SAngus Ainslie (Purism)			linux,code = <KEY_PHONE>;
663ef506b3SAngus Ainslie (Purism)		};
67eb4ea085SAngus Ainslie (Purism)	};
68eb4ea085SAngus Ainslie (Purism)
69eb4ea085SAngus Ainslie (Purism)	leds {
70eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-leds";
71eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
72eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_leds>;
73eb4ea085SAngus Ainslie (Purism)
74eb4ea085SAngus Ainslie (Purism)		led1 {
75eb4ea085SAngus Ainslie (Purism)			label = "LED 1";
76eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
77eb4ea085SAngus Ainslie (Purism)			default-state = "off";
78eb4ea085SAngus Ainslie (Purism)		};
79eb4ea085SAngus Ainslie (Purism)	};
80eb4ea085SAngus Ainslie (Purism)
81eb4ea085SAngus Ainslie (Purism)	pmic_osc: clock-pmic {
82eb4ea085SAngus Ainslie (Purism)		compatible = "fixed-clock";
83eb4ea085SAngus Ainslie (Purism)		#clock-cells = <0>;
84eb4ea085SAngus Ainslie (Purism)		clock-frequency = <32768>;
85eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_osc";
86eb4ea085SAngus Ainslie (Purism)	};
87eb4ea085SAngus Ainslie (Purism)
88eb4ea085SAngus Ainslie (Purism)	reg_1v8_p: regulator-1v8-p {
89eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
90eb4ea085SAngus Ainslie (Purism)		regulator-name = "1v8_p";
91eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <1800000>;
92eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <1800000>;
93eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
94eb4ea085SAngus Ainslie (Purism)	};
95eb4ea085SAngus Ainslie (Purism)
96eb4ea085SAngus Ainslie (Purism)	reg_2v8_p: regulator-2v8-p {
97eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
98eb4ea085SAngus Ainslie (Purism)		regulator-name = "2v8_p";
99eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <2800000>;
100eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <2800000>;
101eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
102eb4ea085SAngus Ainslie (Purism)	};
103eb4ea085SAngus Ainslie (Purism)
104eb4ea085SAngus Ainslie (Purism)	reg_3v3_p: regulator-3v3-p {
105eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
106eb4ea085SAngus Ainslie (Purism)		regulator-name = "3v3_p";
107eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
108eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
109eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
110eb4ea085SAngus Ainslie (Purism)
111eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
112eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
113eb4ea085SAngus Ainslie (Purism)		};
114eb4ea085SAngus Ainslie (Purism)	};
115eb4ea085SAngus Ainslie (Purism)
116eb4ea085SAngus Ainslie (Purism)	reg_5v_p: regulator-5v-p {
117eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
118eb4ea085SAngus Ainslie (Purism)		regulator-name = "5v_p";
119eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <5000000>;
120eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <5000000>;
121eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
122eb4ea085SAngus Ainslie (Purism)
123eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
124eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
125eb4ea085SAngus Ainslie (Purism)		};
126eb4ea085SAngus Ainslie (Purism)	};
127eb4ea085SAngus Ainslie (Purism)
128eb4ea085SAngus Ainslie (Purism)	reg_22v4_p: regulator-22v4-p  {
129eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
130eb4ea085SAngus Ainslie (Purism)		regulator-name = "22v4_P";
131eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <22400000>;
132eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <22400000>;
133eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
134eb4ea085SAngus Ainslie (Purism)	};
135eb4ea085SAngus Ainslie (Purism)
136eb4ea085SAngus Ainslie (Purism)	reg_pwr_en: regulator-pwr-en {
137eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
138eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
139eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pwr_en>;
140eb4ea085SAngus Ainslie (Purism)		regulator-name = "PWR_EN";
141eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
142eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
143eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
144eb4ea085SAngus Ainslie (Purism)		enable-active-high;
145eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
146eb4ea085SAngus Ainslie (Purism)	};
147eb4ea085SAngus Ainslie (Purism)
148eb4ea085SAngus Ainslie (Purism)	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
149eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
150eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
151eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_usdhc2_pwr>;
152eb4ea085SAngus Ainslie (Purism)		regulator-name = "VSD_3V3";
153eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
154eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
155eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
156eb4ea085SAngus Ainslie (Purism)		enable-active-high;
157eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
158eb4ea085SAngus Ainslie (Purism)	};
159eb4ea085SAngus Ainslie (Purism)
1607f7b7997SAngus Ainslie (Purism)	wwan_codec: sound-wwan-codec {
1617f7b7997SAngus Ainslie (Purism)		compatible = "option,gtm601";
1627f7b7997SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
1637f7b7997SAngus Ainslie (Purism)	};
1647f7b7997SAngus Ainslie (Purism)
165c53f0166SAngus Ainslie (Purism)	sound {
166c53f0166SAngus Ainslie (Purism)		compatible = "simple-audio-card";
167c53f0166SAngus Ainslie (Purism)		simple-audio-card,name = "sgtl5000";
168c53f0166SAngus Ainslie (Purism)		simple-audio-card,format = "i2s";
169c53f0166SAngus Ainslie (Purism)		simple-audio-card,widgets =
170c53f0166SAngus Ainslie (Purism)			"Microphone", "Microphone Jack",
171c53f0166SAngus Ainslie (Purism)			"Headphone", "Headphone Jack",
172c53f0166SAngus Ainslie (Purism)			"Speaker", "Speaker Ext",
173c53f0166SAngus Ainslie (Purism)			"Line", "Line In Jack";
174c53f0166SAngus Ainslie (Purism)		simple-audio-card,routing =
175c53f0166SAngus Ainslie (Purism)			"MIC_IN", "Microphone Jack",
176c53f0166SAngus Ainslie (Purism)			"Microphone Jack", "Mic Bias",
177c53f0166SAngus Ainslie (Purism)			"LINE_IN", "Line In Jack",
178c53f0166SAngus Ainslie (Purism)			"Headphone Jack", "HP_OUT",
179c53f0166SAngus Ainslie (Purism)			"Speaker Ext", "LINE_OUT";
180c53f0166SAngus Ainslie (Purism)
181c53f0166SAngus Ainslie (Purism)		simple-audio-card,cpu {
182c53f0166SAngus Ainslie (Purism)			sound-dai = <&sai2>;
183c53f0166SAngus Ainslie (Purism)		};
184c53f0166SAngus Ainslie (Purism)
185c53f0166SAngus Ainslie (Purism)		simple-audio-card,codec {
186c53f0166SAngus Ainslie (Purism)			sound-dai = <&sgtl5000>;
187c53f0166SAngus Ainslie (Purism)			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
188c53f0166SAngus Ainslie (Purism)			frame-master;
189c53f0166SAngus Ainslie (Purism)			bitclock-master;
190c53f0166SAngus Ainslie (Purism)		};
191c53f0166SAngus Ainslie (Purism)	};
192c53f0166SAngus Ainslie (Purism)
1937f7b7997SAngus Ainslie (Purism)	sound-wwan {
1947f7b7997SAngus Ainslie (Purism)		compatible = "simple-audio-card";
1957f7b7997SAngus Ainslie (Purism)		simple-audio-card,name = "SIMCom SIM7100";
1967f7b7997SAngus Ainslie (Purism)		simple-audio-card,format = "dsp_a";
1977f7b7997SAngus Ainslie (Purism)
1987f7b7997SAngus Ainslie (Purism)		simple-audio-card,cpu {
1997f7b7997SAngus Ainslie (Purism)			sound-dai = <&sai6>;
2007f7b7997SAngus Ainslie (Purism)		};
2017f7b7997SAngus Ainslie (Purism)
2027f7b7997SAngus Ainslie (Purism)		telephony_link_master: simple-audio-card,codec {
2037f7b7997SAngus Ainslie (Purism)			sound-dai = <&wwan_codec>;
2047f7b7997SAngus Ainslie (Purism)			frame-master;
2057f7b7997SAngus Ainslie (Purism)			bitclock-master;
2067f7b7997SAngus Ainslie (Purism)		};
2077f7b7997SAngus Ainslie (Purism)	};
2087f7b7997SAngus Ainslie (Purism)
209eb4ea085SAngus Ainslie (Purism)	vibrator {
210eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-vibrator";
211eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
212eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_haptic>;
213eb4ea085SAngus Ainslie (Purism)	        enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
214eb4ea085SAngus Ainslie (Purism)		vcc-supply = <&reg_3v3_p>;
215eb4ea085SAngus Ainslie (Purism)	};
216eb4ea085SAngus Ainslie (Purism)
217eb4ea085SAngus Ainslie (Purism)	wifi_pwr_en: regulator-wifi-en {
218eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
219eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
220eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
221eb4ea085SAngus Ainslie (Purism)		regulator-name = "WIFI_EN";
222eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
223eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
224eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
225eb4ea085SAngus Ainslie (Purism)		enable-active-high;
226eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
227eb4ea085SAngus Ainslie (Purism)	};
228eb4ea085SAngus Ainslie (Purism)};
229eb4ea085SAngus Ainslie (Purism)
230eb4ea085SAngus Ainslie (Purism)&clk {
231eb4ea085SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
232eb4ea085SAngus Ainslie (Purism)	assigned-clock-rates = <786432000>, <722534400>;
233eb4ea085SAngus Ainslie (Purism)};
234eb4ea085SAngus Ainslie (Purism)
2359d9005a5SGuido Günther&dphy {
2369d9005a5SGuido Günther	status = "okay";
2379d9005a5SGuido Günther};
2389d9005a5SGuido Günther
239eb4ea085SAngus Ainslie (Purism)&fec1 {
240eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
241eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_fec1>;
242eb4ea085SAngus Ainslie (Purism)	phy-mode = "rgmii-id";
243eb4ea085SAngus Ainslie (Purism)	phy-handle = <&ethphy0>;
244eb4ea085SAngus Ainslie (Purism)	fsl,magic-packet;
245eb4ea085SAngus Ainslie (Purism)	phy-supply = <&reg_3v3_p>;
246eb4ea085SAngus Ainslie (Purism)	status = "okay";
247eb4ea085SAngus Ainslie (Purism)
248eb4ea085SAngus Ainslie (Purism)	mdio {
249eb4ea085SAngus Ainslie (Purism)		#address-cells = <1>;
250eb4ea085SAngus Ainslie (Purism)		#size-cells = <0>;
251eb4ea085SAngus Ainslie (Purism)
252eb4ea085SAngus Ainslie (Purism)		ethphy0: ethernet-phy@1 {
253eb4ea085SAngus Ainslie (Purism)			compatible = "ethernet-phy-ieee802.3-c22";
254eb4ea085SAngus Ainslie (Purism)			reg = <1>;
255eb4ea085SAngus Ainslie (Purism)		};
256eb4ea085SAngus Ainslie (Purism)	};
257eb4ea085SAngus Ainslie (Purism)};
258eb4ea085SAngus Ainslie (Purism)
259eb4ea085SAngus Ainslie (Purism)&i2c1 {
260eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
261eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
262eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c1>;
263eb4ea085SAngus Ainslie (Purism)	status = "okay";
264eb4ea085SAngus Ainslie (Purism)
265eb4ea085SAngus Ainslie (Purism)	pmic: pmic@4b {
266eb4ea085SAngus Ainslie (Purism)		compatible = "rohm,bd71837";
267eb4ea085SAngus Ainslie (Purism)		reg = <0x4b>;
268eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
269eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pmic>;
270eb4ea085SAngus Ainslie (Purism)		clocks = <&pmic_osc>;
271eb4ea085SAngus Ainslie (Purism)		clock-names = "osc";
272eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_clk";
273eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio1>;
274eb4ea085SAngus Ainslie (Purism)		interrupts = <3 GPIO_ACTIVE_LOW>;
275eb4ea085SAngus Ainslie (Purism)		interrupt-names = "irq";
276eb4ea085SAngus Ainslie (Purism)		rohm,reset-snvs-powered;
277eb4ea085SAngus Ainslie (Purism)
278eb4ea085SAngus Ainslie (Purism)		regulators {
279eb4ea085SAngus Ainslie (Purism)			buck1_reg: BUCK1 {
280eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck1";
281eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
282eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
283eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
284eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
285eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <900000>;
286eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <850000>;
287eb4ea085SAngus Ainslie (Purism)				rohm,dvs-suspend-voltage = <800000>;
288eb4ea085SAngus Ainslie (Purism)			};
289eb4ea085SAngus Ainslie (Purism)
290eb4ea085SAngus Ainslie (Purism)			buck2_reg: BUCK2 {
291eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck2";
292eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
293eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
294eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
295eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
296eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
297eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <900000>;
298eb4ea085SAngus Ainslie (Purism)			};
299eb4ea085SAngus Ainslie (Purism)
300eb4ea085SAngus Ainslie (Purism)			buck3_reg: BUCK3 {
301eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck3";
302eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
303eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
304eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
305eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
306eb4ea085SAngus Ainslie (Purism)			};
307eb4ea085SAngus Ainslie (Purism)
308eb4ea085SAngus Ainslie (Purism)			buck4_reg: BUCK4 {
309eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck4";
310eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
311eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
312eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
313eb4ea085SAngus Ainslie (Purism)			};
314eb4ea085SAngus Ainslie (Purism)
315eb4ea085SAngus Ainslie (Purism)			buck5_reg: BUCK5 {
316eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck5";
317eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
318eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1350000>;
319eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
320eb4ea085SAngus Ainslie (Purism)			};
321eb4ea085SAngus Ainslie (Purism)
322eb4ea085SAngus Ainslie (Purism)			buck6_reg: BUCK6 {
323eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck6";
324eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
325eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
326eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
327eb4ea085SAngus Ainslie (Purism)			};
328eb4ea085SAngus Ainslie (Purism)
329eb4ea085SAngus Ainslie (Purism)			buck7_reg: BUCK7 {
330eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck7";
331eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1605000>;
332eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1995000>;
333eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
334eb4ea085SAngus Ainslie (Purism)			};
335eb4ea085SAngus Ainslie (Purism)
336eb4ea085SAngus Ainslie (Purism)			buck8_reg: BUCK8 {
337eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck8";
338eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <800000>;
339eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1400000>;
340eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
341eb4ea085SAngus Ainslie (Purism)			};
342eb4ea085SAngus Ainslie (Purism)
343eb4ea085SAngus Ainslie (Purism)			ldo1_reg: LDO1 {
344eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo1";
345eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
346eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
347eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
348eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
349eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
350eb4ea085SAngus Ainslie (Purism)			};
351eb4ea085SAngus Ainslie (Purism)
352eb4ea085SAngus Ainslie (Purism)			ldo2_reg: LDO2 {
353eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo2";
354eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
355eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <900000>;
356eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
357eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
358eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
359eb4ea085SAngus Ainslie (Purism)			};
360eb4ea085SAngus Ainslie (Purism)
361eb4ea085SAngus Ainslie (Purism)			ldo3_reg: LDO3 {
362eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo3";
363eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
364eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
365eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
366eb4ea085SAngus Ainslie (Purism)			};
367eb4ea085SAngus Ainslie (Purism)
368eb4ea085SAngus Ainslie (Purism)			ldo4_reg: LDO4 {
369eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo4";
370eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
371eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
372eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
373eb4ea085SAngus Ainslie (Purism)			};
374eb4ea085SAngus Ainslie (Purism)
375eb4ea085SAngus Ainslie (Purism)			ldo5_reg: LDO5 {
376eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo5";
377eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
378eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
379eb4ea085SAngus Ainslie (Purism)			};
380eb4ea085SAngus Ainslie (Purism)
381eb4ea085SAngus Ainslie (Purism)			ldo6_reg: LDO6 {
382eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo6";
383eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
384eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
385eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
386eb4ea085SAngus Ainslie (Purism)			};
387eb4ea085SAngus Ainslie (Purism)
388eb4ea085SAngus Ainslie (Purism)			ldo7_reg: LDO7 {
389eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo7";
390eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
391eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
392eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
393eb4ea085SAngus Ainslie (Purism)			};
394eb4ea085SAngus Ainslie (Purism)		};
395eb4ea085SAngus Ainslie (Purism)	};
396eb4ea085SAngus Ainslie (Purism)
397eb4ea085SAngus Ainslie (Purism)	typec_ptn5100: usb_typec@52 {
398eb4ea085SAngus Ainslie (Purism)		compatible = "nxp,ptn5110";
399eb4ea085SAngus Ainslie (Purism)		reg = <0x52>;
400eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
401eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_typec>;
402eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
403eb4ea085SAngus Ainslie (Purism)		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
404eb4ea085SAngus Ainslie (Purism)
405eb4ea085SAngus Ainslie (Purism)		connector {
406eb4ea085SAngus Ainslie (Purism)			compatible = "usb-c-connector";
407eb4ea085SAngus Ainslie (Purism)			label = "USB-C";
408eb4ea085SAngus Ainslie (Purism)			data-role = "dual";
409eb4ea085SAngus Ainslie (Purism)			power-role = "dual";
410eb4ea085SAngus Ainslie (Purism)			try-power-role = "sink";
411eb4ea085SAngus Ainslie (Purism)			source-pdos = <PDO_FIXED(5000, 2000,
412eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_USB_COMM |
413eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
414eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )>;
415eb4ea085SAngus Ainslie (Purism)			sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM |
416eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
417eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )
4188155b786SAngus Ainslie (Purism)			     PDO_VAR(5000, 3000, 3000)>;
419eb4ea085SAngus Ainslie (Purism)			op-sink-microwatt = <10000000>;
420eb4ea085SAngus Ainslie (Purism)
421eb4ea085SAngus Ainslie (Purism)			ports {
422eb4ea085SAngus Ainslie (Purism)				#address-cells = <1>;
423eb4ea085SAngus Ainslie (Purism)				#size-cells = <0>;
424eb4ea085SAngus Ainslie (Purism)
425eb4ea085SAngus Ainslie (Purism)				port@0 {
426eb4ea085SAngus Ainslie (Purism)					reg = <0>;
427eb4ea085SAngus Ainslie (Purism)
428eb4ea085SAngus Ainslie (Purism)					usb_con_hs: endpoint {
429eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_hs>;
430eb4ea085SAngus Ainslie (Purism)					};
431eb4ea085SAngus Ainslie (Purism)				};
432eb4ea085SAngus Ainslie (Purism)
433eb4ea085SAngus Ainslie (Purism)				port@1 {
434eb4ea085SAngus Ainslie (Purism)					reg = <1>;
435eb4ea085SAngus Ainslie (Purism)
436eb4ea085SAngus Ainslie (Purism)					usb_con_ss: endpoint {
437eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_ss>;
438eb4ea085SAngus Ainslie (Purism)					};
439eb4ea085SAngus Ainslie (Purism)				};
440eb4ea085SAngus Ainslie (Purism)			};
441eb4ea085SAngus Ainslie (Purism)		};
442eb4ea085SAngus Ainslie (Purism)	};
443eb4ea085SAngus Ainslie (Purism)
444eb4ea085SAngus Ainslie (Purism)	rtc@68 {
445eb4ea085SAngus Ainslie (Purism)		compatible = "microcrystal,rv4162";
446eb4ea085SAngus Ainslie (Purism)		reg = <0x68>;
447eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
448eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_rtc>;
449eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio4>;
450eb4ea085SAngus Ainslie (Purism)		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
451eb4ea085SAngus Ainslie (Purism)	};
452eb4ea085SAngus Ainslie (Purism)
453eb4ea085SAngus Ainslie (Purism)	charger@6b { /* bq25896 */
454eb4ea085SAngus Ainslie (Purism)		compatible = "ti,bq25890";
455eb4ea085SAngus Ainslie (Purism)		reg = <0x6b>;
456eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
457eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_charger>;
458eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
459eb4ea085SAngus Ainslie (Purism)		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
460eb4ea085SAngus Ainslie (Purism)		ti,battery-regulation-voltage = <4192000>; /* 4.192V */
461eb4ea085SAngus Ainslie (Purism)		ti,charge-current = <1600000>; /* 1.6A */
462eb4ea085SAngus Ainslie (Purism)		ti,termination-current = <66000>;  /* 66mA */
463eb4ea085SAngus Ainslie (Purism)		ti,precharge-current = <130000>; /* 130mA */
464eb4ea085SAngus Ainslie (Purism)		ti,minimum-sys-voltage = <3000000>; /* 3V */
465eb4ea085SAngus Ainslie (Purism)		ti,boost-voltage = <5000000>; /* 5V */
466eb4ea085SAngus Ainslie (Purism)		ti,boost-max-current = <50000>; /* 50mA */
467eb4ea085SAngus Ainslie (Purism)	};
468eb4ea085SAngus Ainslie (Purism)};
469eb4ea085SAngus Ainslie (Purism)
470eb4ea085SAngus Ainslie (Purism)&i2c3 {
471eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
472eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
473eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c3>;
474eb4ea085SAngus Ainslie (Purism)	status = "okay";
475eb4ea085SAngus Ainslie (Purism)
476eb4ea085SAngus Ainslie (Purism)	magnetometer@1e	{
477eb4ea085SAngus Ainslie (Purism)		compatible = "st,lsm9ds1-magn";
478eb4ea085SAngus Ainslie (Purism)		reg = <0x1e>;
479eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
480eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_imu>;
481eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
482106f7b3bSAngus Ainslie (Purism)		interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
483eb4ea085SAngus Ainslie (Purism)		vdd-supply = <&reg_3v3_p>;
484eb4ea085SAngus Ainslie (Purism)		vddio-supply = <&reg_3v3_p>;
485eb4ea085SAngus Ainslie (Purism)	};
486eb4ea085SAngus Ainslie (Purism)
487c53f0166SAngus Ainslie (Purism)	sgtl5000: audio-codec@a {
488c53f0166SAngus Ainslie (Purism)		compatible = "fsl,sgtl5000";
489c53f0166SAngus Ainslie (Purism)		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
490c53f0166SAngus Ainslie (Purism)		assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
491c53f0166SAngus Ainslie (Purism)		assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
492c53f0166SAngus Ainslie (Purism)		assigned-clock-rates = <24576000>;
493c53f0166SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
494c53f0166SAngus Ainslie (Purism)		reg = <0x0a>;
495c53f0166SAngus Ainslie (Purism)		VDDD-supply = <&reg_1v8_p>;
496c53f0166SAngus Ainslie (Purism)		VDDIO-supply = <&reg_3v3_p>;
497c53f0166SAngus Ainslie (Purism)		VDDA-supply = <&reg_3v3_p>;
498c53f0166SAngus Ainslie (Purism)	};
499c53f0166SAngus Ainslie (Purism)
500eb4ea085SAngus Ainslie (Purism)	touchscreen@5d {
501eb4ea085SAngus Ainslie (Purism)		compatible = "goodix,gt5688";
502eb4ea085SAngus Ainslie (Purism)		reg = <0x5d>;
503eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
504eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_ts>;
505eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
506eb4ea085SAngus Ainslie (Purism)		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
507eb4ea085SAngus Ainslie (Purism)		reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
508eb4ea085SAngus Ainslie (Purism)		irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
509eb4ea085SAngus Ainslie (Purism)		touchscreen-size-x = <720>;
510eb4ea085SAngus Ainslie (Purism)		touchscreen-size-y = <1440>;
511eb4ea085SAngus Ainslie (Purism)		AVDD28-supply = <&reg_2v8_p>;
512eb4ea085SAngus Ainslie (Purism)		VDDIO-supply = <&reg_1v8_p>;
513eb4ea085SAngus Ainslie (Purism)	};
514537c00e3SMartin Kepplinger
515ea38ca9aSGuido Günther	proximity-sensor@60 {
516ea38ca9aSGuido Günther		compatible = "vishay,vcnl4040";
517ea38ca9aSGuido Günther		reg = <0x60>;
518ea38ca9aSGuido Günther		pinctrl-0 = <&pinctrl_prox>;
519ea38ca9aSGuido Günther	};
520ea38ca9aSGuido Günther
521537c00e3SMartin Kepplinger	accel-gyro@6a {
522537c00e3SMartin Kepplinger		compatible = "st,lsm9ds1-imu";
523537c00e3SMartin Kepplinger		reg = <0x6a>;
524537c00e3SMartin Kepplinger		vdd-supply = <&reg_3v3_p>;
525537c00e3SMartin Kepplinger		vddio-supply = <&reg_3v3_p>;
526537c00e3SMartin Kepplinger	};
527eb4ea085SAngus Ainslie (Purism)};
528eb4ea085SAngus Ainslie (Purism)
529eb4ea085SAngus Ainslie (Purism)&iomuxc {
530eb4ea085SAngus Ainslie (Purism)	pinctrl_bl: blgrp {
531eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
532eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT	0x6 /* DSI_BL_PWM */
533eb4ea085SAngus Ainslie (Purism)		>;
534eb4ea085SAngus Ainslie (Purism)	};
535eb4ea085SAngus Ainslie (Purism)
536eb4ea085SAngus Ainslie (Purism)	pinctrl_bt: btgrp {
537eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
538eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11	0x16 /* nBT_DISABLE */
539eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7	0x10 /* BT_HOST_WAKE */
540eb4ea085SAngus Ainslie (Purism)		>;
541eb4ea085SAngus Ainslie (Purism)	};
542eb4ea085SAngus Ainslie (Purism)
543eb4ea085SAngus Ainslie (Purism)	pinctrl_charger: chargergrp {
544eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
545eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x80 /* CHRG_nINT */
546eb4ea085SAngus Ainslie (Purism)		>;
547eb4ea085SAngus Ainslie (Purism)	};
548eb4ea085SAngus Ainslie (Purism)
549eb4ea085SAngus Ainslie (Purism)	pinctrl_fec1: fec1grp {
550eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
551eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
552eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
553eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
554eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
555eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
556eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
557eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
558eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
559eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
560eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
561eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
562eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
563eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
564eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
565eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
566eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x1f
567eb4ea085SAngus Ainslie (Purism)		>;
568eb4ea085SAngus Ainslie (Purism)	};
569eb4ea085SAngus Ainslie (Purism)
570eb4ea085SAngus Ainslie (Purism)	pinctrl_ts: tsgrp {
571eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
572eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0		0x16  /* TOUCH INT */
573eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19  /* TOUCH RST */
574eb4ea085SAngus Ainslie (Purism)		>;
575eb4ea085SAngus Ainslie (Purism)	};
576eb4ea085SAngus Ainslie (Purism)
577eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_leds: gpioledgrp {
578eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
579eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16
580eb4ea085SAngus Ainslie (Purism)		>;
581eb4ea085SAngus Ainslie (Purism)	};
582eb4ea085SAngus Ainslie (Purism)
583eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_keys: gpiokeygrp {
584eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
585eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x16
586eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22	0x16
587eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x180  /* HP_DET */
5883ef506b3SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80   /* nWoWWAN */
589eb4ea085SAngus Ainslie (Purism)		>;
590eb4ea085SAngus Ainslie (Purism)	};
591eb4ea085SAngus Ainslie (Purism)
592eb4ea085SAngus Ainslie (Purism)	pinctrl_haptic: hapticgrp {
593eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
594eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4		0xc6   /* nHAPTIC */
595eb4ea085SAngus Ainslie (Purism)		>;
596eb4ea085SAngus Ainslie (Purism)	};
597eb4ea085SAngus Ainslie (Purism)
598eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c1: i2c1grp {
599eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
600eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000001f
601eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000001f
602eb4ea085SAngus Ainslie (Purism)		>;
603eb4ea085SAngus Ainslie (Purism)	};
604eb4ea085SAngus Ainslie (Purism)
605eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c3: i2c3grp {
606eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
607eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x4000001f
608eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x4000001f
609eb4ea085SAngus Ainslie (Purism)		>;
610eb4ea085SAngus Ainslie (Purism)	};
611eb4ea085SAngus Ainslie (Purism)
612eb4ea085SAngus Ainslie (Purism)	pinctrl_imu: imugrp {
613eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
614eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x8  /* IMU_INT */
615eb4ea085SAngus Ainslie (Purism)		>;
616eb4ea085SAngus Ainslie (Purism)	};
617eb4ea085SAngus Ainslie (Purism)
618eb4ea085SAngus Ainslie (Purism)	pinctrl_pmic: pmicgrp {
619eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
620eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x80  /* PMIC intr */
621eb4ea085SAngus Ainslie (Purism)		>;
622eb4ea085SAngus Ainslie (Purism)	};
623eb4ea085SAngus Ainslie (Purism)
624ea38ca9aSGuido Günther	pinctrl_prox: proxgrp {
625ea38ca9aSGuido Günther		fsl,pins = <
626ea38ca9aSGuido Günther			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x80  /* prox intr */
627ea38ca9aSGuido Günther		>;
628ea38ca9aSGuido Günther	};
629ea38ca9aSGuido Günther
630eb4ea085SAngus Ainslie (Purism)	pinctrl_pwr_en: pwrengrp {
631eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
632eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x06
633eb4ea085SAngus Ainslie (Purism)		>;
634eb4ea085SAngus Ainslie (Purism)	};
635eb4ea085SAngus Ainslie (Purism)
636eb4ea085SAngus Ainslie (Purism)	pinctrl_rtc: rtcgrp {
637eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
638eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29	0x80  /* RTC intr */
639eb4ea085SAngus Ainslie (Purism)		>;
640eb4ea085SAngus Ainslie (Purism)	};
641eb4ea085SAngus Ainslie (Purism)
642c53f0166SAngus Ainslie (Purism)	pinctrl_sai2: sai2grp {
643c53f0166SAngus Ainslie (Purism)		fsl,pins = <
644c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
645c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
646c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
647c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6
648c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
649c53f0166SAngus Ainslie (Purism)		>;
650c53f0166SAngus Ainslie (Purism)	};
651c53f0166SAngus Ainslie (Purism)
6527f7b7997SAngus Ainslie (Purism)	pinctrl_sai6: sai6grp {
6537f7b7997SAngus Ainslie (Purism)		fsl,pins = <
6547f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0	0xd6
6557f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC	0xd6
6567f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK     0xd6
6577f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0	0xd6
6587f7b7997SAngus Ainslie (Purism)		>;
6597f7b7997SAngus Ainslie (Purism)	};
6607f7b7997SAngus Ainslie (Purism)
661eb4ea085SAngus Ainslie (Purism)	pinctrl_typec: typecgrp {
662eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
663eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x16
664eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x80
665eb4ea085SAngus Ainslie (Purism)		>;
666eb4ea085SAngus Ainslie (Purism)	};
667eb4ea085SAngus Ainslie (Purism)
668eb4ea085SAngus Ainslie (Purism)	pinctrl_uart1: uart1grp {
669eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
670eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
671eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
672eb4ea085SAngus Ainslie (Purism)		>;
673eb4ea085SAngus Ainslie (Purism)	};
674eb4ea085SAngus Ainslie (Purism)
675eb4ea085SAngus Ainslie (Purism)	pinctrl_uart2: uart2grp {
676eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
677eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
678eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
679eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
680eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
681eb4ea085SAngus Ainslie (Purism)		>;
682eb4ea085SAngus Ainslie (Purism)	};
683eb4ea085SAngus Ainslie (Purism)
684eb4ea085SAngus Ainslie (Purism)	pinctrl_uart3: uart3grp {
685eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
686eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
687eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
688eb4ea085SAngus Ainslie (Purism)		>;
689eb4ea085SAngus Ainslie (Purism)	};
690eb4ea085SAngus Ainslie (Purism)
691eb4ea085SAngus Ainslie (Purism)	pinctrl_uart4: uart4grp {
692eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
693eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
694eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
695eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x49
696eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49
697eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x49
698eb4ea085SAngus Ainslie (Purism)		>;
699eb4ea085SAngus Ainslie (Purism)	};
700eb4ea085SAngus Ainslie (Purism)
701eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1: usdhc1grp {
702eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
703eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
704eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
705eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
706eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
707eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
708eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
709eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
710eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
711eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
712eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
713eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
714eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
715eb4ea085SAngus Ainslie (Purism)		>;
716eb4ea085SAngus Ainslie (Purism)	};
717eb4ea085SAngus Ainslie (Purism)
718eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
719eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
720eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
721eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
722eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
723eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
724eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
725eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
726eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
727eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
728eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
729eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
730eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
731eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
732eb4ea085SAngus Ainslie (Purism)		>;
733eb4ea085SAngus Ainslie (Purism)	};
734eb4ea085SAngus Ainslie (Purism)
735eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
736eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
737eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
738eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
739eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
740eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
741eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
742eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
743eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
744eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
745eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
746eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
747eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
748eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
749eb4ea085SAngus Ainslie (Purism)		>;
750eb4ea085SAngus Ainslie (Purism)	};
751eb4ea085SAngus Ainslie (Purism)
752eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_pwr: usdhc2grppwr {
753eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
754eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
755eb4ea085SAngus Ainslie (Purism)		>;
756eb4ea085SAngus Ainslie (Purism)	};
757eb4ea085SAngus Ainslie (Purism)
758eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_gpio: usdhc2grpgpio {
759eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
760eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */
761eb4ea085SAngus Ainslie (Purism)		>;
762eb4ea085SAngus Ainslie (Purism)	};
763eb4ea085SAngus Ainslie (Purism)
764eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2: usdhc2grp {
765eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
766eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
767eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
768eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
769eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
770eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
771eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
772eb4ea085SAngus Ainslie (Purism)		>;
773eb4ea085SAngus Ainslie (Purism)	};
774eb4ea085SAngus Ainslie (Purism)
775eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
776eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
777eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d
778eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd
779eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcd
780eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcd
781eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcd
782eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcd
783eb4ea085SAngus Ainslie (Purism)		>;
784eb4ea085SAngus Ainslie (Purism)	};
785eb4ea085SAngus Ainslie (Purism)
786eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
787eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
788eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f
789eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf
790eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcf
791eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcf
792eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcf
793eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcf
794eb4ea085SAngus Ainslie (Purism)		>;
795eb4ea085SAngus Ainslie (Purism)	};
796eb4ea085SAngus Ainslie (Purism)
797eb4ea085SAngus Ainslie (Purism)	pinctrl_wdog: wdoggrp {
798eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
799eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
800eb4ea085SAngus Ainslie (Purism)		>;
801eb4ea085SAngus Ainslie (Purism)	};
802eb4ea085SAngus Ainslie (Purism)
803eb4ea085SAngus Ainslie (Purism)	pinctrl_wifi_pwr_en: wifipwrengrp {
804eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
805eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5         0x06
806eb4ea085SAngus Ainslie (Purism)		>;
807eb4ea085SAngus Ainslie (Purism)	};
808eb4ea085SAngus Ainslie (Purism)
809eb4ea085SAngus Ainslie (Purism)	pinctrl_wwan: wwangrp {
810eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
811eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x09 /* nWWAN_DISABLE */
812eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80 /* nWoWWAN */
813eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9	0x19 /* WWAN_RESET */
814eb4ea085SAngus Ainslie (Purism)		>;
815eb4ea085SAngus Ainslie (Purism)	};
816eb4ea085SAngus Ainslie (Purism)};
817eb4ea085SAngus Ainslie (Purism)
818eb4ea085SAngus Ainslie (Purism)&pgc_gpu {
819eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck3_reg>;
820eb4ea085SAngus Ainslie (Purism)};
821eb4ea085SAngus Ainslie (Purism)
822eb4ea085SAngus Ainslie (Purism)&pgc_vpu {
823eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck4_reg>;
824eb4ea085SAngus Ainslie (Purism)};
825eb4ea085SAngus Ainslie (Purism)
826eb4ea085SAngus Ainslie (Purism)&pwm1 {
827eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
828eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_bl>;
829eb4ea085SAngus Ainslie (Purism)	status = "okay";
830eb4ea085SAngus Ainslie (Purism)};
831eb4ea085SAngus Ainslie (Purism)
83201407158SAngus Ainslie (Purism)&snvs_pwrkey {
83301407158SAngus Ainslie (Purism)	status = "okay";
83401407158SAngus Ainslie (Purism)};
835eb4ea085SAngus Ainslie (Purism)
836c53f0166SAngus Ainslie (Purism)&sai2 {
837c53f0166SAngus Ainslie (Purism)	pinctrl-names = "default";
838c53f0166SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai2>;
839c53f0166SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
840c53f0166SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
841c53f0166SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
842c53f0166SAngus Ainslie (Purism)	status = "okay";
843c53f0166SAngus Ainslie (Purism)};
844c53f0166SAngus Ainslie (Purism)
8457f7b7997SAngus Ainslie (Purism)&sai6 {
8467f7b7997SAngus Ainslie (Purism)	pinctrl-names = "default";
8477f7b7997SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai6>;
8487f7b7997SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI6>;
8497f7b7997SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
8507f7b7997SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
8517f7b7997SAngus Ainslie (Purism)	fsl,sai-synchronous-rx;
8527f7b7997SAngus Ainslie (Purism)	status = "okay";
8537f7b7997SAngus Ainslie (Purism)};
8547f7b7997SAngus Ainslie (Purism)
855eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */
856eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
857eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart1>;
858eb4ea085SAngus Ainslie (Purism)	status = "okay";
859eb4ea085SAngus Ainslie (Purism)};
860eb4ea085SAngus Ainslie (Purism)
861eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */
862eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
863eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart3>;
864eb4ea085SAngus Ainslie (Purism)	status = "okay";
865eb4ea085SAngus Ainslie (Purism)};
866eb4ea085SAngus Ainslie (Purism)
867eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */
868eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
869eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
870eb4ea085SAngus Ainslie (Purism)	uart-has-rtscts;
871eb4ea085SAngus Ainslie (Purism)	status = "okay";
872eb4ea085SAngus Ainslie (Purism)};
873eb4ea085SAngus Ainslie (Purism)
874eb4ea085SAngus Ainslie (Purism)&usb3_phy0 {
875dde061b8SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
876eb4ea085SAngus Ainslie (Purism)	status = "okay";
877eb4ea085SAngus Ainslie (Purism)};
878eb4ea085SAngus Ainslie (Purism)
879eb4ea085SAngus Ainslie (Purism)&usb3_phy1 {
880eb4ea085SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
881eb4ea085SAngus Ainslie (Purism)	status = "okay";
882eb4ea085SAngus Ainslie (Purism)};
883eb4ea085SAngus Ainslie (Purism)
884eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 {
885eb4ea085SAngus Ainslie (Purism)	#address-cells = <1>;
886eb4ea085SAngus Ainslie (Purism)	#size-cells = <0>;
887eb4ea085SAngus Ainslie (Purism)	dr_mode = "otg";
888eb4ea085SAngus Ainslie (Purism)	status = "okay";
889eb4ea085SAngus Ainslie (Purism)
890eb4ea085SAngus Ainslie (Purism)	port@0 {
891eb4ea085SAngus Ainslie (Purism)		reg = <0>;
892eb4ea085SAngus Ainslie (Purism)
893eb4ea085SAngus Ainslie (Purism)		typec_hs: endpoint {
894eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_hs>;
895eb4ea085SAngus Ainslie (Purism)		};
896eb4ea085SAngus Ainslie (Purism)	};
897eb4ea085SAngus Ainslie (Purism)
898eb4ea085SAngus Ainslie (Purism)	port@1 {
899eb4ea085SAngus Ainslie (Purism)		reg = <1>;
900eb4ea085SAngus Ainslie (Purism)
901eb4ea085SAngus Ainslie (Purism)		typec_ss: endpoint {
902eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_ss>;
903eb4ea085SAngus Ainslie (Purism)		};
904eb4ea085SAngus Ainslie (Purism)	};
905eb4ea085SAngus Ainslie (Purism)};
906eb4ea085SAngus Ainslie (Purism)
907eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 {
908eb4ea085SAngus Ainslie (Purism)	dr_mode = "host";
909eb4ea085SAngus Ainslie (Purism)	status = "okay";
910eb4ea085SAngus Ainslie (Purism)};
911eb4ea085SAngus Ainslie (Purism)
912eb4ea085SAngus Ainslie (Purism)&usdhc1 {
913e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
914e045f044SAnson Huang	assigned-clock-rates = <400000000>;
915eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
916eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc1>;
917eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
918eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
919eb4ea085SAngus Ainslie (Purism)	bus-width = <8>;
920eb4ea085SAngus Ainslie (Purism)	non-removable;
921eb4ea085SAngus Ainslie (Purism)	status = "okay";
922eb4ea085SAngus Ainslie (Purism)};
923eb4ea085SAngus Ainslie (Purism)
924eb4ea085SAngus Ainslie (Purism)&usdhc2 {
925e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
926e045f044SAnson Huang	assigned-clock-rates = <200000000>;
927eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
928eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc2>;
929eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
930eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
931eb4ea085SAngus Ainslie (Purism)	bus-width = <4>;
932eb4ea085SAngus Ainslie (Purism)	vmmc-supply = <&reg_usdhc2_vmmc>;
933eb4ea085SAngus Ainslie (Purism)	power-supply = <&wifi_pwr_en>;
934eb4ea085SAngus Ainslie (Purism)	non-removable;
935eb4ea085SAngus Ainslie (Purism)	disable-wp;
936eb4ea085SAngus Ainslie (Purism)	cap-sdio-irq;
937eb4ea085SAngus Ainslie (Purism)	keep-power-in-suspend;
938eb4ea085SAngus Ainslie (Purism)	wakeup-source;
939eb4ea085SAngus Ainslie (Purism)	status = "okay";
940eb4ea085SAngus Ainslie (Purism)};
941eb4ea085SAngus Ainslie (Purism)
942eb4ea085SAngus Ainslie (Purism)&wdog1 {
943eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
944eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_wdog>;
945eb4ea085SAngus Ainslie (Purism)	fsl,ext-reset-output;
946eb4ea085SAngus Ainslie (Purism)	status = "okay";
947eb4ea085SAngus Ainslie (Purism)};
948