1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+
2eb4ea085SAngus Ainslie (Purism)/*
3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC
4eb4ea085SAngus Ainslie (Purism) */
5eb4ea085SAngus Ainslie (Purism)
6eb4ea085SAngus Ainslie (Purism)/dts-v1/;
7eb4ea085SAngus Ainslie (Purism)
8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h"
9d8fa4792SKrzysztof Kozlowski#include <dt-bindings/interrupt-controller/irq.h>
10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h"
11eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h"
12eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi"
13eb4ea085SAngus Ainslie (Purism)
14eb4ea085SAngus Ainslie (Purism)/ {
15eb4ea085SAngus Ainslie (Purism)	model = "Purism Librem 5 devkit";
16eb4ea085SAngus Ainslie (Purism)	compatible = "purism,librem5-devkit", "fsl,imx8mq";
17eb4ea085SAngus Ainslie (Purism)
18eb4ea085SAngus Ainslie (Purism)	backlight_dsi: backlight-dsi {
19eb4ea085SAngus Ainslie (Purism)		compatible = "pwm-backlight";
20eb4ea085SAngus Ainslie (Purism)		/* 200 Hz for the PAM2841 */
21eb4ea085SAngus Ainslie (Purism)		pwms = <&pwm1 0 5000000>;
22eb4ea085SAngus Ainslie (Purism)		brightness-levels = <0 100>;
23eb4ea085SAngus Ainslie (Purism)		num-interpolated-steps = <100>;
24eb4ea085SAngus Ainslie (Purism)		/* Default brightness level (index into the array defined by */
25eb4ea085SAngus Ainslie (Purism)		/* the "brightness-levels" property) */
26eb4ea085SAngus Ainslie (Purism)		default-brightness-level = <0>;
27eb4ea085SAngus Ainslie (Purism)		power-supply = <&reg_22v4_p>;
28eb4ea085SAngus Ainslie (Purism)	};
29eb4ea085SAngus Ainslie (Purism)
30eb4ea085SAngus Ainslie (Purism)	chosen {
31eb4ea085SAngus Ainslie (Purism)		stdout-path = &uart1;
32eb4ea085SAngus Ainslie (Purism)	};
33eb4ea085SAngus Ainslie (Purism)
34eb4ea085SAngus Ainslie (Purism)	gpio-keys {
35eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-keys";
36eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
37eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_keys>;
38eb4ea085SAngus Ainslie (Purism)
39eb4ea085SAngus Ainslie (Purism)		btn1 {
40eb4ea085SAngus Ainslie (Purism)			label = "VOL_UP";
41eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
42eb4ea085SAngus Ainslie (Purism)			wakeup-source;
43eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEUP>;
44eb4ea085SAngus Ainslie (Purism)		};
45eb4ea085SAngus Ainslie (Purism)
46eb4ea085SAngus Ainslie (Purism)		btn2 {
47eb4ea085SAngus Ainslie (Purism)			label = "VOL_DOWN";
48eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
49eb4ea085SAngus Ainslie (Purism)			wakeup-source;
50eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEDOWN>;
51eb4ea085SAngus Ainslie (Purism)		};
52eb4ea085SAngus Ainslie (Purism)
53eb4ea085SAngus Ainslie (Purism)		hp-det {
54eb4ea085SAngus Ainslie (Purism)			label = "HP_DET";
55eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
56eb4ea085SAngus Ainslie (Purism)			wakeup-source;
57eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_HP>;
58eb4ea085SAngus Ainslie (Purism)		};
593ef506b3SAngus Ainslie (Purism)
603ef506b3SAngus Ainslie (Purism)		wwan-wake {
613ef506b3SAngus Ainslie (Purism)			label = "WWAN_WAKE";
623ef506b3SAngus Ainslie (Purism)			gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
633ef506b3SAngus Ainslie (Purism)			interrupt-parent = <&gpio3>;
64d8fa4792SKrzysztof Kozlowski			interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
653ef506b3SAngus Ainslie (Purism)			wakeup-source;
663ef506b3SAngus Ainslie (Purism)			linux,code = <KEY_PHONE>;
673ef506b3SAngus Ainslie (Purism)		};
68eb4ea085SAngus Ainslie (Purism)	};
69eb4ea085SAngus Ainslie (Purism)
70eb4ea085SAngus Ainslie (Purism)	leds {
71eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-leds";
72eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
73eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_leds>;
74eb4ea085SAngus Ainslie (Purism)
75eb4ea085SAngus Ainslie (Purism)		led1 {
76eb4ea085SAngus Ainslie (Purism)			label = "LED 1";
77eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
78eb4ea085SAngus Ainslie (Purism)			default-state = "off";
79eb4ea085SAngus Ainslie (Purism)		};
80eb4ea085SAngus Ainslie (Purism)	};
81eb4ea085SAngus Ainslie (Purism)
82eb4ea085SAngus Ainslie (Purism)	pmic_osc: clock-pmic {
83eb4ea085SAngus Ainslie (Purism)		compatible = "fixed-clock";
84eb4ea085SAngus Ainslie (Purism)		#clock-cells = <0>;
85eb4ea085SAngus Ainslie (Purism)		clock-frequency = <32768>;
86eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_osc";
87eb4ea085SAngus Ainslie (Purism)	};
88eb4ea085SAngus Ainslie (Purism)
89eb4ea085SAngus Ainslie (Purism)	reg_1v8_p: regulator-1v8-p {
90eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
91eb4ea085SAngus Ainslie (Purism)		regulator-name = "1v8_p";
92eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <1800000>;
93eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <1800000>;
94eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
95eb4ea085SAngus Ainslie (Purism)	};
96eb4ea085SAngus Ainslie (Purism)
97eb4ea085SAngus Ainslie (Purism)	reg_2v8_p: regulator-2v8-p {
98eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
99eb4ea085SAngus Ainslie (Purism)		regulator-name = "2v8_p";
100eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <2800000>;
101eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <2800000>;
102eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
103eb4ea085SAngus Ainslie (Purism)	};
104eb4ea085SAngus Ainslie (Purism)
105eb4ea085SAngus Ainslie (Purism)	reg_3v3_p: regulator-3v3-p {
106eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
107eb4ea085SAngus Ainslie (Purism)		regulator-name = "3v3_p";
108eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
109eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
110eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
111eb4ea085SAngus Ainslie (Purism)
112eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
113eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
114eb4ea085SAngus Ainslie (Purism)		};
115eb4ea085SAngus Ainslie (Purism)	};
116eb4ea085SAngus Ainslie (Purism)
117eb4ea085SAngus Ainslie (Purism)	reg_5v_p: regulator-5v-p {
118eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
119eb4ea085SAngus Ainslie (Purism)		regulator-name = "5v_p";
120eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <5000000>;
121eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <5000000>;
122eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
123eb4ea085SAngus Ainslie (Purism)
124eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
125eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
126eb4ea085SAngus Ainslie (Purism)		};
127eb4ea085SAngus Ainslie (Purism)	};
128eb4ea085SAngus Ainslie (Purism)
129eb4ea085SAngus Ainslie (Purism)	reg_22v4_p: regulator-22v4-p  {
130eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
131eb4ea085SAngus Ainslie (Purism)		regulator-name = "22v4_P";
132eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <22400000>;
133eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <22400000>;
134eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
135eb4ea085SAngus Ainslie (Purism)	};
136eb4ea085SAngus Ainslie (Purism)
137eb4ea085SAngus Ainslie (Purism)	reg_pwr_en: regulator-pwr-en {
138eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
139eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
140eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pwr_en>;
141eb4ea085SAngus Ainslie (Purism)		regulator-name = "PWR_EN";
142eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
143eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
144eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
145eb4ea085SAngus Ainslie (Purism)		enable-active-high;
146eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
147eb4ea085SAngus Ainslie (Purism)	};
148eb4ea085SAngus Ainslie (Purism)
149eb4ea085SAngus Ainslie (Purism)	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
150eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
151eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
152eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_usdhc2_pwr>;
153eb4ea085SAngus Ainslie (Purism)		regulator-name = "VSD_3V3";
154eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
155eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
156eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
157eb4ea085SAngus Ainslie (Purism)		enable-active-high;
158eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
159eb4ea085SAngus Ainslie (Purism)	};
160eb4ea085SAngus Ainslie (Purism)
1617f7b7997SAngus Ainslie (Purism)	wwan_codec: sound-wwan-codec {
1627f7b7997SAngus Ainslie (Purism)		compatible = "option,gtm601";
1637f7b7997SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
1647f7b7997SAngus Ainslie (Purism)	};
1657f7b7997SAngus Ainslie (Purism)
166c53f0166SAngus Ainslie (Purism)	sound {
167c53f0166SAngus Ainslie (Purism)		compatible = "simple-audio-card";
1686f46f7ffSGuido Günther		simple-audio-card,aux-devs = <&speaker_amp>;
1695b65f39dSGuido Günther		simple-audio-card,name = "Librem 5 Devkit";
170c53f0166SAngus Ainslie (Purism)		simple-audio-card,format = "i2s";
171c53f0166SAngus Ainslie (Purism)		simple-audio-card,widgets =
172c53f0166SAngus Ainslie (Purism)			"Microphone", "Microphone Jack",
173c53f0166SAngus Ainslie (Purism)			"Headphone", "Headphone Jack",
174*39a346d9SGuido Günther			"Speaker", "Builtin Speaker";
175c53f0166SAngus Ainslie (Purism)		simple-audio-card,routing =
176c53f0166SAngus Ainslie (Purism)			"MIC_IN", "Microphone Jack",
177c53f0166SAngus Ainslie (Purism)			"Microphone Jack", "Mic Bias",
178c53f0166SAngus Ainslie (Purism)			"Headphone Jack", "HP_OUT",
1796f46f7ffSGuido Günther			"Builtin Speaker", "Speaker Amp OUTR",
1806f46f7ffSGuido Günther			"Speaker Amp INR", "LINE_OUT";
181c53f0166SAngus Ainslie (Purism)
182c53f0166SAngus Ainslie (Purism)		simple-audio-card,cpu {
183c53f0166SAngus Ainslie (Purism)			sound-dai = <&sai2>;
184c53f0166SAngus Ainslie (Purism)		};
185c53f0166SAngus Ainslie (Purism)
186c53f0166SAngus Ainslie (Purism)		simple-audio-card,codec {
187c53f0166SAngus Ainslie (Purism)			sound-dai = <&sgtl5000>;
188c53f0166SAngus Ainslie (Purism)			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
189c53f0166SAngus Ainslie (Purism)			frame-master;
190c53f0166SAngus Ainslie (Purism)			bitclock-master;
191c53f0166SAngus Ainslie (Purism)		};
192c53f0166SAngus Ainslie (Purism)	};
193c53f0166SAngus Ainslie (Purism)
1947f7b7997SAngus Ainslie (Purism)	sound-wwan {
1957f7b7997SAngus Ainslie (Purism)		compatible = "simple-audio-card";
1967f7b7997SAngus Ainslie (Purism)		simple-audio-card,name = "SIMCom SIM7100";
1977f7b7997SAngus Ainslie (Purism)		simple-audio-card,format = "dsp_a";
1987f7b7997SAngus Ainslie (Purism)
1997f7b7997SAngus Ainslie (Purism)		simple-audio-card,cpu {
2007f7b7997SAngus Ainslie (Purism)			sound-dai = <&sai6>;
2017f7b7997SAngus Ainslie (Purism)		};
2027f7b7997SAngus Ainslie (Purism)
2037f7b7997SAngus Ainslie (Purism)		telephony_link_master: simple-audio-card,codec {
2047f7b7997SAngus Ainslie (Purism)			sound-dai = <&wwan_codec>;
2057f7b7997SAngus Ainslie (Purism)			frame-master;
2067f7b7997SAngus Ainslie (Purism)			bitclock-master;
2077f7b7997SAngus Ainslie (Purism)		};
2087f7b7997SAngus Ainslie (Purism)	};
2097f7b7997SAngus Ainslie (Purism)
2106f46f7ffSGuido Günther	speaker_amp: speaker-amp {
2116f46f7ffSGuido Günther		compatible = "simple-audio-amplifier";
2126f46f7ffSGuido Günther		pinctrl-names = "default";
2136f46f7ffSGuido Günther		pinctrl-0 = <&pinctrl_spkamp>;
2146f46f7ffSGuido Günther		VCC-supply = <&reg_3v3_p>;
2156f46f7ffSGuido Günther		sound-name-prefix = "Speaker Amp";
2166f46f7ffSGuido Günther		enable-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
2176f46f7ffSGuido Günther	};
2186f46f7ffSGuido Günther
219eb4ea085SAngus Ainslie (Purism)	vibrator {
220eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-vibrator";
221eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
222eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_haptic>;
223eb4ea085SAngus Ainslie (Purism)	        enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
224eb4ea085SAngus Ainslie (Purism)		vcc-supply = <&reg_3v3_p>;
225eb4ea085SAngus Ainslie (Purism)	};
226eb4ea085SAngus Ainslie (Purism)
227eb4ea085SAngus Ainslie (Purism)	wifi_pwr_en: regulator-wifi-en {
228eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
229eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
230eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
231eb4ea085SAngus Ainslie (Purism)		regulator-name = "WIFI_EN";
232eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
233eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
234eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
235eb4ea085SAngus Ainslie (Purism)		enable-active-high;
236eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
237eb4ea085SAngus Ainslie (Purism)	};
238eb4ea085SAngus Ainslie (Purism)};
239eb4ea085SAngus Ainslie (Purism)
240a2e47ba2SAngus Ainslie (Purism)&A53_0 {
241a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
242a2e47ba2SAngus Ainslie (Purism)};
243a2e47ba2SAngus Ainslie (Purism)
244a2e47ba2SAngus Ainslie (Purism)&A53_1 {
245a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
246a2e47ba2SAngus Ainslie (Purism)};
247a2e47ba2SAngus Ainslie (Purism)
248a2e47ba2SAngus Ainslie (Purism)&A53_2 {
249a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
250a2e47ba2SAngus Ainslie (Purism)};
251a2e47ba2SAngus Ainslie (Purism)
252a2e47ba2SAngus Ainslie (Purism)&A53_3 {
253a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
254a2e47ba2SAngus Ainslie (Purism)};
255a2e47ba2SAngus Ainslie (Purism)
2569d9005a5SGuido Günther&dphy {
2579d9005a5SGuido Günther	status = "okay";
2589d9005a5SGuido Günther};
2599d9005a5SGuido Günther
260eb4ea085SAngus Ainslie (Purism)&fec1 {
261eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
262eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_fec1>;
263eb4ea085SAngus Ainslie (Purism)	phy-mode = "rgmii-id";
264eb4ea085SAngus Ainslie (Purism)	phy-handle = <&ethphy0>;
265eb4ea085SAngus Ainslie (Purism)	fsl,magic-packet;
266eb4ea085SAngus Ainslie (Purism)	phy-supply = <&reg_3v3_p>;
267eb4ea085SAngus Ainslie (Purism)	status = "okay";
268eb4ea085SAngus Ainslie (Purism)
269eb4ea085SAngus Ainslie (Purism)	mdio {
270eb4ea085SAngus Ainslie (Purism)		#address-cells = <1>;
271eb4ea085SAngus Ainslie (Purism)		#size-cells = <0>;
272eb4ea085SAngus Ainslie (Purism)
273eb4ea085SAngus Ainslie (Purism)		ethphy0: ethernet-phy@1 {
274eb4ea085SAngus Ainslie (Purism)			compatible = "ethernet-phy-ieee802.3-c22";
275eb4ea085SAngus Ainslie (Purism)			reg = <1>;
276eb4ea085SAngus Ainslie (Purism)		};
277eb4ea085SAngus Ainslie (Purism)	};
278eb4ea085SAngus Ainslie (Purism)};
279eb4ea085SAngus Ainslie (Purism)
280eb4ea085SAngus Ainslie (Purism)&i2c1 {
281eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
282eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
283eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c1>;
284eb4ea085SAngus Ainslie (Purism)	status = "okay";
285eb4ea085SAngus Ainslie (Purism)
286eb4ea085SAngus Ainslie (Purism)	pmic: pmic@4b {
287eb4ea085SAngus Ainslie (Purism)		compatible = "rohm,bd71837";
288eb4ea085SAngus Ainslie (Purism)		reg = <0x4b>;
289eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
290eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pmic>;
291eb4ea085SAngus Ainslie (Purism)		clocks = <&pmic_osc>;
292eb4ea085SAngus Ainslie (Purism)		clock-names = "osc";
293a4a3550eSKrzysztof Kozlowski		#clock-cells = <0>;
294eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_clk";
295eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio1>;
296d8fa4792SKrzysztof Kozlowski		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
297eb4ea085SAngus Ainslie (Purism)		rohm,reset-snvs-powered;
298eb4ea085SAngus Ainslie (Purism)
299eb4ea085SAngus Ainslie (Purism)		regulators {
300eb4ea085SAngus Ainslie (Purism)			buck1_reg: BUCK1 {
301eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck1";
302eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
303eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
304eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
305edb93de4SGuido Günther				regulator-always-on;
306eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
307eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <900000>;
308eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <850000>;
309eb4ea085SAngus Ainslie (Purism)				rohm,dvs-suspend-voltage = <800000>;
310eb4ea085SAngus Ainslie (Purism)			};
311eb4ea085SAngus Ainslie (Purism)
312eb4ea085SAngus Ainslie (Purism)			buck2_reg: BUCK2 {
313eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck2";
314eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
315eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
316eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
317eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
318eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
319eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <900000>;
320eb4ea085SAngus Ainslie (Purism)			};
321eb4ea085SAngus Ainslie (Purism)
322eb4ea085SAngus Ainslie (Purism)			buck3_reg: BUCK3 {
323eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck3";
324eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
325eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
326eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
32776eceb0fSGuido Günther				rohm,dvs-run-voltage = <900000>;
328eb4ea085SAngus Ainslie (Purism)			};
329eb4ea085SAngus Ainslie (Purism)
330eb4ea085SAngus Ainslie (Purism)			buck4_reg: BUCK4 {
331eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck4";
332eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
333eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
334eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
335eb4ea085SAngus Ainslie (Purism)			};
336eb4ea085SAngus Ainslie (Purism)
337eb4ea085SAngus Ainslie (Purism)			buck5_reg: BUCK5 {
338eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck5";
339eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
340eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1350000>;
341eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
342edb93de4SGuido Günther				regulator-always-on;
343eb4ea085SAngus Ainslie (Purism)			};
344eb4ea085SAngus Ainslie (Purism)
345eb4ea085SAngus Ainslie (Purism)			buck6_reg: BUCK6 {
346eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck6";
347eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
348eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
349eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
350edb93de4SGuido Günther				regulator-always-on;
351eb4ea085SAngus Ainslie (Purism)			};
352eb4ea085SAngus Ainslie (Purism)
353eb4ea085SAngus Ainslie (Purism)			buck7_reg: BUCK7 {
354eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck7";
355eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1605000>;
356eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1995000>;
357eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
358edb93de4SGuido Günther				regulator-always-on;
359eb4ea085SAngus Ainslie (Purism)			};
360eb4ea085SAngus Ainslie (Purism)
361eb4ea085SAngus Ainslie (Purism)			buck8_reg: BUCK8 {
362eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck8";
363eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <800000>;
364eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1400000>;
365eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
366edb93de4SGuido Günther				regulator-always-on;
367eb4ea085SAngus Ainslie (Purism)			};
368eb4ea085SAngus Ainslie (Purism)
369eb4ea085SAngus Ainslie (Purism)			ldo1_reg: LDO1 {
370eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo1";
371eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
372eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
373eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
374eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
375eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
376eb4ea085SAngus Ainslie (Purism)			};
377eb4ea085SAngus Ainslie (Purism)
378eb4ea085SAngus Ainslie (Purism)			ldo2_reg: LDO2 {
379eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo2";
380eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
381eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <900000>;
382eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
383eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
384eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
385eb4ea085SAngus Ainslie (Purism)			};
386eb4ea085SAngus Ainslie (Purism)
387eb4ea085SAngus Ainslie (Purism)			ldo3_reg: LDO3 {
388eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo3";
389eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
390eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
391eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
392edb93de4SGuido Günther				regulator-always-on;
393eb4ea085SAngus Ainslie (Purism)			};
394eb4ea085SAngus Ainslie (Purism)
395eb4ea085SAngus Ainslie (Purism)			ldo4_reg: LDO4 {
396eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo4";
397eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
398eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
399eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
400edb93de4SGuido Günther				regulator-always-on;
401eb4ea085SAngus Ainslie (Purism)			};
402eb4ea085SAngus Ainslie (Purism)
403eb4ea085SAngus Ainslie (Purism)			ldo5_reg: LDO5 {
404eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo5";
405eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
406eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
407edb93de4SGuido Günther				regulator-always-on;
408eb4ea085SAngus Ainslie (Purism)			};
409eb4ea085SAngus Ainslie (Purism)
410eb4ea085SAngus Ainslie (Purism)			ldo6_reg: LDO6 {
411eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo6";
412eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
413eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
414eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
415edb93de4SGuido Günther				regulator-always-on;
416eb4ea085SAngus Ainslie (Purism)			};
417eb4ea085SAngus Ainslie (Purism)
418eb4ea085SAngus Ainslie (Purism)			ldo7_reg: LDO7 {
419eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo7";
420eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
421eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
422eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
423edb93de4SGuido Günther				regulator-always-on;
424eb4ea085SAngus Ainslie (Purism)			};
425eb4ea085SAngus Ainslie (Purism)		};
426eb4ea085SAngus Ainslie (Purism)	};
427eb4ea085SAngus Ainslie (Purism)
4289251dad3SGuido Günther	typec_ptn5100: usb-typec@52 {
429eb4ea085SAngus Ainslie (Purism)		compatible = "nxp,ptn5110";
430eb4ea085SAngus Ainslie (Purism)		reg = <0x52>;
431eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
432eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_typec>;
433eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
434eb4ea085SAngus Ainslie (Purism)		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
435eb4ea085SAngus Ainslie (Purism)
436eb4ea085SAngus Ainslie (Purism)		connector {
437eb4ea085SAngus Ainslie (Purism)			compatible = "usb-c-connector";
438eb4ea085SAngus Ainslie (Purism)			label = "USB-C";
439eb4ea085SAngus Ainslie (Purism)			data-role = "dual";
440eb4ea085SAngus Ainslie (Purism)			power-role = "dual";
441eb4ea085SAngus Ainslie (Purism)			try-power-role = "sink";
442eb4ea085SAngus Ainslie (Purism)			source-pdos = <PDO_FIXED(5000, 2000,
443eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_USB_COMM |
444eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
445eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )>;
4465369d191SAngus Ainslie (Purism)			sink-pdos = <PDO_FIXED(5000, 3500, PDO_FIXED_USB_COMM |
447eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
448eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )
4495369d191SAngus Ainslie (Purism)			     PDO_VAR(5000, 5000, 3500)>;
450eb4ea085SAngus Ainslie (Purism)			op-sink-microwatt = <10000000>;
451eb4ea085SAngus Ainslie (Purism)
452eb4ea085SAngus Ainslie (Purism)			ports {
453eb4ea085SAngus Ainslie (Purism)				#address-cells = <1>;
454eb4ea085SAngus Ainslie (Purism)				#size-cells = <0>;
455eb4ea085SAngus Ainslie (Purism)
456eb4ea085SAngus Ainslie (Purism)				port@0 {
457eb4ea085SAngus Ainslie (Purism)					reg = <0>;
458eb4ea085SAngus Ainslie (Purism)
459eb4ea085SAngus Ainslie (Purism)					usb_con_hs: endpoint {
460eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_hs>;
461eb4ea085SAngus Ainslie (Purism)					};
462eb4ea085SAngus Ainslie (Purism)				};
463eb4ea085SAngus Ainslie (Purism)
464eb4ea085SAngus Ainslie (Purism)				port@1 {
465eb4ea085SAngus Ainslie (Purism)					reg = <1>;
466eb4ea085SAngus Ainslie (Purism)
467eb4ea085SAngus Ainslie (Purism)					usb_con_ss: endpoint {
468eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_ss>;
469eb4ea085SAngus Ainslie (Purism)					};
470eb4ea085SAngus Ainslie (Purism)				};
471eb4ea085SAngus Ainslie (Purism)			};
472eb4ea085SAngus Ainslie (Purism)		};
473eb4ea085SAngus Ainslie (Purism)	};
474eb4ea085SAngus Ainslie (Purism)
475eb4ea085SAngus Ainslie (Purism)	rtc@68 {
476eb4ea085SAngus Ainslie (Purism)		compatible = "microcrystal,rv4162";
477eb4ea085SAngus Ainslie (Purism)		reg = <0x68>;
478eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
479eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_rtc>;
480eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio4>;
481eb4ea085SAngus Ainslie (Purism)		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
482eb4ea085SAngus Ainslie (Purism)	};
483eb4ea085SAngus Ainslie (Purism)
484eb4ea085SAngus Ainslie (Purism)	charger@6b { /* bq25896 */
485eb4ea085SAngus Ainslie (Purism)		compatible = "ti,bq25890";
486eb4ea085SAngus Ainslie (Purism)		reg = <0x6b>;
487eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
488eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_charger>;
489eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
490eb4ea085SAngus Ainslie (Purism)		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
491eb4ea085SAngus Ainslie (Purism)		ti,battery-regulation-voltage = <4192000>; /* 4.192V */
492eb4ea085SAngus Ainslie (Purism)		ti,charge-current = <1600000>; /* 1.6A */
493eb4ea085SAngus Ainslie (Purism)		ti,termination-current = <66000>;  /* 66mA */
494eb4ea085SAngus Ainslie (Purism)		ti,precharge-current = <130000>; /* 130mA */
495eb4ea085SAngus Ainslie (Purism)		ti,minimum-sys-voltage = <3000000>; /* 3V */
496eb4ea085SAngus Ainslie (Purism)		ti,boost-voltage = <5000000>; /* 5V */
497eb4ea085SAngus Ainslie (Purism)		ti,boost-max-current = <50000>; /* 50mA */
498eb4ea085SAngus Ainslie (Purism)	};
499eb4ea085SAngus Ainslie (Purism)};
500eb4ea085SAngus Ainslie (Purism)
501eb4ea085SAngus Ainslie (Purism)&i2c3 {
502eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
503eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
504eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c3>;
505eb4ea085SAngus Ainslie (Purism)	status = "okay";
506eb4ea085SAngus Ainslie (Purism)
507eb4ea085SAngus Ainslie (Purism)	magnetometer@1e	{
508eb4ea085SAngus Ainslie (Purism)		compatible = "st,lsm9ds1-magn";
509eb4ea085SAngus Ainslie (Purism)		reg = <0x1e>;
510eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
511eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_imu>;
512eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
513106f7b3bSAngus Ainslie (Purism)		interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
514eb4ea085SAngus Ainslie (Purism)		vdd-supply = <&reg_3v3_p>;
515eb4ea085SAngus Ainslie (Purism)		vddio-supply = <&reg_3v3_p>;
516eb4ea085SAngus Ainslie (Purism)	};
517eb4ea085SAngus Ainslie (Purism)
518c53f0166SAngus Ainslie (Purism)	sgtl5000: audio-codec@a {
519c53f0166SAngus Ainslie (Purism)		compatible = "fsl,sgtl5000";
520c53f0166SAngus Ainslie (Purism)		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
521c53f0166SAngus Ainslie (Purism)		assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
522c53f0166SAngus Ainslie (Purism)		assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
523c53f0166SAngus Ainslie (Purism)		assigned-clock-rates = <24576000>;
524c53f0166SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
525c53f0166SAngus Ainslie (Purism)		reg = <0x0a>;
526c53f0166SAngus Ainslie (Purism)		VDDD-supply = <&reg_1v8_p>;
527c53f0166SAngus Ainslie (Purism)		VDDIO-supply = <&reg_3v3_p>;
528c53f0166SAngus Ainslie (Purism)		VDDA-supply = <&reg_3v3_p>;
529c53f0166SAngus Ainslie (Purism)	};
530c53f0166SAngus Ainslie (Purism)
531eb4ea085SAngus Ainslie (Purism)	touchscreen@5d {
532eb4ea085SAngus Ainslie (Purism)		compatible = "goodix,gt5688";
533eb4ea085SAngus Ainslie (Purism)		reg = <0x5d>;
534eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
535eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_ts>;
536eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
537eb4ea085SAngus Ainslie (Purism)		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
538eb4ea085SAngus Ainslie (Purism)		reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
539eb4ea085SAngus Ainslie (Purism)		irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
540eb4ea085SAngus Ainslie (Purism)		touchscreen-size-x = <720>;
541eb4ea085SAngus Ainslie (Purism)		touchscreen-size-y = <1440>;
542eb4ea085SAngus Ainslie (Purism)		AVDD28-supply = <&reg_2v8_p>;
543eb4ea085SAngus Ainslie (Purism)		VDDIO-supply = <&reg_1v8_p>;
544eb4ea085SAngus Ainslie (Purism)	};
545537c00e3SMartin Kepplinger
546ea38ca9aSGuido Günther	proximity-sensor@60 {
547ea38ca9aSGuido Günther		compatible = "vishay,vcnl4040";
548ea38ca9aSGuido Günther		reg = <0x60>;
549ea38ca9aSGuido Günther		pinctrl-0 = <&pinctrl_prox>;
550ea38ca9aSGuido Günther	};
551ea38ca9aSGuido Günther
552537c00e3SMartin Kepplinger	accel-gyro@6a {
553537c00e3SMartin Kepplinger		compatible = "st,lsm9ds1-imu";
554537c00e3SMartin Kepplinger		reg = <0x6a>;
555537c00e3SMartin Kepplinger		vdd-supply = <&reg_3v3_p>;
556537c00e3SMartin Kepplinger		vddio-supply = <&reg_3v3_p>;
557eef22bb1SMartin Kepplinger		mount-matrix =  "1",  "0",  "0",
558eef22bb1SMartin Kepplinger				"0",  "1",  "0",
559eef22bb1SMartin Kepplinger				"0",  "0", "-1";
560537c00e3SMartin Kepplinger	};
561eb4ea085SAngus Ainslie (Purism)};
562eb4ea085SAngus Ainslie (Purism)
563eb4ea085SAngus Ainslie (Purism)&iomuxc {
564eb4ea085SAngus Ainslie (Purism)	pinctrl_bl: blgrp {
565eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
566eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT	0x6 /* DSI_BL_PWM */
567eb4ea085SAngus Ainslie (Purism)		>;
568eb4ea085SAngus Ainslie (Purism)	};
569eb4ea085SAngus Ainslie (Purism)
570eb4ea085SAngus Ainslie (Purism)	pinctrl_bt: btgrp {
571eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
572eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11	0x16 /* nBT_DISABLE */
573eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7	0x10 /* BT_HOST_WAKE */
574eb4ea085SAngus Ainslie (Purism)		>;
575eb4ea085SAngus Ainslie (Purism)	};
576eb4ea085SAngus Ainslie (Purism)
577eb4ea085SAngus Ainslie (Purism)	pinctrl_charger: chargergrp {
578eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
579eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x80 /* CHRG_nINT */
580eb4ea085SAngus Ainslie (Purism)		>;
581eb4ea085SAngus Ainslie (Purism)	};
582eb4ea085SAngus Ainslie (Purism)
583eb4ea085SAngus Ainslie (Purism)	pinctrl_fec1: fec1grp {
584eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
585eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
586eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
587eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
588eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
589eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
590eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
591eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
592eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
593eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
594eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
595eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
596eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
597eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
598eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
599eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
600eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x1f
601eb4ea085SAngus Ainslie (Purism)		>;
602eb4ea085SAngus Ainslie (Purism)	};
603eb4ea085SAngus Ainslie (Purism)
604eb4ea085SAngus Ainslie (Purism)	pinctrl_ts: tsgrp {
605eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
606eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0		0x16  /* TOUCH INT */
607eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19  /* TOUCH RST */
608eb4ea085SAngus Ainslie (Purism)		>;
609eb4ea085SAngus Ainslie (Purism)	};
610eb4ea085SAngus Ainslie (Purism)
611eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_leds: gpioledgrp {
612eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
613eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16
614eb4ea085SAngus Ainslie (Purism)		>;
615eb4ea085SAngus Ainslie (Purism)	};
616eb4ea085SAngus Ainslie (Purism)
617eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_keys: gpiokeygrp {
618eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
619eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x16
620eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22	0x16
621eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x180  /* HP_DET */
6223ef506b3SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80   /* nWoWWAN */
623eb4ea085SAngus Ainslie (Purism)		>;
624eb4ea085SAngus Ainslie (Purism)	};
625eb4ea085SAngus Ainslie (Purism)
626eb4ea085SAngus Ainslie (Purism)	pinctrl_haptic: hapticgrp {
627eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
628eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4		0xc6   /* nHAPTIC */
629eb4ea085SAngus Ainslie (Purism)		>;
630eb4ea085SAngus Ainslie (Purism)	};
631eb4ea085SAngus Ainslie (Purism)
632eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c1: i2c1grp {
633eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
634eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000001f
635eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000001f
636eb4ea085SAngus Ainslie (Purism)		>;
637eb4ea085SAngus Ainslie (Purism)	};
638eb4ea085SAngus Ainslie (Purism)
639eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c3: i2c3grp {
640eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
641eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x4000001f
642eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x4000001f
643eb4ea085SAngus Ainslie (Purism)		>;
644eb4ea085SAngus Ainslie (Purism)	};
645eb4ea085SAngus Ainslie (Purism)
646eb4ea085SAngus Ainslie (Purism)	pinctrl_imu: imugrp {
647eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
648eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x8  /* IMU_INT */
649eb4ea085SAngus Ainslie (Purism)		>;
650eb4ea085SAngus Ainslie (Purism)	};
651eb4ea085SAngus Ainslie (Purism)
6526f46f7ffSGuido Günther	pinctrl_spkamp: spkamp {
6536f46f7ffSGuido Günther		fsl,pins = <
6546f46f7ffSGuido Günther			MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3		0x81  /* MUTE */
6556f46f7ffSGuido Günther		>;
6566f46f7ffSGuido Günther	};
6576f46f7ffSGuido Günther
658eb4ea085SAngus Ainslie (Purism)	pinctrl_pmic: pmicgrp {
659eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
660eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x80  /* PMIC intr */
661eb4ea085SAngus Ainslie (Purism)		>;
662eb4ea085SAngus Ainslie (Purism)	};
663eb4ea085SAngus Ainslie (Purism)
664ea38ca9aSGuido Günther	pinctrl_prox: proxgrp {
665ea38ca9aSGuido Günther		fsl,pins = <
666ea38ca9aSGuido Günther			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x80  /* prox intr */
667ea38ca9aSGuido Günther		>;
668ea38ca9aSGuido Günther	};
669ea38ca9aSGuido Günther
670eb4ea085SAngus Ainslie (Purism)	pinctrl_pwr_en: pwrengrp {
671eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
672eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x06
673eb4ea085SAngus Ainslie (Purism)		>;
674eb4ea085SAngus Ainslie (Purism)	};
675eb4ea085SAngus Ainslie (Purism)
676eb4ea085SAngus Ainslie (Purism)	pinctrl_rtc: rtcgrp {
677eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
678eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29	0x80  /* RTC intr */
679eb4ea085SAngus Ainslie (Purism)		>;
680eb4ea085SAngus Ainslie (Purism)	};
681eb4ea085SAngus Ainslie (Purism)
682c53f0166SAngus Ainslie (Purism)	pinctrl_sai2: sai2grp {
683c53f0166SAngus Ainslie (Purism)		fsl,pins = <
684c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
685c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
686c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
687c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6
688c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
689c53f0166SAngus Ainslie (Purism)		>;
690c53f0166SAngus Ainslie (Purism)	};
691c53f0166SAngus Ainslie (Purism)
6927f7b7997SAngus Ainslie (Purism)	pinctrl_sai6: sai6grp {
6937f7b7997SAngus Ainslie (Purism)		fsl,pins = <
6947f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0	0xd6
6957f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC	0xd6
6967f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK     0xd6
6977f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0	0xd6
6987f7b7997SAngus Ainslie (Purism)		>;
6997f7b7997SAngus Ainslie (Purism)	};
7007f7b7997SAngus Ainslie (Purism)
701eb4ea085SAngus Ainslie (Purism)	pinctrl_typec: typecgrp {
702eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
703eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x16
704eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x80
705eb4ea085SAngus Ainslie (Purism)		>;
706eb4ea085SAngus Ainslie (Purism)	};
707eb4ea085SAngus Ainslie (Purism)
708eb4ea085SAngus Ainslie (Purism)	pinctrl_uart1: uart1grp {
709eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
710eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
711eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
712eb4ea085SAngus Ainslie (Purism)		>;
713eb4ea085SAngus Ainslie (Purism)	};
714eb4ea085SAngus Ainslie (Purism)
715eb4ea085SAngus Ainslie (Purism)	pinctrl_uart2: uart2grp {
716eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
717eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
718eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
719eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
720eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
721eb4ea085SAngus Ainslie (Purism)		>;
722eb4ea085SAngus Ainslie (Purism)	};
723eb4ea085SAngus Ainslie (Purism)
724eb4ea085SAngus Ainslie (Purism)	pinctrl_uart3: uart3grp {
725eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
726eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
727eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
728eb4ea085SAngus Ainslie (Purism)		>;
729eb4ea085SAngus Ainslie (Purism)	};
730eb4ea085SAngus Ainslie (Purism)
731eb4ea085SAngus Ainslie (Purism)	pinctrl_uart4: uart4grp {
732eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
733eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
734eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
735eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x49
736eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49
737eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x49
738eb4ea085SAngus Ainslie (Purism)		>;
739eb4ea085SAngus Ainslie (Purism)	};
740eb4ea085SAngus Ainslie (Purism)
741eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1: usdhc1grp {
742eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
743eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
744eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
745eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
746eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
747eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
748eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
749eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
750eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
751eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
752eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
753eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
754eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
755eb4ea085SAngus Ainslie (Purism)		>;
756eb4ea085SAngus Ainslie (Purism)	};
757eb4ea085SAngus Ainslie (Purism)
758ae560c43SKrzysztof Kozlowski	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
759eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
760eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
761eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
762eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
763eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
764eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
765eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
766eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
767eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
768eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
769eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
770eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
771eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
772eb4ea085SAngus Ainslie (Purism)		>;
773eb4ea085SAngus Ainslie (Purism)	};
774eb4ea085SAngus Ainslie (Purism)
775ae560c43SKrzysztof Kozlowski	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
776eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
777eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
778eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
779eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
780eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
781eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
782eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
783eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
784eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
785eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
786eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
787eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
788eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
789eb4ea085SAngus Ainslie (Purism)		>;
790eb4ea085SAngus Ainslie (Purism)	};
791eb4ea085SAngus Ainslie (Purism)
792ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_pwr: usdhc2pwrgrp {
793eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
794eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
795eb4ea085SAngus Ainslie (Purism)		>;
796eb4ea085SAngus Ainslie (Purism)	};
797eb4ea085SAngus Ainslie (Purism)
798ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
799eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
800eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */
801eb4ea085SAngus Ainslie (Purism)		>;
802eb4ea085SAngus Ainslie (Purism)	};
803eb4ea085SAngus Ainslie (Purism)
804eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2: usdhc2grp {
805eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
806eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
807eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
808eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
809eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
810eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
811eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
812eb4ea085SAngus Ainslie (Purism)		>;
813eb4ea085SAngus Ainslie (Purism)	};
814eb4ea085SAngus Ainslie (Purism)
815ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
816eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
817eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d
818eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd
819eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcd
820eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcd
821eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcd
822eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcd
823eb4ea085SAngus Ainslie (Purism)		>;
824eb4ea085SAngus Ainslie (Purism)	};
825eb4ea085SAngus Ainslie (Purism)
826ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
827eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
828eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f
829eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf
830eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcf
831eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcf
832eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcf
833eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcf
834eb4ea085SAngus Ainslie (Purism)		>;
835eb4ea085SAngus Ainslie (Purism)	};
836eb4ea085SAngus Ainslie (Purism)
837eb4ea085SAngus Ainslie (Purism)	pinctrl_wdog: wdoggrp {
838eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
839eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
840eb4ea085SAngus Ainslie (Purism)		>;
841eb4ea085SAngus Ainslie (Purism)	};
842eb4ea085SAngus Ainslie (Purism)
843eb4ea085SAngus Ainslie (Purism)	pinctrl_wifi_pwr_en: wifipwrengrp {
844eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
845eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5         0x06
846eb4ea085SAngus Ainslie (Purism)		>;
847eb4ea085SAngus Ainslie (Purism)	};
848eb4ea085SAngus Ainslie (Purism)
849eb4ea085SAngus Ainslie (Purism)	pinctrl_wwan: wwangrp {
850eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
851eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x09 /* nWWAN_DISABLE */
852eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80 /* nWoWWAN */
853eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9	0x19 /* WWAN_RESET */
854eb4ea085SAngus Ainslie (Purism)		>;
855eb4ea085SAngus Ainslie (Purism)	};
856eb4ea085SAngus Ainslie (Purism)};
857eb4ea085SAngus Ainslie (Purism)
858e8151ef3SGuido Günther&lcdif {
859e8151ef3SGuido Günther	status = "okay";
860e8151ef3SGuido Günther};
861e8151ef3SGuido Günther
862e8151ef3SGuido Günther&mipi_dsi {
863e8151ef3SGuido Günther	status = "okay";
864e8151ef3SGuido Günther	#address-cells = <1>;
865e8151ef3SGuido Günther	#size-cells = <0>;
866e8151ef3SGuido Günther
867e8151ef3SGuido Günther	panel@0 {
868e8151ef3SGuido Günther		compatible = "rocktech,jh057n00900";
869e8151ef3SGuido Günther		reg = <0>;
870e8151ef3SGuido Günther		backlight = <&backlight_dsi>;
871e8151ef3SGuido Günther		reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
872e8151ef3SGuido Günther		iovcc-supply = <&reg_1v8_p>;
873e8151ef3SGuido Günther		vcc-supply = <&reg_2v8_p>;
874e8151ef3SGuido Günther		port {
875e8151ef3SGuido Günther			panel_in: endpoint {
876e8151ef3SGuido Günther				remote-endpoint = <&mipi_dsi_out>;
877e8151ef3SGuido Günther			};
878e8151ef3SGuido Günther		};
879e8151ef3SGuido Günther	};
880e8151ef3SGuido Günther
881e8151ef3SGuido Günther	ports {
882e8151ef3SGuido Günther		port@1 {
883e8151ef3SGuido Günther			reg = <1>;
884e8151ef3SGuido Günther			mipi_dsi_out: endpoint {
885e8151ef3SGuido Günther				remote-endpoint = <&panel_in>;
886e8151ef3SGuido Günther			};
887e8151ef3SGuido Günther		};
888e8151ef3SGuido Günther	};
889e8151ef3SGuido Günther};
890e8151ef3SGuido Günther
891eb4ea085SAngus Ainslie (Purism)&pgc_gpu {
892eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck3_reg>;
893eb4ea085SAngus Ainslie (Purism)};
894eb4ea085SAngus Ainslie (Purism)
895eb4ea085SAngus Ainslie (Purism)&pgc_vpu {
896eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck4_reg>;
897eb4ea085SAngus Ainslie (Purism)};
898eb4ea085SAngus Ainslie (Purism)
899eb4ea085SAngus Ainslie (Purism)&pwm1 {
900eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
901eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_bl>;
902eb4ea085SAngus Ainslie (Purism)	status = "okay";
903eb4ea085SAngus Ainslie (Purism)};
904eb4ea085SAngus Ainslie (Purism)
90501407158SAngus Ainslie (Purism)&snvs_pwrkey {
90601407158SAngus Ainslie (Purism)	status = "okay";
90701407158SAngus Ainslie (Purism)};
908eb4ea085SAngus Ainslie (Purism)
909ff38c1ddSGuido Günther&snvs_rtc {
910ff38c1ddSGuido Günther	status = "disabled";
911ff38c1ddSGuido Günther};
912ff38c1ddSGuido Günther
913c53f0166SAngus Ainslie (Purism)&sai2 {
914c53f0166SAngus Ainslie (Purism)	pinctrl-names = "default";
915c53f0166SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai2>;
916c53f0166SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
917c53f0166SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
918c53f0166SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
919c53f0166SAngus Ainslie (Purism)	status = "okay";
920c53f0166SAngus Ainslie (Purism)};
921c53f0166SAngus Ainslie (Purism)
9227f7b7997SAngus Ainslie (Purism)&sai6 {
9237f7b7997SAngus Ainslie (Purism)	pinctrl-names = "default";
9247f7b7997SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai6>;
9257f7b7997SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI6>;
9267f7b7997SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
9277f7b7997SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
9287f7b7997SAngus Ainslie (Purism)	fsl,sai-synchronous-rx;
9297f7b7997SAngus Ainslie (Purism)	status = "okay";
9307f7b7997SAngus Ainslie (Purism)};
9317f7b7997SAngus Ainslie (Purism)
932eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */
933eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
934eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart1>;
935eb4ea085SAngus Ainslie (Purism)	status = "okay";
936eb4ea085SAngus Ainslie (Purism)};
937eb4ea085SAngus Ainslie (Purism)
938eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */
939eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
940eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart3>;
941eb4ea085SAngus Ainslie (Purism)	status = "okay";
942eb4ea085SAngus Ainslie (Purism)};
943eb4ea085SAngus Ainslie (Purism)
944eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */
945eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
946eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
947eb4ea085SAngus Ainslie (Purism)	uart-has-rtscts;
948eb4ea085SAngus Ainslie (Purism)	status = "okay";
949eb4ea085SAngus Ainslie (Purism)};
950eb4ea085SAngus Ainslie (Purism)
951eb4ea085SAngus Ainslie (Purism)&usb3_phy0 {
952dde061b8SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
953eb4ea085SAngus Ainslie (Purism)	status = "okay";
954eb4ea085SAngus Ainslie (Purism)};
955eb4ea085SAngus Ainslie (Purism)
956eb4ea085SAngus Ainslie (Purism)&usb3_phy1 {
957eb4ea085SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
958eb4ea085SAngus Ainslie (Purism)	status = "okay";
959eb4ea085SAngus Ainslie (Purism)};
960eb4ea085SAngus Ainslie (Purism)
961eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 {
962eb4ea085SAngus Ainslie (Purism)	#address-cells = <1>;
963eb4ea085SAngus Ainslie (Purism)	#size-cells = <0>;
964eb4ea085SAngus Ainslie (Purism)	dr_mode = "otg";
965eb4ea085SAngus Ainslie (Purism)	status = "okay";
966eb4ea085SAngus Ainslie (Purism)
967eb4ea085SAngus Ainslie (Purism)	port@0 {
968eb4ea085SAngus Ainslie (Purism)		reg = <0>;
969eb4ea085SAngus Ainslie (Purism)
970eb4ea085SAngus Ainslie (Purism)		typec_hs: endpoint {
971eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_hs>;
972eb4ea085SAngus Ainslie (Purism)		};
973eb4ea085SAngus Ainslie (Purism)	};
974eb4ea085SAngus Ainslie (Purism)
975eb4ea085SAngus Ainslie (Purism)	port@1 {
976eb4ea085SAngus Ainslie (Purism)		reg = <1>;
977eb4ea085SAngus Ainslie (Purism)
978eb4ea085SAngus Ainslie (Purism)		typec_ss: endpoint {
979eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_ss>;
980eb4ea085SAngus Ainslie (Purism)		};
981eb4ea085SAngus Ainslie (Purism)	};
982eb4ea085SAngus Ainslie (Purism)};
983eb4ea085SAngus Ainslie (Purism)
984eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 {
985eb4ea085SAngus Ainslie (Purism)	dr_mode = "host";
986eb4ea085SAngus Ainslie (Purism)	status = "okay";
987eb4ea085SAngus Ainslie (Purism)};
988eb4ea085SAngus Ainslie (Purism)
989eb4ea085SAngus Ainslie (Purism)&usdhc1 {
990e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
991e045f044SAnson Huang	assigned-clock-rates = <400000000>;
992eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
993eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc1>;
994eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
995eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
996eb4ea085SAngus Ainslie (Purism)	bus-width = <8>;
997eb4ea085SAngus Ainslie (Purism)	non-removable;
998eb4ea085SAngus Ainslie (Purism)	status = "okay";
999eb4ea085SAngus Ainslie (Purism)};
1000eb4ea085SAngus Ainslie (Purism)
1001eb4ea085SAngus Ainslie (Purism)&usdhc2 {
1002e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
1003e045f044SAnson Huang	assigned-clock-rates = <200000000>;
1004eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
1005eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc2>;
1006eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
1007eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
1008eb4ea085SAngus Ainslie (Purism)	bus-width = <4>;
1009eb4ea085SAngus Ainslie (Purism)	vmmc-supply = <&reg_usdhc2_vmmc>;
1010eb4ea085SAngus Ainslie (Purism)	power-supply = <&wifi_pwr_en>;
10119dae8563SAngus Ainslie (Purism)	broken-cd;
1012eb4ea085SAngus Ainslie (Purism)	disable-wp;
1013eb4ea085SAngus Ainslie (Purism)	cap-sdio-irq;
1014eb4ea085SAngus Ainslie (Purism)	keep-power-in-suspend;
1015eb4ea085SAngus Ainslie (Purism)	wakeup-source;
1016eb4ea085SAngus Ainslie (Purism)	status = "okay";
1017eb4ea085SAngus Ainslie (Purism)};
1018eb4ea085SAngus Ainslie (Purism)
1019eb4ea085SAngus Ainslie (Purism)&wdog1 {
1020eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
1021eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_wdog>;
1022eb4ea085SAngus Ainslie (Purism)	fsl,ext-reset-output;
1023eb4ea085SAngus Ainslie (Purism)	status = "okay";
1024eb4ea085SAngus Ainslie (Purism)};
1025