1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+
2eb4ea085SAngus Ainslie (Purism)/*
3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC
4eb4ea085SAngus Ainslie (Purism) */
5eb4ea085SAngus Ainslie (Purism)
6eb4ea085SAngus Ainslie (Purism)/dts-v1/;
7eb4ea085SAngus Ainslie (Purism)
8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h"
9d8fa4792SKrzysztof Kozlowski#include <dt-bindings/interrupt-controller/irq.h>
10eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h"
11eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h"
12eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi"
13eb4ea085SAngus Ainslie (Purism)
14eb4ea085SAngus Ainslie (Purism)/ {
15eb4ea085SAngus Ainslie (Purism)	model = "Purism Librem 5 devkit";
16eb4ea085SAngus Ainslie (Purism)	compatible = "purism,librem5-devkit", "fsl,imx8mq";
17eb4ea085SAngus Ainslie (Purism)
18eb4ea085SAngus Ainslie (Purism)	backlight_dsi: backlight-dsi {
19eb4ea085SAngus Ainslie (Purism)		compatible = "pwm-backlight";
20eb4ea085SAngus Ainslie (Purism)		/* 200 Hz for the PAM2841 */
21eb4ea085SAngus Ainslie (Purism)		pwms = <&pwm1 0 5000000>;
22eb4ea085SAngus Ainslie (Purism)		brightness-levels = <0 100>;
23eb4ea085SAngus Ainslie (Purism)		num-interpolated-steps = <100>;
24eb4ea085SAngus Ainslie (Purism)		/* Default brightness level (index into the array defined by */
25eb4ea085SAngus Ainslie (Purism)		/* the "brightness-levels" property) */
26eb4ea085SAngus Ainslie (Purism)		default-brightness-level = <0>;
27eb4ea085SAngus Ainslie (Purism)		power-supply = <&reg_22v4_p>;
28eb4ea085SAngus Ainslie (Purism)	};
29eb4ea085SAngus Ainslie (Purism)
30eb4ea085SAngus Ainslie (Purism)	chosen {
31eb4ea085SAngus Ainslie (Purism)		stdout-path = &uart1;
32eb4ea085SAngus Ainslie (Purism)	};
33eb4ea085SAngus Ainslie (Purism)
34eb4ea085SAngus Ainslie (Purism)	gpio-keys {
35eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-keys";
36eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
37eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_keys>;
38eb4ea085SAngus Ainslie (Purism)
39eb4ea085SAngus Ainslie (Purism)		btn1 {
40eb4ea085SAngus Ainslie (Purism)			label = "VOL_UP";
41eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
42eb4ea085SAngus Ainslie (Purism)			wakeup-source;
43eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEUP>;
44eb4ea085SAngus Ainslie (Purism)		};
45eb4ea085SAngus Ainslie (Purism)
46eb4ea085SAngus Ainslie (Purism)		btn2 {
47eb4ea085SAngus Ainslie (Purism)			label = "VOL_DOWN";
48eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
49eb4ea085SAngus Ainslie (Purism)			wakeup-source;
50eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_VOLUMEDOWN>;
51eb4ea085SAngus Ainslie (Purism)		};
52eb4ea085SAngus Ainslie (Purism)
53eb4ea085SAngus Ainslie (Purism)		hp-det {
54eb4ea085SAngus Ainslie (Purism)			label = "HP_DET";
55eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
56eb4ea085SAngus Ainslie (Purism)			wakeup-source;
57eb4ea085SAngus Ainslie (Purism)			linux,code = <KEY_HP>;
58eb4ea085SAngus Ainslie (Purism)		};
593ef506b3SAngus Ainslie (Purism)
603ef506b3SAngus Ainslie (Purism)		wwan-wake {
613ef506b3SAngus Ainslie (Purism)			label = "WWAN_WAKE";
623ef506b3SAngus Ainslie (Purism)			gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
633ef506b3SAngus Ainslie (Purism)			interrupt-parent = <&gpio3>;
64d8fa4792SKrzysztof Kozlowski			interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
653ef506b3SAngus Ainslie (Purism)			wakeup-source;
663ef506b3SAngus Ainslie (Purism)			linux,code = <KEY_PHONE>;
673ef506b3SAngus Ainslie (Purism)		};
68eb4ea085SAngus Ainslie (Purism)	};
69eb4ea085SAngus Ainslie (Purism)
70eb4ea085SAngus Ainslie (Purism)	leds {
71eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-leds";
72eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
73eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_gpio_leds>;
74eb4ea085SAngus Ainslie (Purism)
75eb4ea085SAngus Ainslie (Purism)		led1 {
76eb4ea085SAngus Ainslie (Purism)			label = "LED 1";
77eb4ea085SAngus Ainslie (Purism)			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
78eb4ea085SAngus Ainslie (Purism)			default-state = "off";
79eb4ea085SAngus Ainslie (Purism)		};
80eb4ea085SAngus Ainslie (Purism)	};
81eb4ea085SAngus Ainslie (Purism)
82eb4ea085SAngus Ainslie (Purism)	pmic_osc: clock-pmic {
83eb4ea085SAngus Ainslie (Purism)		compatible = "fixed-clock";
84eb4ea085SAngus Ainslie (Purism)		#clock-cells = <0>;
85eb4ea085SAngus Ainslie (Purism)		clock-frequency = <32768>;
86eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_osc";
87eb4ea085SAngus Ainslie (Purism)	};
88eb4ea085SAngus Ainslie (Purism)
89eb4ea085SAngus Ainslie (Purism)	reg_1v8_p: regulator-1v8-p {
90eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
91eb4ea085SAngus Ainslie (Purism)		regulator-name = "1v8_p";
92eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <1800000>;
93eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <1800000>;
94eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
95eb4ea085SAngus Ainslie (Purism)	};
96eb4ea085SAngus Ainslie (Purism)
97eb4ea085SAngus Ainslie (Purism)	reg_2v8_p: regulator-2v8-p {
98eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
99eb4ea085SAngus Ainslie (Purism)		regulator-name = "2v8_p";
100eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <2800000>;
101eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <2800000>;
102eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
103eb4ea085SAngus Ainslie (Purism)	};
104eb4ea085SAngus Ainslie (Purism)
105eb4ea085SAngus Ainslie (Purism)	reg_3v3_p: regulator-3v3-p {
106eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
107eb4ea085SAngus Ainslie (Purism)		regulator-name = "3v3_p";
108eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
109eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
110eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
111eb4ea085SAngus Ainslie (Purism)
112eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
113eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
114eb4ea085SAngus Ainslie (Purism)		};
115eb4ea085SAngus Ainslie (Purism)	};
116eb4ea085SAngus Ainslie (Purism)
117eb4ea085SAngus Ainslie (Purism)	reg_5v_p: regulator-5v-p {
118eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
119eb4ea085SAngus Ainslie (Purism)		regulator-name = "5v_p";
120eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <5000000>;
121eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <5000000>;
122eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
123eb4ea085SAngus Ainslie (Purism)
124eb4ea085SAngus Ainslie (Purism)		regulator-state-mem {
125eb4ea085SAngus Ainslie (Purism)			regulator-on-in-suspend;
126eb4ea085SAngus Ainslie (Purism)		};
127eb4ea085SAngus Ainslie (Purism)	};
128eb4ea085SAngus Ainslie (Purism)
129eb4ea085SAngus Ainslie (Purism)	reg_22v4_p: regulator-22v4-p  {
130eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
131eb4ea085SAngus Ainslie (Purism)		regulator-name = "22v4_P";
132eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <22400000>;
133eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <22400000>;
134eb4ea085SAngus Ainslie (Purism)		vin-supply = <&reg_pwr_en>;
135eb4ea085SAngus Ainslie (Purism)	};
136eb4ea085SAngus Ainslie (Purism)
137eb4ea085SAngus Ainslie (Purism)	reg_pwr_en: regulator-pwr-en {
138eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
139eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
140eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pwr_en>;
141eb4ea085SAngus Ainslie (Purism)		regulator-name = "PWR_EN";
142eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
143eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
144eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
145eb4ea085SAngus Ainslie (Purism)		enable-active-high;
146eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
147eb4ea085SAngus Ainslie (Purism)	};
148eb4ea085SAngus Ainslie (Purism)
149eb4ea085SAngus Ainslie (Purism)	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
150eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
151eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
152eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_usdhc2_pwr>;
153eb4ea085SAngus Ainslie (Purism)		regulator-name = "VSD_3V3";
154eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
155eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
156eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
157eb4ea085SAngus Ainslie (Purism)		enable-active-high;
158eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
159eb4ea085SAngus Ainslie (Purism)	};
160eb4ea085SAngus Ainslie (Purism)
1617f7b7997SAngus Ainslie (Purism)	wwan_codec: sound-wwan-codec {
1627f7b7997SAngus Ainslie (Purism)		compatible = "option,gtm601";
1637f7b7997SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
1647f7b7997SAngus Ainslie (Purism)	};
1657f7b7997SAngus Ainslie (Purism)
166*15094482SGuido Günther	mic_mux: mic-mux {
167*15094482SGuido Günther		compatible = "simple-audio-mux";
168*15094482SGuido Günther		pinctrl-names = "default";
169*15094482SGuido Günther		pinctrl-0 = <&pinctrl_micsel>;
170*15094482SGuido Günther		mux-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
171*15094482SGuido Günther		sound-name-prefix = "Mic Mux";
172*15094482SGuido Günther	};
173*15094482SGuido Günther
174c53f0166SAngus Ainslie (Purism)	sound {
175c53f0166SAngus Ainslie (Purism)		compatible = "simple-audio-card";
176*15094482SGuido Günther		simple-audio-card,aux-devs = <&speaker_amp>, <&mic_mux>;
1775b65f39dSGuido Günther		simple-audio-card,name = "Librem 5 Devkit";
178c53f0166SAngus Ainslie (Purism)		simple-audio-card,format = "i2s";
179c53f0166SAngus Ainslie (Purism)		simple-audio-card,widgets =
180*15094482SGuido Günther			"Microphone", "Builtin Microphone",
181*15094482SGuido Günther			"Microphone", "Headset Microphone",
182c53f0166SAngus Ainslie (Purism)			"Headphone", "Headphone Jack",
18339a346d9SGuido Günther			"Speaker", "Builtin Speaker";
184c53f0166SAngus Ainslie (Purism)		simple-audio-card,routing =
185*15094482SGuido Günther			"MIC_IN", "Mic Mux OUT",
186*15094482SGuido Günther			"Mic Mux IN1", "Headset Microphone",
187*15094482SGuido Günther			"Mic Mux IN2", "Builtin Microphone",
188*15094482SGuido Günther			"Mic Mux OUT", "Mic Bias",
189c53f0166SAngus Ainslie (Purism)			"Headphone Jack", "HP_OUT",
1906f46f7ffSGuido Günther			"Builtin Speaker", "Speaker Amp OUTR",
1916f46f7ffSGuido Günther			"Speaker Amp INR", "LINE_OUT";
192c53f0166SAngus Ainslie (Purism)
193c53f0166SAngus Ainslie (Purism)		simple-audio-card,cpu {
194c53f0166SAngus Ainslie (Purism)			sound-dai = <&sai2>;
195c53f0166SAngus Ainslie (Purism)		};
196c53f0166SAngus Ainslie (Purism)
197c53f0166SAngus Ainslie (Purism)		simple-audio-card,codec {
198c53f0166SAngus Ainslie (Purism)			sound-dai = <&sgtl5000>;
199c53f0166SAngus Ainslie (Purism)			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
200c53f0166SAngus Ainslie (Purism)			frame-master;
201c53f0166SAngus Ainslie (Purism)			bitclock-master;
202c53f0166SAngus Ainslie (Purism)		};
203c53f0166SAngus Ainslie (Purism)	};
204c53f0166SAngus Ainslie (Purism)
2057f7b7997SAngus Ainslie (Purism)	sound-wwan {
2067f7b7997SAngus Ainslie (Purism)		compatible = "simple-audio-card";
2077f7b7997SAngus Ainslie (Purism)		simple-audio-card,name = "SIMCom SIM7100";
2087f7b7997SAngus Ainslie (Purism)		simple-audio-card,format = "dsp_a";
2097f7b7997SAngus Ainslie (Purism)
2107f7b7997SAngus Ainslie (Purism)		simple-audio-card,cpu {
2117f7b7997SAngus Ainslie (Purism)			sound-dai = <&sai6>;
2127f7b7997SAngus Ainslie (Purism)		};
2137f7b7997SAngus Ainslie (Purism)
2147f7b7997SAngus Ainslie (Purism)		telephony_link_master: simple-audio-card,codec {
2157f7b7997SAngus Ainslie (Purism)			sound-dai = <&wwan_codec>;
2167f7b7997SAngus Ainslie (Purism)			frame-master;
2177f7b7997SAngus Ainslie (Purism)			bitclock-master;
2187f7b7997SAngus Ainslie (Purism)		};
2197f7b7997SAngus Ainslie (Purism)	};
2207f7b7997SAngus Ainslie (Purism)
2216f46f7ffSGuido Günther	speaker_amp: speaker-amp {
2226f46f7ffSGuido Günther		compatible = "simple-audio-amplifier";
2236f46f7ffSGuido Günther		pinctrl-names = "default";
2246f46f7ffSGuido Günther		pinctrl-0 = <&pinctrl_spkamp>;
2256f46f7ffSGuido Günther		VCC-supply = <&reg_3v3_p>;
2266f46f7ffSGuido Günther		sound-name-prefix = "Speaker Amp";
2276f46f7ffSGuido Günther		enable-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
2286f46f7ffSGuido Günther	};
2296f46f7ffSGuido Günther
230eb4ea085SAngus Ainslie (Purism)	vibrator {
231eb4ea085SAngus Ainslie (Purism)		compatible = "gpio-vibrator";
232eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
233eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_haptic>;
234eb4ea085SAngus Ainslie (Purism)	        enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
235eb4ea085SAngus Ainslie (Purism)		vcc-supply = <&reg_3v3_p>;
236eb4ea085SAngus Ainslie (Purism)	};
237eb4ea085SAngus Ainslie (Purism)
238eb4ea085SAngus Ainslie (Purism)	wifi_pwr_en: regulator-wifi-en {
239eb4ea085SAngus Ainslie (Purism)		compatible = "regulator-fixed";
240eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
241eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
242eb4ea085SAngus Ainslie (Purism)		regulator-name = "WIFI_EN";
243eb4ea085SAngus Ainslie (Purism)		regulator-min-microvolt = <3300000>;
244eb4ea085SAngus Ainslie (Purism)		regulator-max-microvolt = <3300000>;
245eb4ea085SAngus Ainslie (Purism)		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
246eb4ea085SAngus Ainslie (Purism)		enable-active-high;
247eb4ea085SAngus Ainslie (Purism)		regulator-always-on;
248eb4ea085SAngus Ainslie (Purism)	};
249eb4ea085SAngus Ainslie (Purism)};
250eb4ea085SAngus Ainslie (Purism)
251a2e47ba2SAngus Ainslie (Purism)&A53_0 {
252a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
253a2e47ba2SAngus Ainslie (Purism)};
254a2e47ba2SAngus Ainslie (Purism)
255a2e47ba2SAngus Ainslie (Purism)&A53_1 {
256a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
257a2e47ba2SAngus Ainslie (Purism)};
258a2e47ba2SAngus Ainslie (Purism)
259a2e47ba2SAngus Ainslie (Purism)&A53_2 {
260a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
261a2e47ba2SAngus Ainslie (Purism)};
262a2e47ba2SAngus Ainslie (Purism)
263a2e47ba2SAngus Ainslie (Purism)&A53_3 {
264a2e47ba2SAngus Ainslie (Purism)	cpu-supply = <&buck2_reg>;
265a2e47ba2SAngus Ainslie (Purism)};
266a2e47ba2SAngus Ainslie (Purism)
2679d9005a5SGuido Günther&dphy {
2689d9005a5SGuido Günther	status = "okay";
2699d9005a5SGuido Günther};
2709d9005a5SGuido Günther
271eb4ea085SAngus Ainslie (Purism)&fec1 {
272eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
273eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_fec1>;
274eb4ea085SAngus Ainslie (Purism)	phy-mode = "rgmii-id";
275eb4ea085SAngus Ainslie (Purism)	phy-handle = <&ethphy0>;
276eb4ea085SAngus Ainslie (Purism)	fsl,magic-packet;
277eb4ea085SAngus Ainslie (Purism)	phy-supply = <&reg_3v3_p>;
278eb4ea085SAngus Ainslie (Purism)	status = "okay";
279eb4ea085SAngus Ainslie (Purism)
280eb4ea085SAngus Ainslie (Purism)	mdio {
281eb4ea085SAngus Ainslie (Purism)		#address-cells = <1>;
282eb4ea085SAngus Ainslie (Purism)		#size-cells = <0>;
283eb4ea085SAngus Ainslie (Purism)
284eb4ea085SAngus Ainslie (Purism)		ethphy0: ethernet-phy@1 {
285eb4ea085SAngus Ainslie (Purism)			compatible = "ethernet-phy-ieee802.3-c22";
286eb4ea085SAngus Ainslie (Purism)			reg = <1>;
287eb4ea085SAngus Ainslie (Purism)		};
288eb4ea085SAngus Ainslie (Purism)	};
289eb4ea085SAngus Ainslie (Purism)};
290eb4ea085SAngus Ainslie (Purism)
291eb4ea085SAngus Ainslie (Purism)&i2c1 {
292eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
293eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
294eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c1>;
295eb4ea085SAngus Ainslie (Purism)	status = "okay";
296eb4ea085SAngus Ainslie (Purism)
297eb4ea085SAngus Ainslie (Purism)	pmic: pmic@4b {
298eb4ea085SAngus Ainslie (Purism)		compatible = "rohm,bd71837";
299eb4ea085SAngus Ainslie (Purism)		reg = <0x4b>;
300eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
301eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_pmic>;
302eb4ea085SAngus Ainslie (Purism)		clocks = <&pmic_osc>;
303eb4ea085SAngus Ainslie (Purism)		clock-names = "osc";
304a4a3550eSKrzysztof Kozlowski		#clock-cells = <0>;
305eb4ea085SAngus Ainslie (Purism)		clock-output-names = "pmic_clk";
306eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio1>;
307d8fa4792SKrzysztof Kozlowski		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
308eb4ea085SAngus Ainslie (Purism)		rohm,reset-snvs-powered;
309eb4ea085SAngus Ainslie (Purism)
310eb4ea085SAngus Ainslie (Purism)		regulators {
311eb4ea085SAngus Ainslie (Purism)			buck1_reg: BUCK1 {
312eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck1";
313eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
314eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
315eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
316edb93de4SGuido Günther				regulator-always-on;
317eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
318eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <900000>;
319eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <850000>;
320eb4ea085SAngus Ainslie (Purism)				rohm,dvs-suspend-voltage = <800000>;
321eb4ea085SAngus Ainslie (Purism)			};
322eb4ea085SAngus Ainslie (Purism)
323eb4ea085SAngus Ainslie (Purism)			buck2_reg: BUCK2 {
324eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck2";
325eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
326eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
327eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
328eb4ea085SAngus Ainslie (Purism)				regulator-ramp-delay = <1250>;
329eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
330eb4ea085SAngus Ainslie (Purism)				rohm,dvs-idle-voltage = <900000>;
331eb4ea085SAngus Ainslie (Purism)			};
332eb4ea085SAngus Ainslie (Purism)
333eb4ea085SAngus Ainslie (Purism)			buck3_reg: BUCK3 {
334eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck3";
335eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
336eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
337eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
33876eceb0fSGuido Günther				rohm,dvs-run-voltage = <900000>;
339eb4ea085SAngus Ainslie (Purism)			};
340eb4ea085SAngus Ainslie (Purism)
341eb4ea085SAngus Ainslie (Purism)			buck4_reg: BUCK4 {
342eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck4";
343eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
344eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1300000>;
345eb4ea085SAngus Ainslie (Purism)				rohm,dvs-run-voltage = <1000000>;
346eb4ea085SAngus Ainslie (Purism)			};
347eb4ea085SAngus Ainslie (Purism)
348eb4ea085SAngus Ainslie (Purism)			buck5_reg: BUCK5 {
349eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck5";
350eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <700000>;
351eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1350000>;
352eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
353edb93de4SGuido Günther				regulator-always-on;
354eb4ea085SAngus Ainslie (Purism)			};
355eb4ea085SAngus Ainslie (Purism)
356eb4ea085SAngus Ainslie (Purism)			buck6_reg: BUCK6 {
357eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck6";
358eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
359eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
360eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
361edb93de4SGuido Günther				regulator-always-on;
362eb4ea085SAngus Ainslie (Purism)			};
363eb4ea085SAngus Ainslie (Purism)
364eb4ea085SAngus Ainslie (Purism)			buck7_reg: BUCK7 {
365eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck7";
366eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1605000>;
367eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1995000>;
368eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
369edb93de4SGuido Günther				regulator-always-on;
370eb4ea085SAngus Ainslie (Purism)			};
371eb4ea085SAngus Ainslie (Purism)
372eb4ea085SAngus Ainslie (Purism)			buck8_reg: BUCK8 {
373eb4ea085SAngus Ainslie (Purism)				regulator-name = "buck8";
374eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <800000>;
375eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1400000>;
376eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
377edb93de4SGuido Günther				regulator-always-on;
378eb4ea085SAngus Ainslie (Purism)			};
379eb4ea085SAngus Ainslie (Purism)
380eb4ea085SAngus Ainslie (Purism)			ldo1_reg: LDO1 {
381eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo1";
382eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <3000000>;
383eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
384eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
385eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
386eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
387eb4ea085SAngus Ainslie (Purism)			};
388eb4ea085SAngus Ainslie (Purism)
389eb4ea085SAngus Ainslie (Purism)			ldo2_reg: LDO2 {
390eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo2";
391eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
392eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <900000>;
393eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
394eb4ea085SAngus Ainslie (Purism)				/* leave on for snvs power button */
395eb4ea085SAngus Ainslie (Purism)				regulator-always-on;
396eb4ea085SAngus Ainslie (Purism)			};
397eb4ea085SAngus Ainslie (Purism)
398eb4ea085SAngus Ainslie (Purism)			ldo3_reg: LDO3 {
399eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo3";
400eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
401eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
402eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
403edb93de4SGuido Günther				regulator-always-on;
404eb4ea085SAngus Ainslie (Purism)			};
405eb4ea085SAngus Ainslie (Purism)
406eb4ea085SAngus Ainslie (Purism)			ldo4_reg: LDO4 {
407eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo4";
408eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
409eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
410eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
411edb93de4SGuido Günther				regulator-always-on;
412eb4ea085SAngus Ainslie (Purism)			};
413eb4ea085SAngus Ainslie (Purism)
414eb4ea085SAngus Ainslie (Purism)			ldo5_reg: LDO5 {
415eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo5";
416eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
417eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
418edb93de4SGuido Günther				regulator-always-on;
419eb4ea085SAngus Ainslie (Purism)			};
420eb4ea085SAngus Ainslie (Purism)
421eb4ea085SAngus Ainslie (Purism)			ldo6_reg: LDO6 {
422eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo6";
423eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <900000>;
424eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <1800000>;
425eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
426edb93de4SGuido Günther				regulator-always-on;
427eb4ea085SAngus Ainslie (Purism)			};
428eb4ea085SAngus Ainslie (Purism)
429eb4ea085SAngus Ainslie (Purism)			ldo7_reg: LDO7 {
430eb4ea085SAngus Ainslie (Purism)				regulator-name = "ldo7";
431eb4ea085SAngus Ainslie (Purism)				regulator-min-microvolt = <1800000>;
432eb4ea085SAngus Ainslie (Purism)				regulator-max-microvolt = <3300000>;
433eb4ea085SAngus Ainslie (Purism)				regulator-boot-on;
434edb93de4SGuido Günther				regulator-always-on;
435eb4ea085SAngus Ainslie (Purism)			};
436eb4ea085SAngus Ainslie (Purism)		};
437eb4ea085SAngus Ainslie (Purism)	};
438eb4ea085SAngus Ainslie (Purism)
4399251dad3SGuido Günther	typec_ptn5100: usb-typec@52 {
440eb4ea085SAngus Ainslie (Purism)		compatible = "nxp,ptn5110";
441eb4ea085SAngus Ainslie (Purism)		reg = <0x52>;
442eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
443eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_typec>;
444eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
445eb4ea085SAngus Ainslie (Purism)		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
446eb4ea085SAngus Ainslie (Purism)
447eb4ea085SAngus Ainslie (Purism)		connector {
448eb4ea085SAngus Ainslie (Purism)			compatible = "usb-c-connector";
449eb4ea085SAngus Ainslie (Purism)			label = "USB-C";
450eb4ea085SAngus Ainslie (Purism)			data-role = "dual";
451eb4ea085SAngus Ainslie (Purism)			power-role = "dual";
452eb4ea085SAngus Ainslie (Purism)			try-power-role = "sink";
453eb4ea085SAngus Ainslie (Purism)			source-pdos = <PDO_FIXED(5000, 2000,
454eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_USB_COMM |
455eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
456eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )>;
4575369d191SAngus Ainslie (Purism)			sink-pdos = <PDO_FIXED(5000, 3500, PDO_FIXED_USB_COMM |
458eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DUAL_ROLE |
459eb4ea085SAngus Ainslie (Purism)				PDO_FIXED_DATA_SWAP )
4605369d191SAngus Ainslie (Purism)			     PDO_VAR(5000, 5000, 3500)>;
461eb4ea085SAngus Ainslie (Purism)			op-sink-microwatt = <10000000>;
462eb4ea085SAngus Ainslie (Purism)
463eb4ea085SAngus Ainslie (Purism)			ports {
464eb4ea085SAngus Ainslie (Purism)				#address-cells = <1>;
465eb4ea085SAngus Ainslie (Purism)				#size-cells = <0>;
466eb4ea085SAngus Ainslie (Purism)
467eb4ea085SAngus Ainslie (Purism)				port@0 {
468eb4ea085SAngus Ainslie (Purism)					reg = <0>;
469eb4ea085SAngus Ainslie (Purism)
470eb4ea085SAngus Ainslie (Purism)					usb_con_hs: endpoint {
471eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_hs>;
472eb4ea085SAngus Ainslie (Purism)					};
473eb4ea085SAngus Ainslie (Purism)				};
474eb4ea085SAngus Ainslie (Purism)
475eb4ea085SAngus Ainslie (Purism)				port@1 {
476eb4ea085SAngus Ainslie (Purism)					reg = <1>;
477eb4ea085SAngus Ainslie (Purism)
478eb4ea085SAngus Ainslie (Purism)					usb_con_ss: endpoint {
479eb4ea085SAngus Ainslie (Purism)						remote-endpoint = <&typec_ss>;
480eb4ea085SAngus Ainslie (Purism)					};
481eb4ea085SAngus Ainslie (Purism)				};
482eb4ea085SAngus Ainslie (Purism)			};
483eb4ea085SAngus Ainslie (Purism)		};
484eb4ea085SAngus Ainslie (Purism)	};
485eb4ea085SAngus Ainslie (Purism)
486eb4ea085SAngus Ainslie (Purism)	rtc@68 {
487eb4ea085SAngus Ainslie (Purism)		compatible = "microcrystal,rv4162";
488eb4ea085SAngus Ainslie (Purism)		reg = <0x68>;
489eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
490eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_rtc>;
491eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio4>;
492eb4ea085SAngus Ainslie (Purism)		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
493eb4ea085SAngus Ainslie (Purism)	};
494eb4ea085SAngus Ainslie (Purism)
495eb4ea085SAngus Ainslie (Purism)	charger@6b { /* bq25896 */
496eb4ea085SAngus Ainslie (Purism)		compatible = "ti,bq25890";
497eb4ea085SAngus Ainslie (Purism)		reg = <0x6b>;
498eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
499eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_charger>;
500eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
501eb4ea085SAngus Ainslie (Purism)		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
502eb4ea085SAngus Ainslie (Purism)		ti,battery-regulation-voltage = <4192000>; /* 4.192V */
503eb4ea085SAngus Ainslie (Purism)		ti,charge-current = <1600000>; /* 1.6A */
504eb4ea085SAngus Ainslie (Purism)		ti,termination-current = <66000>;  /* 66mA */
505eb4ea085SAngus Ainslie (Purism)		ti,precharge-current = <130000>; /* 130mA */
506eb4ea085SAngus Ainslie (Purism)		ti,minimum-sys-voltage = <3000000>; /* 3V */
507eb4ea085SAngus Ainslie (Purism)		ti,boost-voltage = <5000000>; /* 5V */
508eb4ea085SAngus Ainslie (Purism)		ti,boost-max-current = <50000>; /* 50mA */
509eb4ea085SAngus Ainslie (Purism)	};
510eb4ea085SAngus Ainslie (Purism)};
511eb4ea085SAngus Ainslie (Purism)
512eb4ea085SAngus Ainslie (Purism)&i2c3 {
513eb4ea085SAngus Ainslie (Purism)	clock-frequency = <100000>;
514eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
515eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_i2c3>;
516eb4ea085SAngus Ainslie (Purism)	status = "okay";
517eb4ea085SAngus Ainslie (Purism)
518eb4ea085SAngus Ainslie (Purism)	magnetometer@1e	{
519eb4ea085SAngus Ainslie (Purism)		compatible = "st,lsm9ds1-magn";
520eb4ea085SAngus Ainslie (Purism)		reg = <0x1e>;
521eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
522eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_imu>;
523eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
524106f7b3bSAngus Ainslie (Purism)		interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
525eb4ea085SAngus Ainslie (Purism)		vdd-supply = <&reg_3v3_p>;
526eb4ea085SAngus Ainslie (Purism)		vddio-supply = <&reg_3v3_p>;
527eb4ea085SAngus Ainslie (Purism)	};
528eb4ea085SAngus Ainslie (Purism)
529c53f0166SAngus Ainslie (Purism)	sgtl5000: audio-codec@a {
530c53f0166SAngus Ainslie (Purism)		compatible = "fsl,sgtl5000";
531c53f0166SAngus Ainslie (Purism)		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
532c53f0166SAngus Ainslie (Purism)		assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
533c53f0166SAngus Ainslie (Purism)		assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
534c53f0166SAngus Ainslie (Purism)		assigned-clock-rates = <24576000>;
535c53f0166SAngus Ainslie (Purism)		#sound-dai-cells = <0>;
536c53f0166SAngus Ainslie (Purism)		reg = <0x0a>;
537c53f0166SAngus Ainslie (Purism)		VDDD-supply = <&reg_1v8_p>;
538c53f0166SAngus Ainslie (Purism)		VDDIO-supply = <&reg_3v3_p>;
539c53f0166SAngus Ainslie (Purism)		VDDA-supply = <&reg_3v3_p>;
540c53f0166SAngus Ainslie (Purism)	};
541c53f0166SAngus Ainslie (Purism)
542eb4ea085SAngus Ainslie (Purism)	touchscreen@5d {
543eb4ea085SAngus Ainslie (Purism)		compatible = "goodix,gt5688";
544eb4ea085SAngus Ainslie (Purism)		reg = <0x5d>;
545eb4ea085SAngus Ainslie (Purism)		pinctrl-names = "default";
546eb4ea085SAngus Ainslie (Purism)		pinctrl-0 = <&pinctrl_ts>;
547eb4ea085SAngus Ainslie (Purism)		interrupt-parent = <&gpio3>;
548eb4ea085SAngus Ainslie (Purism)		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
549eb4ea085SAngus Ainslie (Purism)		reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
550eb4ea085SAngus Ainslie (Purism)		irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
551eb4ea085SAngus Ainslie (Purism)		touchscreen-size-x = <720>;
552eb4ea085SAngus Ainslie (Purism)		touchscreen-size-y = <1440>;
553eb4ea085SAngus Ainslie (Purism)		AVDD28-supply = <&reg_2v8_p>;
554eb4ea085SAngus Ainslie (Purism)		VDDIO-supply = <&reg_1v8_p>;
555eb4ea085SAngus Ainslie (Purism)	};
556537c00e3SMartin Kepplinger
557ea38ca9aSGuido Günther	proximity-sensor@60 {
558ea38ca9aSGuido Günther		compatible = "vishay,vcnl4040";
559ea38ca9aSGuido Günther		reg = <0x60>;
560ea38ca9aSGuido Günther		pinctrl-0 = <&pinctrl_prox>;
561ea38ca9aSGuido Günther	};
562ea38ca9aSGuido Günther
563537c00e3SMartin Kepplinger	accel-gyro@6a {
564537c00e3SMartin Kepplinger		compatible = "st,lsm9ds1-imu";
565537c00e3SMartin Kepplinger		reg = <0x6a>;
566537c00e3SMartin Kepplinger		vdd-supply = <&reg_3v3_p>;
567537c00e3SMartin Kepplinger		vddio-supply = <&reg_3v3_p>;
568eef22bb1SMartin Kepplinger		mount-matrix =  "1",  "0",  "0",
569eef22bb1SMartin Kepplinger				"0",  "1",  "0",
570eef22bb1SMartin Kepplinger				"0",  "0", "-1";
571537c00e3SMartin Kepplinger	};
572eb4ea085SAngus Ainslie (Purism)};
573eb4ea085SAngus Ainslie (Purism)
574eb4ea085SAngus Ainslie (Purism)&iomuxc {
575eb4ea085SAngus Ainslie (Purism)	pinctrl_bl: blgrp {
576eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
577eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT	0x6 /* DSI_BL_PWM */
578eb4ea085SAngus Ainslie (Purism)		>;
579eb4ea085SAngus Ainslie (Purism)	};
580eb4ea085SAngus Ainslie (Purism)
581eb4ea085SAngus Ainslie (Purism)	pinctrl_bt: btgrp {
582eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
583eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11	0x16 /* nBT_DISABLE */
584eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7	0x10 /* BT_HOST_WAKE */
585eb4ea085SAngus Ainslie (Purism)		>;
586eb4ea085SAngus Ainslie (Purism)	};
587eb4ea085SAngus Ainslie (Purism)
588eb4ea085SAngus Ainslie (Purism)	pinctrl_charger: chargergrp {
589eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
590eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x80 /* CHRG_nINT */
591eb4ea085SAngus Ainslie (Purism)		>;
592eb4ea085SAngus Ainslie (Purism)	};
593eb4ea085SAngus Ainslie (Purism)
594eb4ea085SAngus Ainslie (Purism)	pinctrl_fec1: fec1grp {
595eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
596eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
597eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
598eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
599eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
600eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
601eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
602eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
603eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
604eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
605eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
606eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
607eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
608eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
609eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
610eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
611eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x1f
612eb4ea085SAngus Ainslie (Purism)		>;
613eb4ea085SAngus Ainslie (Purism)	};
614eb4ea085SAngus Ainslie (Purism)
615eb4ea085SAngus Ainslie (Purism)	pinctrl_ts: tsgrp {
616eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
617eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0		0x16  /* TOUCH INT */
618eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19  /* TOUCH RST */
619eb4ea085SAngus Ainslie (Purism)		>;
620eb4ea085SAngus Ainslie (Purism)	};
621eb4ea085SAngus Ainslie (Purism)
622eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_leds: gpioledgrp {
623eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
624eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16
625eb4ea085SAngus Ainslie (Purism)		>;
626eb4ea085SAngus Ainslie (Purism)	};
627eb4ea085SAngus Ainslie (Purism)
628eb4ea085SAngus Ainslie (Purism)	pinctrl_gpio_keys: gpiokeygrp {
629eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
630eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x16
631eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22	0x16
632eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x180  /* HP_DET */
6333ef506b3SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80   /* nWoWWAN */
634eb4ea085SAngus Ainslie (Purism)		>;
635eb4ea085SAngus Ainslie (Purism)	};
636eb4ea085SAngus Ainslie (Purism)
637eb4ea085SAngus Ainslie (Purism)	pinctrl_haptic: hapticgrp {
638eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
639eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4		0xc6   /* nHAPTIC */
640eb4ea085SAngus Ainslie (Purism)		>;
641eb4ea085SAngus Ainslie (Purism)	};
642eb4ea085SAngus Ainslie (Purism)
643eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c1: i2c1grp {
644eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
645eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000001f
646eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000001f
647eb4ea085SAngus Ainslie (Purism)		>;
648eb4ea085SAngus Ainslie (Purism)	};
649eb4ea085SAngus Ainslie (Purism)
650eb4ea085SAngus Ainslie (Purism)	pinctrl_i2c3: i2c3grp {
651eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
652eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x4000001f
653eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x4000001f
654eb4ea085SAngus Ainslie (Purism)		>;
655eb4ea085SAngus Ainslie (Purism)	};
656eb4ea085SAngus Ainslie (Purism)
657eb4ea085SAngus Ainslie (Purism)	pinctrl_imu: imugrp {
658eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
659eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x8  /* IMU_INT */
660eb4ea085SAngus Ainslie (Purism)		>;
661eb4ea085SAngus Ainslie (Purism)	};
662eb4ea085SAngus Ainslie (Purism)
663*15094482SGuido Günther	pinctrl_micsel: micselgrp {
664*15094482SGuido Günther		fsl,pins = <
665*15094482SGuido Günther			MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0xc6  /* MIC_SEL */
666*15094482SGuido Günther		>;
667*15094482SGuido Günther	};
668*15094482SGuido Günther
6696f46f7ffSGuido Günther	pinctrl_spkamp: spkamp {
6706f46f7ffSGuido Günther		fsl,pins = <
6716f46f7ffSGuido Günther			MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3		0x81  /* MUTE */
6726f46f7ffSGuido Günther		>;
6736f46f7ffSGuido Günther	};
6746f46f7ffSGuido Günther
675eb4ea085SAngus Ainslie (Purism)	pinctrl_pmic: pmicgrp {
676eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
677eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x80  /* PMIC intr */
678eb4ea085SAngus Ainslie (Purism)		>;
679eb4ea085SAngus Ainslie (Purism)	};
680eb4ea085SAngus Ainslie (Purism)
681ea38ca9aSGuido Günther	pinctrl_prox: proxgrp {
682ea38ca9aSGuido Günther		fsl,pins = <
683ea38ca9aSGuido Günther			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x80  /* prox intr */
684ea38ca9aSGuido Günther		>;
685ea38ca9aSGuido Günther	};
686ea38ca9aSGuido Günther
687eb4ea085SAngus Ainslie (Purism)	pinctrl_pwr_en: pwrengrp {
688eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
689eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x06
690eb4ea085SAngus Ainslie (Purism)		>;
691eb4ea085SAngus Ainslie (Purism)	};
692eb4ea085SAngus Ainslie (Purism)
693eb4ea085SAngus Ainslie (Purism)	pinctrl_rtc: rtcgrp {
694eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
695eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29	0x80  /* RTC intr */
696eb4ea085SAngus Ainslie (Purism)		>;
697eb4ea085SAngus Ainslie (Purism)	};
698eb4ea085SAngus Ainslie (Purism)
699c53f0166SAngus Ainslie (Purism)	pinctrl_sai2: sai2grp {
700c53f0166SAngus Ainslie (Purism)		fsl,pins = <
701c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
702c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
703c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
704c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6
705c53f0166SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
706c53f0166SAngus Ainslie (Purism)		>;
707c53f0166SAngus Ainslie (Purism)	};
708c53f0166SAngus Ainslie (Purism)
7097f7b7997SAngus Ainslie (Purism)	pinctrl_sai6: sai6grp {
7107f7b7997SAngus Ainslie (Purism)		fsl,pins = <
7117f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0	0xd6
7127f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC	0xd6
7137f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK     0xd6
7147f7b7997SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0	0xd6
7157f7b7997SAngus Ainslie (Purism)		>;
7167f7b7997SAngus Ainslie (Purism)	};
7177f7b7997SAngus Ainslie (Purism)
718eb4ea085SAngus Ainslie (Purism)	pinctrl_typec: typecgrp {
719eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
720eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x16
721eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x80
722eb4ea085SAngus Ainslie (Purism)		>;
723eb4ea085SAngus Ainslie (Purism)	};
724eb4ea085SAngus Ainslie (Purism)
725eb4ea085SAngus Ainslie (Purism)	pinctrl_uart1: uart1grp {
726eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
727eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
728eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
729eb4ea085SAngus Ainslie (Purism)		>;
730eb4ea085SAngus Ainslie (Purism)	};
731eb4ea085SAngus Ainslie (Purism)
732eb4ea085SAngus Ainslie (Purism)	pinctrl_uart2: uart2grp {
733eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
734eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
735eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
736eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
737eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
738eb4ea085SAngus Ainslie (Purism)		>;
739eb4ea085SAngus Ainslie (Purism)	};
740eb4ea085SAngus Ainslie (Purism)
741eb4ea085SAngus Ainslie (Purism)	pinctrl_uart3: uart3grp {
742eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
743eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
744eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
745eb4ea085SAngus Ainslie (Purism)		>;
746eb4ea085SAngus Ainslie (Purism)	};
747eb4ea085SAngus Ainslie (Purism)
748eb4ea085SAngus Ainslie (Purism)	pinctrl_uart4: uart4grp {
749eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
750eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
751eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
752eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x49
753eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49
754eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x49
755eb4ea085SAngus Ainslie (Purism)		>;
756eb4ea085SAngus Ainslie (Purism)	};
757eb4ea085SAngus Ainslie (Purism)
758eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc1: usdhc1grp {
759eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
760eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
761eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
762eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
763eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
764eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
765eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
766eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
767eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
768eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
769eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
770eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
771eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
772eb4ea085SAngus Ainslie (Purism)		>;
773eb4ea085SAngus Ainslie (Purism)	};
774eb4ea085SAngus Ainslie (Purism)
775ae560c43SKrzysztof Kozlowski	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
776eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
777eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
778eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
779eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
780eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
781eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
782eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
783eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
784eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
785eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
786eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
787eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
788eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
789eb4ea085SAngus Ainslie (Purism)		>;
790eb4ea085SAngus Ainslie (Purism)	};
791eb4ea085SAngus Ainslie (Purism)
792ae560c43SKrzysztof Kozlowski	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
793eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
794eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
795eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
796eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
797eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
798eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
799eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
800eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
801eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
802eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
803eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
804eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
805eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
806eb4ea085SAngus Ainslie (Purism)		>;
807eb4ea085SAngus Ainslie (Purism)	};
808eb4ea085SAngus Ainslie (Purism)
809ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_pwr: usdhc2pwrgrp {
810eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
811eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
812eb4ea085SAngus Ainslie (Purism)		>;
813eb4ea085SAngus Ainslie (Purism)	};
814eb4ea085SAngus Ainslie (Purism)
815ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
816eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
817eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */
818eb4ea085SAngus Ainslie (Purism)		>;
819eb4ea085SAngus Ainslie (Purism)	};
820eb4ea085SAngus Ainslie (Purism)
821eb4ea085SAngus Ainslie (Purism)	pinctrl_usdhc2: usdhc2grp {
822eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
823eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
824eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
825eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
826eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
827eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
828eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
829eb4ea085SAngus Ainslie (Purism)		>;
830eb4ea085SAngus Ainslie (Purism)	};
831eb4ea085SAngus Ainslie (Purism)
832ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
833eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
834eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d
835eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd
836eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcd
837eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcd
838eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcd
839eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcd
840eb4ea085SAngus Ainslie (Purism)		>;
841eb4ea085SAngus Ainslie (Purism)	};
842eb4ea085SAngus Ainslie (Purism)
843ae560c43SKrzysztof Kozlowski	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
844eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
845eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f
846eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf
847eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcf
848eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcf
849eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcf
850eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcf
851eb4ea085SAngus Ainslie (Purism)		>;
852eb4ea085SAngus Ainslie (Purism)	};
853eb4ea085SAngus Ainslie (Purism)
854eb4ea085SAngus Ainslie (Purism)	pinctrl_wdog: wdoggrp {
855eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
856eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
857eb4ea085SAngus Ainslie (Purism)		>;
858eb4ea085SAngus Ainslie (Purism)	};
859eb4ea085SAngus Ainslie (Purism)
860eb4ea085SAngus Ainslie (Purism)	pinctrl_wifi_pwr_en: wifipwrengrp {
861eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
862eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5         0x06
863eb4ea085SAngus Ainslie (Purism)		>;
864eb4ea085SAngus Ainslie (Purism)	};
865eb4ea085SAngus Ainslie (Purism)
866eb4ea085SAngus Ainslie (Purism)	pinctrl_wwan: wwangrp {
867eb4ea085SAngus Ainslie (Purism)		fsl,pins = <
868eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x09 /* nWWAN_DISABLE */
869eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80 /* nWoWWAN */
870eb4ea085SAngus Ainslie (Purism)			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9	0x19 /* WWAN_RESET */
871eb4ea085SAngus Ainslie (Purism)		>;
872eb4ea085SAngus Ainslie (Purism)	};
873eb4ea085SAngus Ainslie (Purism)};
874eb4ea085SAngus Ainslie (Purism)
875e8151ef3SGuido Günther&lcdif {
876e8151ef3SGuido Günther	status = "okay";
877e8151ef3SGuido Günther};
878e8151ef3SGuido Günther
879e8151ef3SGuido Günther&mipi_dsi {
880e8151ef3SGuido Günther	status = "okay";
881e8151ef3SGuido Günther	#address-cells = <1>;
882e8151ef3SGuido Günther	#size-cells = <0>;
883e8151ef3SGuido Günther
884e8151ef3SGuido Günther	panel@0 {
885e8151ef3SGuido Günther		compatible = "rocktech,jh057n00900";
886e8151ef3SGuido Günther		reg = <0>;
887e8151ef3SGuido Günther		backlight = <&backlight_dsi>;
888e8151ef3SGuido Günther		reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
889e8151ef3SGuido Günther		iovcc-supply = <&reg_1v8_p>;
890e8151ef3SGuido Günther		vcc-supply = <&reg_2v8_p>;
891e8151ef3SGuido Günther		port {
892e8151ef3SGuido Günther			panel_in: endpoint {
893e8151ef3SGuido Günther				remote-endpoint = <&mipi_dsi_out>;
894e8151ef3SGuido Günther			};
895e8151ef3SGuido Günther		};
896e8151ef3SGuido Günther	};
897e8151ef3SGuido Günther
898e8151ef3SGuido Günther	ports {
899e8151ef3SGuido Günther		port@1 {
900e8151ef3SGuido Günther			reg = <1>;
901e8151ef3SGuido Günther			mipi_dsi_out: endpoint {
902e8151ef3SGuido Günther				remote-endpoint = <&panel_in>;
903e8151ef3SGuido Günther			};
904e8151ef3SGuido Günther		};
905e8151ef3SGuido Günther	};
906e8151ef3SGuido Günther};
907e8151ef3SGuido Günther
908eb4ea085SAngus Ainslie (Purism)&pgc_gpu {
909eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck3_reg>;
910eb4ea085SAngus Ainslie (Purism)};
911eb4ea085SAngus Ainslie (Purism)
912eb4ea085SAngus Ainslie (Purism)&pgc_vpu {
913eb4ea085SAngus Ainslie (Purism)	power-supply = <&buck4_reg>;
914eb4ea085SAngus Ainslie (Purism)};
915eb4ea085SAngus Ainslie (Purism)
916eb4ea085SAngus Ainslie (Purism)&pwm1 {
917eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
918eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_bl>;
919eb4ea085SAngus Ainslie (Purism)	status = "okay";
920eb4ea085SAngus Ainslie (Purism)};
921eb4ea085SAngus Ainslie (Purism)
92201407158SAngus Ainslie (Purism)&snvs_pwrkey {
92301407158SAngus Ainslie (Purism)	status = "okay";
92401407158SAngus Ainslie (Purism)};
925eb4ea085SAngus Ainslie (Purism)
926ff38c1ddSGuido Günther&snvs_rtc {
927ff38c1ddSGuido Günther	status = "disabled";
928ff38c1ddSGuido Günther};
929ff38c1ddSGuido Günther
930c53f0166SAngus Ainslie (Purism)&sai2 {
931c53f0166SAngus Ainslie (Purism)	pinctrl-names = "default";
932c53f0166SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai2>;
933c53f0166SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
934c53f0166SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
935c53f0166SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
936c53f0166SAngus Ainslie (Purism)	status = "okay";
937c53f0166SAngus Ainslie (Purism)};
938c53f0166SAngus Ainslie (Purism)
9397f7b7997SAngus Ainslie (Purism)&sai6 {
9407f7b7997SAngus Ainslie (Purism)	pinctrl-names = "default";
9417f7b7997SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_sai6>;
9427f7b7997SAngus Ainslie (Purism)	assigned-clocks = <&clk IMX8MQ_CLK_SAI6>;
9437f7b7997SAngus Ainslie (Purism)	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
9447f7b7997SAngus Ainslie (Purism)	assigned-clock-rates = <24576000>;
9457f7b7997SAngus Ainslie (Purism)	fsl,sai-synchronous-rx;
9467f7b7997SAngus Ainslie (Purism)	status = "okay";
9477f7b7997SAngus Ainslie (Purism)};
9487f7b7997SAngus Ainslie (Purism)
949eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */
950eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
951eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart1>;
952eb4ea085SAngus Ainslie (Purism)	status = "okay";
953eb4ea085SAngus Ainslie (Purism)};
954eb4ea085SAngus Ainslie (Purism)
955eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */
956eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
957eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart3>;
958eb4ea085SAngus Ainslie (Purism)	status = "okay";
959eb4ea085SAngus Ainslie (Purism)};
960eb4ea085SAngus Ainslie (Purism)
961eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */
962eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
963eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
964eb4ea085SAngus Ainslie (Purism)	uart-has-rtscts;
965eb4ea085SAngus Ainslie (Purism)	status = "okay";
966eb4ea085SAngus Ainslie (Purism)};
967eb4ea085SAngus Ainslie (Purism)
968eb4ea085SAngus Ainslie (Purism)&usb3_phy0 {
969dde061b8SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
970eb4ea085SAngus Ainslie (Purism)	status = "okay";
971eb4ea085SAngus Ainslie (Purism)};
972eb4ea085SAngus Ainslie (Purism)
973eb4ea085SAngus Ainslie (Purism)&usb3_phy1 {
974eb4ea085SAngus Ainslie (Purism)	vbus-supply = <&reg_5v_p>;
975eb4ea085SAngus Ainslie (Purism)	status = "okay";
976eb4ea085SAngus Ainslie (Purism)};
977eb4ea085SAngus Ainslie (Purism)
978eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 {
979eb4ea085SAngus Ainslie (Purism)	#address-cells = <1>;
980eb4ea085SAngus Ainslie (Purism)	#size-cells = <0>;
981eb4ea085SAngus Ainslie (Purism)	dr_mode = "otg";
982eb4ea085SAngus Ainslie (Purism)	status = "okay";
983eb4ea085SAngus Ainslie (Purism)
984eb4ea085SAngus Ainslie (Purism)	port@0 {
985eb4ea085SAngus Ainslie (Purism)		reg = <0>;
986eb4ea085SAngus Ainslie (Purism)
987eb4ea085SAngus Ainslie (Purism)		typec_hs: endpoint {
988eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_hs>;
989eb4ea085SAngus Ainslie (Purism)		};
990eb4ea085SAngus Ainslie (Purism)	};
991eb4ea085SAngus Ainslie (Purism)
992eb4ea085SAngus Ainslie (Purism)	port@1 {
993eb4ea085SAngus Ainslie (Purism)		reg = <1>;
994eb4ea085SAngus Ainslie (Purism)
995eb4ea085SAngus Ainslie (Purism)		typec_ss: endpoint {
996eb4ea085SAngus Ainslie (Purism)			remote-endpoint = <&usb_con_ss>;
997eb4ea085SAngus Ainslie (Purism)		};
998eb4ea085SAngus Ainslie (Purism)	};
999eb4ea085SAngus Ainslie (Purism)};
1000eb4ea085SAngus Ainslie (Purism)
1001eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 {
1002eb4ea085SAngus Ainslie (Purism)	dr_mode = "host";
1003eb4ea085SAngus Ainslie (Purism)	status = "okay";
1004eb4ea085SAngus Ainslie (Purism)};
1005eb4ea085SAngus Ainslie (Purism)
1006eb4ea085SAngus Ainslie (Purism)&usdhc1 {
1007e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
1008e045f044SAnson Huang	assigned-clock-rates = <400000000>;
1009eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
1010eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc1>;
1011eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
1012eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
1013eb4ea085SAngus Ainslie (Purism)	bus-width = <8>;
1014eb4ea085SAngus Ainslie (Purism)	non-removable;
1015eb4ea085SAngus Ainslie (Purism)	status = "okay";
1016eb4ea085SAngus Ainslie (Purism)};
1017eb4ea085SAngus Ainslie (Purism)
1018eb4ea085SAngus Ainslie (Purism)&usdhc2 {
1019e045f044SAnson Huang	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
1020e045f044SAnson Huang	assigned-clock-rates = <200000000>;
1021eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default", "state_100mhz", "state_200mhz";
1022eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_usdhc2>;
1023eb4ea085SAngus Ainslie (Purism)	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
1024eb4ea085SAngus Ainslie (Purism)	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
1025eb4ea085SAngus Ainslie (Purism)	bus-width = <4>;
1026eb4ea085SAngus Ainslie (Purism)	vmmc-supply = <&reg_usdhc2_vmmc>;
1027eb4ea085SAngus Ainslie (Purism)	power-supply = <&wifi_pwr_en>;
10289dae8563SAngus Ainslie (Purism)	broken-cd;
1029eb4ea085SAngus Ainslie (Purism)	disable-wp;
1030eb4ea085SAngus Ainslie (Purism)	cap-sdio-irq;
1031eb4ea085SAngus Ainslie (Purism)	keep-power-in-suspend;
1032eb4ea085SAngus Ainslie (Purism)	wakeup-source;
1033eb4ea085SAngus Ainslie (Purism)	status = "okay";
1034eb4ea085SAngus Ainslie (Purism)};
1035eb4ea085SAngus Ainslie (Purism)
1036eb4ea085SAngus Ainslie (Purism)&wdog1 {
1037eb4ea085SAngus Ainslie (Purism)	pinctrl-names = "default";
1038eb4ea085SAngus Ainslie (Purism)	pinctrl-0 = <&pinctrl_wdog>;
1039eb4ea085SAngus Ainslie (Purism)	fsl,ext-reset-output;
1040eb4ea085SAngus Ainslie (Purism)	status = "okay";
1041eb4ea085SAngus Ainslie (Purism)};
1042