1eb4ea085SAngus Ainslie (Purism)// SPDX-License-Identifier: GPL-2.0+ 2eb4ea085SAngus Ainslie (Purism)/* 3eb4ea085SAngus Ainslie (Purism) * Copyright 2018-2019 Purism SPC 4eb4ea085SAngus Ainslie (Purism) */ 5eb4ea085SAngus Ainslie (Purism) 6eb4ea085SAngus Ainslie (Purism)/dts-v1/; 7eb4ea085SAngus Ainslie (Purism) 8eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/input/input.h" 9d8fa4792SKrzysztof Kozlowski#include <dt-bindings/interrupt-controller/irq.h> 10822b29e3SGuido Günther#include <dt-bindings/leds/common.h> 11eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/pwm/pwm.h" 12eb4ea085SAngus Ainslie (Purism)#include "dt-bindings/usb/pd.h" 13eb4ea085SAngus Ainslie (Purism)#include "imx8mq.dtsi" 14eb4ea085SAngus Ainslie (Purism) 15eb4ea085SAngus Ainslie (Purism)/ { 16eb4ea085SAngus Ainslie (Purism) model = "Purism Librem 5 devkit"; 17eb4ea085SAngus Ainslie (Purism) compatible = "purism,librem5-devkit", "fsl,imx8mq"; 18eb4ea085SAngus Ainslie (Purism) 19eb4ea085SAngus Ainslie (Purism) backlight_dsi: backlight-dsi { 20eb4ea085SAngus Ainslie (Purism) compatible = "pwm-backlight"; 21eb4ea085SAngus Ainslie (Purism) /* 200 Hz for the PAM2841 */ 2215ca3f00SMarkus Niebel pwms = <&pwm1 0 5000000 0>; 23eb4ea085SAngus Ainslie (Purism) brightness-levels = <0 100>; 24eb4ea085SAngus Ainslie (Purism) num-interpolated-steps = <100>; 25eb4ea085SAngus Ainslie (Purism) /* Default brightness level (index into the array defined by */ 26eb4ea085SAngus Ainslie (Purism) /* the "brightness-levels" property) */ 27eb4ea085SAngus Ainslie (Purism) default-brightness-level = <0>; 28eb4ea085SAngus Ainslie (Purism) power-supply = <®_22v4_p>; 29eb4ea085SAngus Ainslie (Purism) }; 30eb4ea085SAngus Ainslie (Purism) 31eb4ea085SAngus Ainslie (Purism) chosen { 32eb4ea085SAngus Ainslie (Purism) stdout-path = &uart1; 33eb4ea085SAngus Ainslie (Purism) }; 34eb4ea085SAngus Ainslie (Purism) 35eb4ea085SAngus Ainslie (Purism) gpio-keys { 36eb4ea085SAngus Ainslie (Purism) compatible = "gpio-keys"; 37eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 38eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_gpio_keys>; 39eb4ea085SAngus Ainslie (Purism) 40b803d15eSKrzysztof Kozlowski button-1 { 41eb4ea085SAngus Ainslie (Purism) label = "VOL_UP"; 42eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; 43eb4ea085SAngus Ainslie (Purism) wakeup-source; 44eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEUP>; 45eb4ea085SAngus Ainslie (Purism) }; 46eb4ea085SAngus Ainslie (Purism) 47b803d15eSKrzysztof Kozlowski button-2 { 48eb4ea085SAngus Ainslie (Purism) label = "VOL_DOWN"; 49eb4ea085SAngus Ainslie (Purism) gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 50eb4ea085SAngus Ainslie (Purism) wakeup-source; 51eb4ea085SAngus Ainslie (Purism) linux,code = <KEY_VOLUMEDOWN>; 52eb4ea085SAngus Ainslie (Purism) }; 53eb4ea085SAngus Ainslie (Purism) 54b803d15eSKrzysztof Kozlowski button-3 { 553ef506b3SAngus Ainslie (Purism) label = "WWAN_WAKE"; 563ef506b3SAngus Ainslie (Purism) gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; 573ef506b3SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 58d8fa4792SKrzysztof Kozlowski interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 593ef506b3SAngus Ainslie (Purism) wakeup-source; 603ef506b3SAngus Ainslie (Purism) linux,code = <KEY_PHONE>; 613ef506b3SAngus Ainslie (Purism) }; 62eb4ea085SAngus Ainslie (Purism) }; 63eb4ea085SAngus Ainslie (Purism) 64eb4ea085SAngus Ainslie (Purism) leds { 6529ecef8eSGuido Günther compatible = "pwm-leds"; 66eb4ea085SAngus Ainslie (Purism) 67ad214526SKrzysztof Kozlowski led-1 { 68822b29e3SGuido Günther function = LED_FUNCTION_STATUS; 69822b29e3SGuido Günther color = <LED_COLOR_ID_RED>; 7029ecef8eSGuido Günther max-brightness = <248>; 7129ecef8eSGuido Günther pwms = <&pwm2 0 50000 0>; 72eb4ea085SAngus Ainslie (Purism) }; 73eb4ea085SAngus Ainslie (Purism) }; 74eb4ea085SAngus Ainslie (Purism) 75eb4ea085SAngus Ainslie (Purism) pmic_osc: clock-pmic { 76eb4ea085SAngus Ainslie (Purism) compatible = "fixed-clock"; 77eb4ea085SAngus Ainslie (Purism) #clock-cells = <0>; 78eb4ea085SAngus Ainslie (Purism) clock-frequency = <32768>; 79eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_osc"; 80eb4ea085SAngus Ainslie (Purism) }; 81eb4ea085SAngus Ainslie (Purism) 82eb4ea085SAngus Ainslie (Purism) reg_1v8_p: regulator-1v8-p { 83eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 84eb4ea085SAngus Ainslie (Purism) regulator-name = "1v8_p"; 85eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 86eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 87eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 88eb4ea085SAngus Ainslie (Purism) }; 89eb4ea085SAngus Ainslie (Purism) 90eb4ea085SAngus Ainslie (Purism) reg_2v8_p: regulator-2v8-p { 91eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 92eb4ea085SAngus Ainslie (Purism) regulator-name = "2v8_p"; 93eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <2800000>; 94eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <2800000>; 95eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 96eb4ea085SAngus Ainslie (Purism) }; 97eb4ea085SAngus Ainslie (Purism) 98eb4ea085SAngus Ainslie (Purism) reg_3v3_p: regulator-3v3-p { 99eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 100eb4ea085SAngus Ainslie (Purism) regulator-name = "3v3_p"; 101eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 102eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 103eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 104eb4ea085SAngus Ainslie (Purism) 105eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 106eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 107eb4ea085SAngus Ainslie (Purism) }; 108eb4ea085SAngus Ainslie (Purism) }; 109eb4ea085SAngus Ainslie (Purism) 110eb4ea085SAngus Ainslie (Purism) reg_5v_p: regulator-5v-p { 111eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 112eb4ea085SAngus Ainslie (Purism) regulator-name = "5v_p"; 113eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <5000000>; 114eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <5000000>; 115eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 116eb4ea085SAngus Ainslie (Purism) 117eb4ea085SAngus Ainslie (Purism) regulator-state-mem { 118eb4ea085SAngus Ainslie (Purism) regulator-on-in-suspend; 119eb4ea085SAngus Ainslie (Purism) }; 120eb4ea085SAngus Ainslie (Purism) }; 121eb4ea085SAngus Ainslie (Purism) 122eb4ea085SAngus Ainslie (Purism) reg_22v4_p: regulator-22v4-p { 123eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 124eb4ea085SAngus Ainslie (Purism) regulator-name = "22v4_P"; 125eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <22400000>; 126eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <22400000>; 127eb4ea085SAngus Ainslie (Purism) vin-supply = <®_pwr_en>; 128eb4ea085SAngus Ainslie (Purism) }; 129eb4ea085SAngus Ainslie (Purism) 130eb4ea085SAngus Ainslie (Purism) reg_pwr_en: regulator-pwr-en { 131eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 132eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 133eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pwr_en>; 134eb4ea085SAngus Ainslie (Purism) regulator-name = "PWR_EN"; 135eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 136eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 137eb4ea085SAngus Ainslie (Purism) gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 138eb4ea085SAngus Ainslie (Purism) enable-active-high; 139eb4ea085SAngus Ainslie (Purism) regulator-always-on; 140eb4ea085SAngus Ainslie (Purism) }; 141eb4ea085SAngus Ainslie (Purism) 1427f7b7997SAngus Ainslie (Purism) wwan_codec: sound-wwan-codec { 1437f7b7997SAngus Ainslie (Purism) compatible = "option,gtm601"; 1447f7b7997SAngus Ainslie (Purism) #sound-dai-cells = <0>; 1457f7b7997SAngus Ainslie (Purism) }; 1467f7b7997SAngus Ainslie (Purism) 14715094482SGuido Günther mic_mux: mic-mux { 14815094482SGuido Günther compatible = "simple-audio-mux"; 14915094482SGuido Günther pinctrl-names = "default"; 15015094482SGuido Günther pinctrl-0 = <&pinctrl_micsel>; 15115094482SGuido Günther mux-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; 15215094482SGuido Günther sound-name-prefix = "Mic Mux"; 15315094482SGuido Günther }; 15415094482SGuido Günther 155c53f0166SAngus Ainslie (Purism) sound { 156c53f0166SAngus Ainslie (Purism) compatible = "simple-audio-card"; 157d779f4c9SGuido Günther pinctrl-names = "default"; 158d779f4c9SGuido Günther pinctrl-0 = <&pinctrl_hpdet>; 15915094482SGuido Günther simple-audio-card,aux-devs = <&speaker_amp>, <&mic_mux>; 1605b65f39dSGuido Günther simple-audio-card,name = "Librem 5 Devkit"; 161c53f0166SAngus Ainslie (Purism) simple-audio-card,format = "i2s"; 162c53f0166SAngus Ainslie (Purism) simple-audio-card,widgets = 16315094482SGuido Günther "Microphone", "Builtin Microphone", 16415094482SGuido Günther "Microphone", "Headset Microphone", 165d779f4c9SGuido Günther "Headphone", "Headphones", 16639a346d9SGuido Günther "Speaker", "Builtin Speaker"; 167c53f0166SAngus Ainslie (Purism) simple-audio-card,routing = 16815094482SGuido Günther "MIC_IN", "Mic Mux OUT", 16915094482SGuido Günther "Mic Mux IN1", "Headset Microphone", 17015094482SGuido Günther "Mic Mux IN2", "Builtin Microphone", 17115094482SGuido Günther "Mic Mux OUT", "Mic Bias", 172d779f4c9SGuido Günther "Headphones", "HP_OUT", 1736f46f7ffSGuido Günther "Builtin Speaker", "Speaker Amp OUTR", 1746f46f7ffSGuido Günther "Speaker Amp INR", "LINE_OUT"; 175d779f4c9SGuido Günther simple-audio-card,hp-det-gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; 176c53f0166SAngus Ainslie (Purism) 177c53f0166SAngus Ainslie (Purism) simple-audio-card,cpu { 178c53f0166SAngus Ainslie (Purism) sound-dai = <&sai2>; 179c53f0166SAngus Ainslie (Purism) }; 180c53f0166SAngus Ainslie (Purism) 181c53f0166SAngus Ainslie (Purism) simple-audio-card,codec { 182c53f0166SAngus Ainslie (Purism) sound-dai = <&sgtl5000>; 183c53f0166SAngus Ainslie (Purism) clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 184c53f0166SAngus Ainslie (Purism) frame-master; 185c53f0166SAngus Ainslie (Purism) bitclock-master; 186c53f0166SAngus Ainslie (Purism) }; 187c53f0166SAngus Ainslie (Purism) }; 188c53f0166SAngus Ainslie (Purism) 1897f7b7997SAngus Ainslie (Purism) sound-wwan { 1907f7b7997SAngus Ainslie (Purism) compatible = "simple-audio-card"; 1917f7b7997SAngus Ainslie (Purism) simple-audio-card,name = "SIMCom SIM7100"; 1927f7b7997SAngus Ainslie (Purism) simple-audio-card,format = "dsp_a"; 1937f7b7997SAngus Ainslie (Purism) 1947f7b7997SAngus Ainslie (Purism) simple-audio-card,cpu { 1957f7b7997SAngus Ainslie (Purism) sound-dai = <&sai6>; 1967f7b7997SAngus Ainslie (Purism) }; 1977f7b7997SAngus Ainslie (Purism) 1987f7b7997SAngus Ainslie (Purism) telephony_link_master: simple-audio-card,codec { 1997f7b7997SAngus Ainslie (Purism) sound-dai = <&wwan_codec>; 2007f7b7997SAngus Ainslie (Purism) frame-master; 2017f7b7997SAngus Ainslie (Purism) bitclock-master; 2027f7b7997SAngus Ainslie (Purism) }; 2037f7b7997SAngus Ainslie (Purism) }; 2047f7b7997SAngus Ainslie (Purism) 2056f46f7ffSGuido Günther speaker_amp: speaker-amp { 2066f46f7ffSGuido Günther compatible = "simple-audio-amplifier"; 2076f46f7ffSGuido Günther pinctrl-names = "default"; 2086f46f7ffSGuido Günther pinctrl-0 = <&pinctrl_spkamp>; 2096f46f7ffSGuido Günther VCC-supply = <®_3v3_p>; 2106f46f7ffSGuido Günther sound-name-prefix = "Speaker Amp"; 2116f46f7ffSGuido Günther enable-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 2126f46f7ffSGuido Günther }; 2136f46f7ffSGuido Günther 214eb4ea085SAngus Ainslie (Purism) vibrator { 215eb4ea085SAngus Ainslie (Purism) compatible = "gpio-vibrator"; 216eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 217eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_haptic>; 218eb4ea085SAngus Ainslie (Purism) enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; 219eb4ea085SAngus Ainslie (Purism) vcc-supply = <®_3v3_p>; 220eb4ea085SAngus Ainslie (Purism) }; 221eb4ea085SAngus Ainslie (Purism) 222eb4ea085SAngus Ainslie (Purism) wifi_pwr_en: regulator-wifi-en { 223eb4ea085SAngus Ainslie (Purism) compatible = "regulator-fixed"; 224eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 225eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wifi_pwr_en>; 226eb4ea085SAngus Ainslie (Purism) regulator-name = "WIFI_EN"; 227eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3300000>; 228eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 229eb4ea085SAngus Ainslie (Purism) gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 230eb4ea085SAngus Ainslie (Purism) enable-active-high; 231eb4ea085SAngus Ainslie (Purism) regulator-always-on; 232eb4ea085SAngus Ainslie (Purism) }; 233*60ac8a77SGuido Günther 234*60ac8a77SGuido Günther wifi_pwr_seq: pwrseq { 235*60ac8a77SGuido Günther pinctrl-names = "default"; 236*60ac8a77SGuido Günther pinctrl-0 = <&pinctrl_usdhc2_rst>; 237*60ac8a77SGuido Günther compatible = "mmc-pwrseq-simple"; 238*60ac8a77SGuido Günther reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; 239*60ac8a77SGuido Günther }; 240eb4ea085SAngus Ainslie (Purism)}; 241eb4ea085SAngus Ainslie (Purism) 242a2e47ba2SAngus Ainslie (Purism)&A53_0 { 243a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 244a2e47ba2SAngus Ainslie (Purism)}; 245a2e47ba2SAngus Ainslie (Purism) 246a2e47ba2SAngus Ainslie (Purism)&A53_1 { 247a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 248a2e47ba2SAngus Ainslie (Purism)}; 249a2e47ba2SAngus Ainslie (Purism) 250a2e47ba2SAngus Ainslie (Purism)&A53_2 { 251a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 252a2e47ba2SAngus Ainslie (Purism)}; 253a2e47ba2SAngus Ainslie (Purism) 254a2e47ba2SAngus Ainslie (Purism)&A53_3 { 255a2e47ba2SAngus Ainslie (Purism) cpu-supply = <&buck2_reg>; 256a2e47ba2SAngus Ainslie (Purism)}; 257a2e47ba2SAngus Ainslie (Purism) 2589d9005a5SGuido Günther&dphy { 2599d9005a5SGuido Günther status = "okay"; 2609d9005a5SGuido Günther}; 2619d9005a5SGuido Günther 262eb4ea085SAngus Ainslie (Purism)&fec1 { 263eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 264eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_fec1>; 265eb4ea085SAngus Ainslie (Purism) phy-mode = "rgmii-id"; 266eb4ea085SAngus Ainslie (Purism) phy-handle = <ðphy0>; 267eb4ea085SAngus Ainslie (Purism) fsl,magic-packet; 268eb4ea085SAngus Ainslie (Purism) phy-supply = <®_3v3_p>; 269eb4ea085SAngus Ainslie (Purism) status = "okay"; 270eb4ea085SAngus Ainslie (Purism) 271eb4ea085SAngus Ainslie (Purism) mdio { 272eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 273eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 274eb4ea085SAngus Ainslie (Purism) 275eb4ea085SAngus Ainslie (Purism) ethphy0: ethernet-phy@1 { 276eb4ea085SAngus Ainslie (Purism) compatible = "ethernet-phy-ieee802.3-c22"; 277eb4ea085SAngus Ainslie (Purism) reg = <1>; 278eb4ea085SAngus Ainslie (Purism) }; 279eb4ea085SAngus Ainslie (Purism) }; 280eb4ea085SAngus Ainslie (Purism)}; 281eb4ea085SAngus Ainslie (Purism) 282eb4ea085SAngus Ainslie (Purism)&i2c1 { 283eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 284eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 285eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c1>; 286eb4ea085SAngus Ainslie (Purism) status = "okay"; 287eb4ea085SAngus Ainslie (Purism) 288eb4ea085SAngus Ainslie (Purism) pmic: pmic@4b { 289eb4ea085SAngus Ainslie (Purism) compatible = "rohm,bd71837"; 290eb4ea085SAngus Ainslie (Purism) reg = <0x4b>; 291eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 292eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_pmic>; 293eb4ea085SAngus Ainslie (Purism) clocks = <&pmic_osc>; 294eb4ea085SAngus Ainslie (Purism) clock-names = "osc"; 295a4a3550eSKrzysztof Kozlowski #clock-cells = <0>; 296eb4ea085SAngus Ainslie (Purism) clock-output-names = "pmic_clk"; 297eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio1>; 298d8fa4792SKrzysztof Kozlowski interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 299eb4ea085SAngus Ainslie (Purism) rohm,reset-snvs-powered; 300eb4ea085SAngus Ainslie (Purism) 301eb4ea085SAngus Ainslie (Purism) regulators { 302eb4ea085SAngus Ainslie (Purism) buck1_reg: BUCK1 { 303eb4ea085SAngus Ainslie (Purism) regulator-name = "buck1"; 304eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 305eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 306eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 307edb93de4SGuido Günther regulator-always-on; 308eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 309eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <900000>; 310eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <850000>; 311eb4ea085SAngus Ainslie (Purism) rohm,dvs-suspend-voltage = <800000>; 312eb4ea085SAngus Ainslie (Purism) }; 313eb4ea085SAngus Ainslie (Purism) 314eb4ea085SAngus Ainslie (Purism) buck2_reg: BUCK2 { 315eb4ea085SAngus Ainslie (Purism) regulator-name = "buck2"; 316eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 317eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 318eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 319eb4ea085SAngus Ainslie (Purism) regulator-ramp-delay = <1250>; 320eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 321eb4ea085SAngus Ainslie (Purism) rohm,dvs-idle-voltage = <900000>; 32274cec60cSGuido Günther regulator-always-on; 323eb4ea085SAngus Ainslie (Purism) }; 324eb4ea085SAngus Ainslie (Purism) 325eb4ea085SAngus Ainslie (Purism) buck3_reg: BUCK3 { 326eb4ea085SAngus Ainslie (Purism) regulator-name = "buck3"; 327eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 328eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 329eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 33076eceb0fSGuido Günther rohm,dvs-run-voltage = <900000>; 331eb4ea085SAngus Ainslie (Purism) }; 332eb4ea085SAngus Ainslie (Purism) 333eb4ea085SAngus Ainslie (Purism) buck4_reg: BUCK4 { 334eb4ea085SAngus Ainslie (Purism) regulator-name = "buck4"; 335eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 336eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1300000>; 337eb4ea085SAngus Ainslie (Purism) rohm,dvs-run-voltage = <1000000>; 338eb4ea085SAngus Ainslie (Purism) }; 339eb4ea085SAngus Ainslie (Purism) 340eb4ea085SAngus Ainslie (Purism) buck5_reg: BUCK5 { 341eb4ea085SAngus Ainslie (Purism) regulator-name = "buck5"; 342eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <700000>; 343eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1350000>; 344eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 345edb93de4SGuido Günther regulator-always-on; 346eb4ea085SAngus Ainslie (Purism) }; 347eb4ea085SAngus Ainslie (Purism) 348eb4ea085SAngus Ainslie (Purism) buck6_reg: BUCK6 { 349eb4ea085SAngus Ainslie (Purism) regulator-name = "buck6"; 350eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 351eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 352eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 353edb93de4SGuido Günther regulator-always-on; 354eb4ea085SAngus Ainslie (Purism) }; 355eb4ea085SAngus Ainslie (Purism) 356eb4ea085SAngus Ainslie (Purism) buck7_reg: BUCK7 { 357eb4ea085SAngus Ainslie (Purism) regulator-name = "buck7"; 358eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1605000>; 359eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1995000>; 360eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 361edb93de4SGuido Günther regulator-always-on; 362eb4ea085SAngus Ainslie (Purism) }; 363eb4ea085SAngus Ainslie (Purism) 364eb4ea085SAngus Ainslie (Purism) buck8_reg: BUCK8 { 365eb4ea085SAngus Ainslie (Purism) regulator-name = "buck8"; 366eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <800000>; 367eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1400000>; 368eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 369edb93de4SGuido Günther regulator-always-on; 370eb4ea085SAngus Ainslie (Purism) }; 371eb4ea085SAngus Ainslie (Purism) 372eb4ea085SAngus Ainslie (Purism) ldo1_reg: LDO1 { 373eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo1"; 374eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <3000000>; 375eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 376eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 377eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 378eb4ea085SAngus Ainslie (Purism) regulator-always-on; 379eb4ea085SAngus Ainslie (Purism) }; 380eb4ea085SAngus Ainslie (Purism) 381eb4ea085SAngus Ainslie (Purism) ldo2_reg: LDO2 { 382eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo2"; 383eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 384eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <900000>; 385eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 386eb4ea085SAngus Ainslie (Purism) /* leave on for snvs power button */ 387eb4ea085SAngus Ainslie (Purism) regulator-always-on; 388eb4ea085SAngus Ainslie (Purism) }; 389eb4ea085SAngus Ainslie (Purism) 390eb4ea085SAngus Ainslie (Purism) ldo3_reg: LDO3 { 391eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo3"; 392eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 393eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 394eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 395edb93de4SGuido Günther regulator-always-on; 396eb4ea085SAngus Ainslie (Purism) }; 397eb4ea085SAngus Ainslie (Purism) 398eb4ea085SAngus Ainslie (Purism) ldo4_reg: LDO4 { 399eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo4"; 400eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 401eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 402eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 403edb93de4SGuido Günther regulator-always-on; 404eb4ea085SAngus Ainslie (Purism) }; 405eb4ea085SAngus Ainslie (Purism) 406eb4ea085SAngus Ainslie (Purism) ldo5_reg: LDO5 { 407eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo5"; 408eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 409eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 410edb93de4SGuido Günther regulator-always-on; 411eb4ea085SAngus Ainslie (Purism) }; 412eb4ea085SAngus Ainslie (Purism) 413eb4ea085SAngus Ainslie (Purism) ldo6_reg: LDO6 { 414eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo6"; 415eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <900000>; 416eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <1800000>; 417eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 418edb93de4SGuido Günther regulator-always-on; 419eb4ea085SAngus Ainslie (Purism) }; 420eb4ea085SAngus Ainslie (Purism) 421eb4ea085SAngus Ainslie (Purism) ldo7_reg: LDO7 { 422eb4ea085SAngus Ainslie (Purism) regulator-name = "ldo7"; 423eb4ea085SAngus Ainslie (Purism) regulator-min-microvolt = <1800000>; 424eb4ea085SAngus Ainslie (Purism) regulator-max-microvolt = <3300000>; 425eb4ea085SAngus Ainslie (Purism) regulator-boot-on; 426edb93de4SGuido Günther regulator-always-on; 427eb4ea085SAngus Ainslie (Purism) }; 428eb4ea085SAngus Ainslie (Purism) }; 429eb4ea085SAngus Ainslie (Purism) }; 430eb4ea085SAngus Ainslie (Purism) 4319251dad3SGuido Günther typec_ptn5100: usb-typec@52 { 432eb4ea085SAngus Ainslie (Purism) compatible = "nxp,ptn5110"; 433eb4ea085SAngus Ainslie (Purism) reg = <0x52>; 434eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 435eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_typec>; 436eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 437eb4ea085SAngus Ainslie (Purism) interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 438eb4ea085SAngus Ainslie (Purism) 439eb4ea085SAngus Ainslie (Purism) connector { 440eb4ea085SAngus Ainslie (Purism) compatible = "usb-c-connector"; 441eb4ea085SAngus Ainslie (Purism) label = "USB-C"; 442eb4ea085SAngus Ainslie (Purism) data-role = "dual"; 443eb4ea085SAngus Ainslie (Purism) power-role = "dual"; 444eb4ea085SAngus Ainslie (Purism) try-power-role = "sink"; 445eb4ea085SAngus Ainslie (Purism) source-pdos = <PDO_FIXED(5000, 2000, 446eb4ea085SAngus Ainslie (Purism) PDO_FIXED_USB_COMM | 447eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 448eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP )>; 4495369d191SAngus Ainslie (Purism) sink-pdos = <PDO_FIXED(5000, 3500, PDO_FIXED_USB_COMM | 450eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DUAL_ROLE | 451eb4ea085SAngus Ainslie (Purism) PDO_FIXED_DATA_SWAP ) 4525369d191SAngus Ainslie (Purism) PDO_VAR(5000, 5000, 3500)>; 453eb4ea085SAngus Ainslie (Purism) op-sink-microwatt = <10000000>; 454eb4ea085SAngus Ainslie (Purism) 455eb4ea085SAngus Ainslie (Purism) ports { 456eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 457eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 458eb4ea085SAngus Ainslie (Purism) 459eb4ea085SAngus Ainslie (Purism) port@0 { 460eb4ea085SAngus Ainslie (Purism) reg = <0>; 461eb4ea085SAngus Ainslie (Purism) 462eb4ea085SAngus Ainslie (Purism) usb_con_hs: endpoint { 463eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_hs>; 464eb4ea085SAngus Ainslie (Purism) }; 465eb4ea085SAngus Ainslie (Purism) }; 466eb4ea085SAngus Ainslie (Purism) 467eb4ea085SAngus Ainslie (Purism) port@1 { 468eb4ea085SAngus Ainslie (Purism) reg = <1>; 469eb4ea085SAngus Ainslie (Purism) 470eb4ea085SAngus Ainslie (Purism) usb_con_ss: endpoint { 471eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&typec_ss>; 472eb4ea085SAngus Ainslie (Purism) }; 473eb4ea085SAngus Ainslie (Purism) }; 474eb4ea085SAngus Ainslie (Purism) }; 475eb4ea085SAngus Ainslie (Purism) }; 476eb4ea085SAngus Ainslie (Purism) }; 477eb4ea085SAngus Ainslie (Purism) 478eb4ea085SAngus Ainslie (Purism) rtc@68 { 479eb4ea085SAngus Ainslie (Purism) compatible = "microcrystal,rv4162"; 480eb4ea085SAngus Ainslie (Purism) reg = <0x68>; 481eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 482eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_rtc>; 483eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio4>; 484eb4ea085SAngus Ainslie (Purism) interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 485eb4ea085SAngus Ainslie (Purism) }; 486eb4ea085SAngus Ainslie (Purism) 487eb4ea085SAngus Ainslie (Purism) charger@6b { /* bq25896 */ 488eb4ea085SAngus Ainslie (Purism) compatible = "ti,bq25890"; 489eb4ea085SAngus Ainslie (Purism) reg = <0x6b>; 490eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 491eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_charger>; 492eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 493eb4ea085SAngus Ainslie (Purism) interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 494eb4ea085SAngus Ainslie (Purism) ti,battery-regulation-voltage = <4192000>; /* 4.192V */ 495eb4ea085SAngus Ainslie (Purism) ti,charge-current = <1600000>; /* 1.6A */ 496eb4ea085SAngus Ainslie (Purism) ti,termination-current = <66000>; /* 66mA */ 497eb4ea085SAngus Ainslie (Purism) ti,precharge-current = <130000>; /* 130mA */ 498eb4ea085SAngus Ainslie (Purism) ti,minimum-sys-voltage = <3000000>; /* 3V */ 499eb4ea085SAngus Ainslie (Purism) ti,boost-voltage = <5000000>; /* 5V */ 500eb4ea085SAngus Ainslie (Purism) ti,boost-max-current = <50000>; /* 50mA */ 501eb4ea085SAngus Ainslie (Purism) }; 502eb4ea085SAngus Ainslie (Purism)}; 503eb4ea085SAngus Ainslie (Purism) 504eb4ea085SAngus Ainslie (Purism)&i2c3 { 505eb4ea085SAngus Ainslie (Purism) clock-frequency = <100000>; 506eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 507eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_i2c3>; 508eb4ea085SAngus Ainslie (Purism) status = "okay"; 509eb4ea085SAngus Ainslie (Purism) 510eb4ea085SAngus Ainslie (Purism) magnetometer@1e { 511eb4ea085SAngus Ainslie (Purism) compatible = "st,lsm9ds1-magn"; 512eb4ea085SAngus Ainslie (Purism) reg = <0x1e>; 513eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 514eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_imu>; 515eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 516106f7b3bSAngus Ainslie (Purism) interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 517eb4ea085SAngus Ainslie (Purism) vdd-supply = <®_3v3_p>; 518eb4ea085SAngus Ainslie (Purism) vddio-supply = <®_3v3_p>; 519eb4ea085SAngus Ainslie (Purism) }; 520eb4ea085SAngus Ainslie (Purism) 521c53f0166SAngus Ainslie (Purism) sgtl5000: audio-codec@a { 522c53f0166SAngus Ainslie (Purism) compatible = "fsl,sgtl5000"; 523c53f0166SAngus Ainslie (Purism) clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; 524c53f0166SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 525c53f0166SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 526c53f0166SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 527c53f0166SAngus Ainslie (Purism) #sound-dai-cells = <0>; 528c53f0166SAngus Ainslie (Purism) reg = <0x0a>; 529c53f0166SAngus Ainslie (Purism) VDDD-supply = <®_1v8_p>; 530c53f0166SAngus Ainslie (Purism) VDDIO-supply = <®_3v3_p>; 531c53f0166SAngus Ainslie (Purism) VDDA-supply = <®_3v3_p>; 532c53f0166SAngus Ainslie (Purism) }; 533c53f0166SAngus Ainslie (Purism) 534eb4ea085SAngus Ainslie (Purism) touchscreen@5d { 535eb4ea085SAngus Ainslie (Purism) compatible = "goodix,gt5688"; 536eb4ea085SAngus Ainslie (Purism) reg = <0x5d>; 537eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 538eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_ts>; 539eb4ea085SAngus Ainslie (Purism) interrupt-parent = <&gpio3>; 540eb4ea085SAngus Ainslie (Purism) interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 541eb4ea085SAngus Ainslie (Purism) reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; 542eb4ea085SAngus Ainslie (Purism) irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 543eb4ea085SAngus Ainslie (Purism) touchscreen-size-x = <720>; 544eb4ea085SAngus Ainslie (Purism) touchscreen-size-y = <1440>; 545eb4ea085SAngus Ainslie (Purism) AVDD28-supply = <®_2v8_p>; 546eb4ea085SAngus Ainslie (Purism) VDDIO-supply = <®_1v8_p>; 547eb4ea085SAngus Ainslie (Purism) }; 548537c00e3SMartin Kepplinger 549ea38ca9aSGuido Günther proximity-sensor@60 { 550ea38ca9aSGuido Günther compatible = "vishay,vcnl4040"; 551ea38ca9aSGuido Günther reg = <0x60>; 552ea38ca9aSGuido Günther pinctrl-0 = <&pinctrl_prox>; 553ea38ca9aSGuido Günther }; 554ea38ca9aSGuido Günther 555537c00e3SMartin Kepplinger accel-gyro@6a { 556537c00e3SMartin Kepplinger compatible = "st,lsm9ds1-imu"; 557537c00e3SMartin Kepplinger reg = <0x6a>; 558537c00e3SMartin Kepplinger vdd-supply = <®_3v3_p>; 559537c00e3SMartin Kepplinger vddio-supply = <®_3v3_p>; 560eef22bb1SMartin Kepplinger mount-matrix = "1", "0", "0", 561eef22bb1SMartin Kepplinger "0", "1", "0", 562eef22bb1SMartin Kepplinger "0", "0", "-1"; 563537c00e3SMartin Kepplinger }; 564eb4ea085SAngus Ainslie (Purism)}; 565eb4ea085SAngus Ainslie (Purism) 566eb4ea085SAngus Ainslie (Purism)&iomuxc { 567eb4ea085SAngus Ainslie (Purism) pinctrl_bl: blgrp { 568eb4ea085SAngus Ainslie (Purism) fsl,pins = < 569eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* DSI_BL_PWM */ 570eb4ea085SAngus Ainslie (Purism) >; 571eb4ea085SAngus Ainslie (Purism) }; 572eb4ea085SAngus Ainslie (Purism) 573eb4ea085SAngus Ainslie (Purism) pinctrl_bt: btgrp { 574eb4ea085SAngus Ainslie (Purism) fsl,pins = < 575eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16 /* nBT_DISABLE */ 576eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10 /* BT_HOST_WAKE */ 577eb4ea085SAngus Ainslie (Purism) >; 578eb4ea085SAngus Ainslie (Purism) }; 579eb4ea085SAngus Ainslie (Purism) 580eb4ea085SAngus Ainslie (Purism) pinctrl_charger: chargergrp { 581eb4ea085SAngus Ainslie (Purism) fsl,pins = < 582eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80 /* CHRG_nINT */ 583eb4ea085SAngus Ainslie (Purism) >; 584eb4ea085SAngus Ainslie (Purism) }; 585eb4ea085SAngus Ainslie (Purism) 586eb4ea085SAngus Ainslie (Purism) pinctrl_fec1: fec1grp { 587eb4ea085SAngus Ainslie (Purism) fsl,pins = < 588eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 589eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 590eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 591eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 592eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 593eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 594eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 595eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 596eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 597eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 598eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 599eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 600eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 601eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 602eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 603eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f 604eb4ea085SAngus Ainslie (Purism) >; 605eb4ea085SAngus Ainslie (Purism) }; 606eb4ea085SAngus Ainslie (Purism) 607eb4ea085SAngus Ainslie (Purism) pinctrl_ts: tsgrp { 608eb4ea085SAngus Ainslie (Purism) fsl,pins = < 609eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16 /* TOUCH INT */ 610eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* TOUCH RST */ 611eb4ea085SAngus Ainslie (Purism) >; 612eb4ea085SAngus Ainslie (Purism) }; 613eb4ea085SAngus Ainslie (Purism) 61429ecef8eSGuido Günther pinctrl_pwm_led: pwmledgrp { 615eb4ea085SAngus Ainslie (Purism) fsl,pins = < 61629ecef8eSGuido Günther MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 617eb4ea085SAngus Ainslie (Purism) >; 618eb4ea085SAngus Ainslie (Purism) }; 619eb4ea085SAngus Ainslie (Purism) 620eb4ea085SAngus Ainslie (Purism) pinctrl_gpio_keys: gpiokeygrp { 621eb4ea085SAngus Ainslie (Purism) fsl,pins = < 622eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16 623eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16 6243ef506b3SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ 625eb4ea085SAngus Ainslie (Purism) >; 626eb4ea085SAngus Ainslie (Purism) }; 627eb4ea085SAngus Ainslie (Purism) 628eb4ea085SAngus Ainslie (Purism) pinctrl_haptic: hapticgrp { 629eb4ea085SAngus Ainslie (Purism) fsl,pins = < 630eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0xc6 /* nHAPTIC */ 631eb4ea085SAngus Ainslie (Purism) >; 632eb4ea085SAngus Ainslie (Purism) }; 633eb4ea085SAngus Ainslie (Purism) 634d779f4c9SGuido Günther pinctrl_hpdet: hpdetgrp { 635d779f4c9SGuido Günther fsl,pins = < 636d779f4c9SGuido Günther MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */ 637d779f4c9SGuido Günther >; 638d779f4c9SGuido Günther }; 639d779f4c9SGuido Günther 640eb4ea085SAngus Ainslie (Purism) pinctrl_i2c1: i2c1grp { 641eb4ea085SAngus Ainslie (Purism) fsl,pins = < 642eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f 643eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f 644eb4ea085SAngus Ainslie (Purism) >; 645eb4ea085SAngus Ainslie (Purism) }; 646eb4ea085SAngus Ainslie (Purism) 647eb4ea085SAngus Ainslie (Purism) pinctrl_i2c3: i2c3grp { 648eb4ea085SAngus Ainslie (Purism) fsl,pins = < 649eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f 650eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f 651eb4ea085SAngus Ainslie (Purism) >; 652eb4ea085SAngus Ainslie (Purism) }; 653eb4ea085SAngus Ainslie (Purism) 654eb4ea085SAngus Ainslie (Purism) pinctrl_imu: imugrp { 655eb4ea085SAngus Ainslie (Purism) fsl,pins = < 656eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8 /* IMU_INT */ 657eb4ea085SAngus Ainslie (Purism) >; 658eb4ea085SAngus Ainslie (Purism) }; 659eb4ea085SAngus Ainslie (Purism) 66015094482SGuido Günther pinctrl_micsel: micselgrp { 66115094482SGuido Günther fsl,pins = < 66215094482SGuido Günther MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6 /* MIC_SEL */ 66315094482SGuido Günther >; 66415094482SGuido Günther }; 66515094482SGuido Günther 66672783d65SPeng Fan pinctrl_spkamp: spkampgrp { 6676f46f7ffSGuido Günther fsl,pins = < 6686f46f7ffSGuido Günther MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x81 /* MUTE */ 6696f46f7ffSGuido Günther >; 6706f46f7ffSGuido Günther }; 6716f46f7ffSGuido Günther 672eb4ea085SAngus Ainslie (Purism) pinctrl_pmic: pmicgrp { 673eb4ea085SAngus Ainslie (Purism) fsl,pins = < 674eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80 /* PMIC intr */ 675eb4ea085SAngus Ainslie (Purism) >; 676eb4ea085SAngus Ainslie (Purism) }; 677eb4ea085SAngus Ainslie (Purism) 678ea38ca9aSGuido Günther pinctrl_prox: proxgrp { 679ea38ca9aSGuido Günther fsl,pins = < 680ea38ca9aSGuido Günther MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80 /* prox intr */ 681ea38ca9aSGuido Günther >; 682ea38ca9aSGuido Günther }; 683ea38ca9aSGuido Günther 684eb4ea085SAngus Ainslie (Purism) pinctrl_pwr_en: pwrengrp { 685eb4ea085SAngus Ainslie (Purism) fsl,pins = < 686eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06 687eb4ea085SAngus Ainslie (Purism) >; 688eb4ea085SAngus Ainslie (Purism) }; 689eb4ea085SAngus Ainslie (Purism) 690eb4ea085SAngus Ainslie (Purism) pinctrl_rtc: rtcgrp { 691eb4ea085SAngus Ainslie (Purism) fsl,pins = < 692eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80 /* RTC intr */ 693eb4ea085SAngus Ainslie (Purism) >; 694eb4ea085SAngus Ainslie (Purism) }; 695eb4ea085SAngus Ainslie (Purism) 696c53f0166SAngus Ainslie (Purism) pinctrl_sai2: sai2grp { 697c53f0166SAngus Ainslie (Purism) fsl,pins = < 698c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 699c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 700c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 701c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 702c53f0166SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 703c53f0166SAngus Ainslie (Purism) >; 704c53f0166SAngus Ainslie (Purism) }; 705c53f0166SAngus Ainslie (Purism) 7067f7b7997SAngus Ainslie (Purism) pinctrl_sai6: sai6grp { 7077f7b7997SAngus Ainslie (Purism) fsl,pins = < 7087f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6 7097f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6 7107f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6 7117f7b7997SAngus Ainslie (Purism) MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6 7127f7b7997SAngus Ainslie (Purism) >; 7137f7b7997SAngus Ainslie (Purism) }; 7147f7b7997SAngus Ainslie (Purism) 715eb4ea085SAngus Ainslie (Purism) pinctrl_typec: typecgrp { 716eb4ea085SAngus Ainslie (Purism) fsl,pins = < 717eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16 718eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80 719eb4ea085SAngus Ainslie (Purism) >; 720eb4ea085SAngus Ainslie (Purism) }; 721eb4ea085SAngus Ainslie (Purism) 722eb4ea085SAngus Ainslie (Purism) pinctrl_uart1: uart1grp { 723eb4ea085SAngus Ainslie (Purism) fsl,pins = < 724eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 725eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 726eb4ea085SAngus Ainslie (Purism) >; 727eb4ea085SAngus Ainslie (Purism) }; 728eb4ea085SAngus Ainslie (Purism) 729eb4ea085SAngus Ainslie (Purism) pinctrl_uart2: uart2grp { 730eb4ea085SAngus Ainslie (Purism) fsl,pins = < 731eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 732eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 733eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49 734eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49 735eb4ea085SAngus Ainslie (Purism) >; 736eb4ea085SAngus Ainslie (Purism) }; 737eb4ea085SAngus Ainslie (Purism) 738eb4ea085SAngus Ainslie (Purism) pinctrl_uart3: uart3grp { 739eb4ea085SAngus Ainslie (Purism) fsl,pins = < 740eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 741eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 742eb4ea085SAngus Ainslie (Purism) >; 743eb4ea085SAngus Ainslie (Purism) }; 744eb4ea085SAngus Ainslie (Purism) 745eb4ea085SAngus Ainslie (Purism) pinctrl_uart4: uart4grp { 746eb4ea085SAngus Ainslie (Purism) fsl,pins = < 747eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 748eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 749eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 750eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 751eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49 752eb4ea085SAngus Ainslie (Purism) >; 753eb4ea085SAngus Ainslie (Purism) }; 754eb4ea085SAngus Ainslie (Purism) 755eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc1: usdhc1grp { 756eb4ea085SAngus Ainslie (Purism) fsl,pins = < 757eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 758eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 759eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 760eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 761eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 762eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 763eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 764eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 765eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 766eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 767eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 768eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 769eb4ea085SAngus Ainslie (Purism) >; 770eb4ea085SAngus Ainslie (Purism) }; 771eb4ea085SAngus Ainslie (Purism) 772ae560c43SKrzysztof Kozlowski pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 773eb4ea085SAngus Ainslie (Purism) fsl,pins = < 774eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 775eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 776eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 777eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 778eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 779eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 780eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 781eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 782eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 783eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 784eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 785eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 786eb4ea085SAngus Ainslie (Purism) >; 787eb4ea085SAngus Ainslie (Purism) }; 788eb4ea085SAngus Ainslie (Purism) 789ae560c43SKrzysztof Kozlowski pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 790eb4ea085SAngus Ainslie (Purism) fsl,pins = < 791eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 792eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 793eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 794eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 795eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 796eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 797eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 798eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 799eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 800eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 801eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 802eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 803eb4ea085SAngus Ainslie (Purism) >; 804eb4ea085SAngus Ainslie (Purism) }; 805eb4ea085SAngus Ainslie (Purism) 806*60ac8a77SGuido Günther pinctrl_usdhc2_rst: usdhc2rstgrp { 807eb4ea085SAngus Ainslie (Purism) fsl,pins = < 808eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 809eb4ea085SAngus Ainslie (Purism) >; 810eb4ea085SAngus Ainslie (Purism) }; 811eb4ea085SAngus Ainslie (Purism) 812ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_gpio: usdhc2gpiogrp { 813eb4ea085SAngus Ainslie (Purism) fsl,pins = < 814eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */ 815eb4ea085SAngus Ainslie (Purism) >; 816eb4ea085SAngus Ainslie (Purism) }; 817eb4ea085SAngus Ainslie (Purism) 818eb4ea085SAngus Ainslie (Purism) pinctrl_usdhc2: usdhc2grp { 819eb4ea085SAngus Ainslie (Purism) fsl,pins = < 820eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 821eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 822eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 823eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 824eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 825eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 826eb4ea085SAngus Ainslie (Purism) >; 827eb4ea085SAngus Ainslie (Purism) }; 828eb4ea085SAngus Ainslie (Purism) 829ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 830eb4ea085SAngus Ainslie (Purism) fsl,pins = < 831eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 832eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 833eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 834eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 835eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 836eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 837eb4ea085SAngus Ainslie (Purism) >; 838eb4ea085SAngus Ainslie (Purism) }; 839eb4ea085SAngus Ainslie (Purism) 840ae560c43SKrzysztof Kozlowski pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 841eb4ea085SAngus Ainslie (Purism) fsl,pins = < 842eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 843eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf 844eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf 845eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf 846eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf 847eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf 848eb4ea085SAngus Ainslie (Purism) >; 849eb4ea085SAngus Ainslie (Purism) }; 850eb4ea085SAngus Ainslie (Purism) 851eb4ea085SAngus Ainslie (Purism) pinctrl_wdog: wdoggrp { 852eb4ea085SAngus Ainslie (Purism) fsl,pins = < 853eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 854eb4ea085SAngus Ainslie (Purism) >; 855eb4ea085SAngus Ainslie (Purism) }; 856eb4ea085SAngus Ainslie (Purism) 857eb4ea085SAngus Ainslie (Purism) pinctrl_wifi_pwr_en: wifipwrengrp { 858eb4ea085SAngus Ainslie (Purism) fsl,pins = < 859eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 860eb4ea085SAngus Ainslie (Purism) >; 861eb4ea085SAngus Ainslie (Purism) }; 862eb4ea085SAngus Ainslie (Purism) 863eb4ea085SAngus Ainslie (Purism) pinctrl_wwan: wwangrp { 864eb4ea085SAngus Ainslie (Purism) fsl,pins = < 865eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09 /* nWWAN_DISABLE */ 866eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80 /* nWoWWAN */ 867eb4ea085SAngus Ainslie (Purism) MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* WWAN_RESET */ 868eb4ea085SAngus Ainslie (Purism) >; 869eb4ea085SAngus Ainslie (Purism) }; 870eb4ea085SAngus Ainslie (Purism)}; 871eb4ea085SAngus Ainslie (Purism) 872e8151ef3SGuido Günther&lcdif { 873e8151ef3SGuido Günther status = "okay"; 874e8151ef3SGuido Günther}; 875e8151ef3SGuido Günther 876e8151ef3SGuido Günther&mipi_dsi { 877e8151ef3SGuido Günther status = "okay"; 878e8151ef3SGuido Günther #address-cells = <1>; 879e8151ef3SGuido Günther #size-cells = <0>; 880e8151ef3SGuido Günther 881e8151ef3SGuido Günther panel@0 { 882e8151ef3SGuido Günther compatible = "rocktech,jh057n00900"; 883e8151ef3SGuido Günther reg = <0>; 884e8151ef3SGuido Günther backlight = <&backlight_dsi>; 885e8151ef3SGuido Günther reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; 886e8151ef3SGuido Günther iovcc-supply = <®_1v8_p>; 887e8151ef3SGuido Günther vcc-supply = <®_2v8_p>; 888e8151ef3SGuido Günther port { 889e8151ef3SGuido Günther panel_in: endpoint { 890e8151ef3SGuido Günther remote-endpoint = <&mipi_dsi_out>; 891e8151ef3SGuido Günther }; 892e8151ef3SGuido Günther }; 893e8151ef3SGuido Günther }; 894e8151ef3SGuido Günther 895e8151ef3SGuido Günther ports { 896e8151ef3SGuido Günther port@1 { 897e8151ef3SGuido Günther reg = <1>; 898e8151ef3SGuido Günther mipi_dsi_out: endpoint { 899e8151ef3SGuido Günther remote-endpoint = <&panel_in>; 900e8151ef3SGuido Günther }; 901e8151ef3SGuido Günther }; 902e8151ef3SGuido Günther }; 903e8151ef3SGuido Günther}; 904e8151ef3SGuido Günther 905eb4ea085SAngus Ainslie (Purism)&pgc_gpu { 906eb4ea085SAngus Ainslie (Purism) power-supply = <&buck3_reg>; 907eb4ea085SAngus Ainslie (Purism)}; 908eb4ea085SAngus Ainslie (Purism) 909eb4ea085SAngus Ainslie (Purism)&pgc_vpu { 910eb4ea085SAngus Ainslie (Purism) power-supply = <&buck4_reg>; 911eb4ea085SAngus Ainslie (Purism)}; 912eb4ea085SAngus Ainslie (Purism) 913eb4ea085SAngus Ainslie (Purism)&pwm1 { 914eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 915eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_bl>; 916eb4ea085SAngus Ainslie (Purism) status = "okay"; 917eb4ea085SAngus Ainslie (Purism)}; 918eb4ea085SAngus Ainslie (Purism) 91929ecef8eSGuido Günther&pwm2 { 92029ecef8eSGuido Günther pinctrl-names = "default"; 92129ecef8eSGuido Günther pinctrl-0 = <&pinctrl_pwm_led>; 92229ecef8eSGuido Günther status = "okay"; 92329ecef8eSGuido Günther}; 92429ecef8eSGuido Günther 92501407158SAngus Ainslie (Purism)&snvs_pwrkey { 92601407158SAngus Ainslie (Purism) status = "okay"; 92701407158SAngus Ainslie (Purism)}; 928eb4ea085SAngus Ainslie (Purism) 929ff38c1ddSGuido Günther&snvs_rtc { 930ff38c1ddSGuido Günther status = "disabled"; 931ff38c1ddSGuido Günther}; 932ff38c1ddSGuido Günther 933c53f0166SAngus Ainslie (Purism)&sai2 { 934c53f0166SAngus Ainslie (Purism) pinctrl-names = "default"; 935c53f0166SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_sai2>; 936c53f0166SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; 937c53f0166SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 938c53f0166SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 939c53f0166SAngus Ainslie (Purism) status = "okay"; 940c53f0166SAngus Ainslie (Purism)}; 941c53f0166SAngus Ainslie (Purism) 9427f7b7997SAngus Ainslie (Purism)&sai6 { 9437f7b7997SAngus Ainslie (Purism) pinctrl-names = "default"; 9447f7b7997SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_sai6>; 9457f7b7997SAngus Ainslie (Purism) assigned-clocks = <&clk IMX8MQ_CLK_SAI6>; 9467f7b7997SAngus Ainslie (Purism) assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; 9477f7b7997SAngus Ainslie (Purism) assigned-clock-rates = <24576000>; 9487f7b7997SAngus Ainslie (Purism) fsl,sai-synchronous-rx; 9497f7b7997SAngus Ainslie (Purism) status = "okay"; 9507f7b7997SAngus Ainslie (Purism)}; 9517f7b7997SAngus Ainslie (Purism) 952eb4ea085SAngus Ainslie (Purism)&uart1 { /* console */ 953eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 954eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart1>; 955eb4ea085SAngus Ainslie (Purism) status = "okay"; 956eb4ea085SAngus Ainslie (Purism)}; 957eb4ea085SAngus Ainslie (Purism) 958eb4ea085SAngus Ainslie (Purism)&uart3 { /* GNSS */ 959eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 960eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart3>; 961eb4ea085SAngus Ainslie (Purism) status = "okay"; 962eb4ea085SAngus Ainslie (Purism)}; 963eb4ea085SAngus Ainslie (Purism) 964eb4ea085SAngus Ainslie (Purism)&uart4 { /* BT */ 965eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 966eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; 967eb4ea085SAngus Ainslie (Purism) uart-has-rtscts; 968eb4ea085SAngus Ainslie (Purism) status = "okay"; 969eb4ea085SAngus Ainslie (Purism)}; 970eb4ea085SAngus Ainslie (Purism) 971eb4ea085SAngus Ainslie (Purism)&usb3_phy0 { 972dde061b8SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 973eb4ea085SAngus Ainslie (Purism) status = "okay"; 974eb4ea085SAngus Ainslie (Purism)}; 975eb4ea085SAngus Ainslie (Purism) 976eb4ea085SAngus Ainslie (Purism)&usb3_phy1 { 977eb4ea085SAngus Ainslie (Purism) vbus-supply = <®_5v_p>; 978eb4ea085SAngus Ainslie (Purism) status = "okay"; 979eb4ea085SAngus Ainslie (Purism)}; 980eb4ea085SAngus Ainslie (Purism) 981eb4ea085SAngus Ainslie (Purism)&usb_dwc3_0 { 982eb4ea085SAngus Ainslie (Purism) #address-cells = <1>; 983eb4ea085SAngus Ainslie (Purism) #size-cells = <0>; 984eb4ea085SAngus Ainslie (Purism) dr_mode = "otg"; 985eb4ea085SAngus Ainslie (Purism) status = "okay"; 986eb4ea085SAngus Ainslie (Purism) 987eb4ea085SAngus Ainslie (Purism) port@0 { 988eb4ea085SAngus Ainslie (Purism) reg = <0>; 989eb4ea085SAngus Ainslie (Purism) 990eb4ea085SAngus Ainslie (Purism) typec_hs: endpoint { 991eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_hs>; 992eb4ea085SAngus Ainslie (Purism) }; 993eb4ea085SAngus Ainslie (Purism) }; 994eb4ea085SAngus Ainslie (Purism) 995eb4ea085SAngus Ainslie (Purism) port@1 { 996eb4ea085SAngus Ainslie (Purism) reg = <1>; 997eb4ea085SAngus Ainslie (Purism) 998eb4ea085SAngus Ainslie (Purism) typec_ss: endpoint { 999eb4ea085SAngus Ainslie (Purism) remote-endpoint = <&usb_con_ss>; 1000eb4ea085SAngus Ainslie (Purism) }; 1001eb4ea085SAngus Ainslie (Purism) }; 1002eb4ea085SAngus Ainslie (Purism)}; 1003eb4ea085SAngus Ainslie (Purism) 1004eb4ea085SAngus Ainslie (Purism)&usb_dwc3_1 { 1005eb4ea085SAngus Ainslie (Purism) dr_mode = "host"; 1006eb4ea085SAngus Ainslie (Purism) status = "okay"; 1007eb4ea085SAngus Ainslie (Purism)}; 1008eb4ea085SAngus Ainslie (Purism) 1009eb4ea085SAngus Ainslie (Purism)&usdhc1 { 1010e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 1011e045f044SAnson Huang assigned-clock-rates = <400000000>; 1012eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1013eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc1>; 1014eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 1015eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 1016eb4ea085SAngus Ainslie (Purism) bus-width = <8>; 1017eb4ea085SAngus Ainslie (Purism) non-removable; 1018eb4ea085SAngus Ainslie (Purism) status = "okay"; 1019eb4ea085SAngus Ainslie (Purism)}; 1020eb4ea085SAngus Ainslie (Purism) 1021eb4ea085SAngus Ainslie (Purism)&usdhc2 { 1022e045f044SAnson Huang assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 1023e045f044SAnson Huang assigned-clock-rates = <200000000>; 1024eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default", "state_100mhz", "state_200mhz"; 1025eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_usdhc2>; 1026eb4ea085SAngus Ainslie (Purism) pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 1027eb4ea085SAngus Ainslie (Purism) pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 1028eb4ea085SAngus Ainslie (Purism) bus-width = <4>; 1029*60ac8a77SGuido Günther vmmc-supply = <&wifi_pwr_en>; 1030*60ac8a77SGuido Günther mmc-pwrseq = <&wifi_pwr_seq>; 10319dae8563SAngus Ainslie (Purism) broken-cd; 1032eb4ea085SAngus Ainslie (Purism) disable-wp; 1033eb4ea085SAngus Ainslie (Purism) cap-sdio-irq; 1034eb4ea085SAngus Ainslie (Purism) keep-power-in-suspend; 1035eb4ea085SAngus Ainslie (Purism) wakeup-source; 1036eb4ea085SAngus Ainslie (Purism) status = "okay"; 1037eb4ea085SAngus Ainslie (Purism)}; 1038eb4ea085SAngus Ainslie (Purism) 1039eb4ea085SAngus Ainslie (Purism)&wdog1 { 1040eb4ea085SAngus Ainslie (Purism) pinctrl-names = "default"; 1041eb4ea085SAngus Ainslie (Purism) pinctrl-0 = <&pinctrl_wdog>; 1042eb4ea085SAngus Ainslie (Purism) fsl,ext-reset-output; 1043eb4ea085SAngus Ainslie (Purism) status = "okay"; 1044eb4ea085SAngus Ainslie (Purism)}; 1045