1*5dbadc84SHeiko Thiery// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*5dbadc84SHeiko Thiery/* 3*5dbadc84SHeiko Thiery * Device Tree File for the Kontron pitx-imx8m board. 4*5dbadc84SHeiko Thiery * 5*5dbadc84SHeiko Thiery * Copyright (C) 2021 Heiko Thiery <heiko.thiery@gmail.com> 6*5dbadc84SHeiko Thiery */ 7*5dbadc84SHeiko Thiery 8*5dbadc84SHeiko Thiery/dts-v1/; 9*5dbadc84SHeiko Thiery 10*5dbadc84SHeiko Thiery#include "imx8mq.dtsi" 11*5dbadc84SHeiko Thiery#include <dt-bindings/net/ti-dp83867.h> 12*5dbadc84SHeiko Thiery 13*5dbadc84SHeiko Thiery/ { 14*5dbadc84SHeiko Thiery model = "Kontron pITX-imx8m"; 15*5dbadc84SHeiko Thiery compatible = "kontron,pitx-imx8m", "fsl,imx8mq"; 16*5dbadc84SHeiko Thiery 17*5dbadc84SHeiko Thiery aliases { 18*5dbadc84SHeiko Thiery i2c0 = &i2c1; 19*5dbadc84SHeiko Thiery i2c1 = &i2c2; 20*5dbadc84SHeiko Thiery i2c2 = &i2c3; 21*5dbadc84SHeiko Thiery mmc0 = &usdhc1; 22*5dbadc84SHeiko Thiery mmc1 = &usdhc2; 23*5dbadc84SHeiko Thiery serial0 = &uart1; 24*5dbadc84SHeiko Thiery serial1 = &uart2; 25*5dbadc84SHeiko Thiery serial2 = &uart3; 26*5dbadc84SHeiko Thiery spi0 = &qspi0; 27*5dbadc84SHeiko Thiery spi1 = &ecspi2; 28*5dbadc84SHeiko Thiery }; 29*5dbadc84SHeiko Thiery 30*5dbadc84SHeiko Thiery chosen { 31*5dbadc84SHeiko Thiery stdout-path = "serial2:115200n8"; 32*5dbadc84SHeiko Thiery }; 33*5dbadc84SHeiko Thiery 34*5dbadc84SHeiko Thiery pcie0_refclk: pcie0-clock { 35*5dbadc84SHeiko Thiery compatible = "fixed-clock"; 36*5dbadc84SHeiko Thiery #clock-cells = <0>; 37*5dbadc84SHeiko Thiery clock-frequency = <100000000>; 38*5dbadc84SHeiko Thiery }; 39*5dbadc84SHeiko Thiery 40*5dbadc84SHeiko Thiery pcie1_refclk: pcie1-clock { 41*5dbadc84SHeiko Thiery compatible = "fixed-clock"; 42*5dbadc84SHeiko Thiery #clock-cells = <0>; 43*5dbadc84SHeiko Thiery clock-frequency = <100000000>; 44*5dbadc84SHeiko Thiery }; 45*5dbadc84SHeiko Thiery 46*5dbadc84SHeiko Thiery reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 47*5dbadc84SHeiko Thiery compatible = "regulator-fixed"; 48*5dbadc84SHeiko Thiery pinctrl-names = "default"; 49*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_reg_usdhc2>; 50*5dbadc84SHeiko Thiery regulator-name = "V_3V3_SD"; 51*5dbadc84SHeiko Thiery regulator-min-microvolt = <3300000>; 52*5dbadc84SHeiko Thiery regulator-max-microvolt = <3300000>; 53*5dbadc84SHeiko Thiery gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 54*5dbadc84SHeiko Thiery off-on-delay-us = <20000>; 55*5dbadc84SHeiko Thiery enable-active-high; 56*5dbadc84SHeiko Thiery }; 57*5dbadc84SHeiko Thiery}; 58*5dbadc84SHeiko Thiery 59*5dbadc84SHeiko Thiery&ecspi2 { 60*5dbadc84SHeiko Thiery #address-cells = <1>; 61*5dbadc84SHeiko Thiery #size-cells = <0>; 62*5dbadc84SHeiko Thiery pinctrl-names = "default"; 63*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; 64*5dbadc84SHeiko Thiery cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 65*5dbadc84SHeiko Thiery status = "okay"; 66*5dbadc84SHeiko Thiery 67*5dbadc84SHeiko Thiery tpm@0 { 68*5dbadc84SHeiko Thiery compatible = "infineon,slb9670"; 69*5dbadc84SHeiko Thiery reg = <0>; 70*5dbadc84SHeiko Thiery spi-max-frequency = <43000000>; 71*5dbadc84SHeiko Thiery }; 72*5dbadc84SHeiko Thiery}; 73*5dbadc84SHeiko Thiery 74*5dbadc84SHeiko Thiery&fec1 { 75*5dbadc84SHeiko Thiery pinctrl-names = "default"; 76*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_fec1>; 77*5dbadc84SHeiko Thiery phy-mode = "rgmii-id"; 78*5dbadc84SHeiko Thiery phy-handle = <ðphy0>; 79*5dbadc84SHeiko Thiery fsl,magic-packet; 80*5dbadc84SHeiko Thiery status = "okay"; 81*5dbadc84SHeiko Thiery 82*5dbadc84SHeiko Thiery mdio { 83*5dbadc84SHeiko Thiery #address-cells = <1>; 84*5dbadc84SHeiko Thiery #size-cells = <0>; 85*5dbadc84SHeiko Thiery 86*5dbadc84SHeiko Thiery ethphy0: ethernet-phy@0 { 87*5dbadc84SHeiko Thiery compatible = "ethernet-phy-ieee802.3-c22"; 88*5dbadc84SHeiko Thiery reg = <0>; 89*5dbadc84SHeiko Thiery ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 90*5dbadc84SHeiko Thiery ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; 91*5dbadc84SHeiko Thiery ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 92*5dbadc84SHeiko Thiery reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 93*5dbadc84SHeiko Thiery reset-assert-us = <10>; 94*5dbadc84SHeiko Thiery reset-deassert-us = <280>; 95*5dbadc84SHeiko Thiery }; 96*5dbadc84SHeiko Thiery }; 97*5dbadc84SHeiko Thiery}; 98*5dbadc84SHeiko Thiery 99*5dbadc84SHeiko Thiery&i2c1 { 100*5dbadc84SHeiko Thiery clock-frequency = <400000>; 101*5dbadc84SHeiko Thiery pinctrl-names = "default"; 102*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_i2c1>; 103*5dbadc84SHeiko Thiery status = "okay"; 104*5dbadc84SHeiko Thiery 105*5dbadc84SHeiko Thiery pmic@8 { 106*5dbadc84SHeiko Thiery compatible = "fsl,pfuze100"; 107*5dbadc84SHeiko Thiery fsl,pfuze-support-disable-sw; 108*5dbadc84SHeiko Thiery reg = <0x8>; 109*5dbadc84SHeiko Thiery 110*5dbadc84SHeiko Thiery regulators { 111*5dbadc84SHeiko Thiery sw1a_reg: sw1ab { 112*5dbadc84SHeiko Thiery regulator-name = "V_0V9_GPU"; 113*5dbadc84SHeiko Thiery regulator-min-microvolt = <825000>; 114*5dbadc84SHeiko Thiery regulator-max-microvolt = <1100000>; 115*5dbadc84SHeiko Thiery }; 116*5dbadc84SHeiko Thiery 117*5dbadc84SHeiko Thiery sw1c_reg: sw1c { 118*5dbadc84SHeiko Thiery regulator-name = "V_0V9_VPU"; 119*5dbadc84SHeiko Thiery regulator-min-microvolt = <825000>; 120*5dbadc84SHeiko Thiery regulator-max-microvolt = <1100000>; 121*5dbadc84SHeiko Thiery }; 122*5dbadc84SHeiko Thiery 123*5dbadc84SHeiko Thiery sw2_reg: sw2 { 124*5dbadc84SHeiko Thiery regulator-name = "V_1V1_NVCC_DRAM"; 125*5dbadc84SHeiko Thiery regulator-min-microvolt = <1100000>; 126*5dbadc84SHeiko Thiery regulator-max-microvolt = <1100000>; 127*5dbadc84SHeiko Thiery regulator-always-on; 128*5dbadc84SHeiko Thiery }; 129*5dbadc84SHeiko Thiery 130*5dbadc84SHeiko Thiery sw3a_reg: sw3ab { 131*5dbadc84SHeiko Thiery regulator-name = "V_1V0_DRAM"; 132*5dbadc84SHeiko Thiery regulator-min-microvolt = <825000>; 133*5dbadc84SHeiko Thiery regulator-max-microvolt = <1100000>; 134*5dbadc84SHeiko Thiery regulator-always-on; 135*5dbadc84SHeiko Thiery }; 136*5dbadc84SHeiko Thiery 137*5dbadc84SHeiko Thiery sw4_reg: sw4 { 138*5dbadc84SHeiko Thiery regulator-name = "V_1V8_S0"; 139*5dbadc84SHeiko Thiery regulator-min-microvolt = <1800000>; 140*5dbadc84SHeiko Thiery regulator-max-microvolt = <1800000>; 141*5dbadc84SHeiko Thiery regulator-always-on; 142*5dbadc84SHeiko Thiery }; 143*5dbadc84SHeiko Thiery 144*5dbadc84SHeiko Thiery swbst_reg: swbst { 145*5dbadc84SHeiko Thiery regulator-name = "NC"; 146*5dbadc84SHeiko Thiery regulator-min-microvolt = <5000000>; 147*5dbadc84SHeiko Thiery regulator-max-microvolt = <5150000>; 148*5dbadc84SHeiko Thiery }; 149*5dbadc84SHeiko Thiery 150*5dbadc84SHeiko Thiery snvs_reg: vsnvs { 151*5dbadc84SHeiko Thiery regulator-name = "V_0V9_SNVS"; 152*5dbadc84SHeiko Thiery regulator-min-microvolt = <1000000>; 153*5dbadc84SHeiko Thiery regulator-max-microvolt = <3000000>; 154*5dbadc84SHeiko Thiery regulator-always-on; 155*5dbadc84SHeiko Thiery }; 156*5dbadc84SHeiko Thiery 157*5dbadc84SHeiko Thiery vref_reg: vrefddr { 158*5dbadc84SHeiko Thiery regulator-name = "V_0V55_VREF_DDR"; 159*5dbadc84SHeiko Thiery regulator-always-on; 160*5dbadc84SHeiko Thiery }; 161*5dbadc84SHeiko Thiery 162*5dbadc84SHeiko Thiery vgen1_reg: vgen1 { 163*5dbadc84SHeiko Thiery regulator-name = "V_1V5_CSI"; 164*5dbadc84SHeiko Thiery regulator-min-microvolt = <800000>; 165*5dbadc84SHeiko Thiery regulator-max-microvolt = <1550000>; 166*5dbadc84SHeiko Thiery }; 167*5dbadc84SHeiko Thiery 168*5dbadc84SHeiko Thiery vgen2_reg: vgen2 { 169*5dbadc84SHeiko Thiery regulator-name = "V_0V9_PHY"; 170*5dbadc84SHeiko Thiery regulator-min-microvolt = <850000>; 171*5dbadc84SHeiko Thiery regulator-max-microvolt = <975000>; 172*5dbadc84SHeiko Thiery regulator-always-on; 173*5dbadc84SHeiko Thiery }; 174*5dbadc84SHeiko Thiery 175*5dbadc84SHeiko Thiery vgen3_reg: vgen3 { 176*5dbadc84SHeiko Thiery regulator-name = "V_1V8_PHY"; 177*5dbadc84SHeiko Thiery regulator-min-microvolt = <1675000>; 178*5dbadc84SHeiko Thiery regulator-max-microvolt = <1975000>; 179*5dbadc84SHeiko Thiery regulator-always-on; 180*5dbadc84SHeiko Thiery }; 181*5dbadc84SHeiko Thiery 182*5dbadc84SHeiko Thiery vgen4_reg: vgen4 { 183*5dbadc84SHeiko Thiery regulator-name = "V_1V8_VDDA"; 184*5dbadc84SHeiko Thiery regulator-min-microvolt = <1625000>; 185*5dbadc84SHeiko Thiery regulator-max-microvolt = <1875000>; 186*5dbadc84SHeiko Thiery regulator-always-on; 187*5dbadc84SHeiko Thiery }; 188*5dbadc84SHeiko Thiery 189*5dbadc84SHeiko Thiery vgen5_reg: vgen5 { 190*5dbadc84SHeiko Thiery regulator-name = "V_3V3_PHY"; 191*5dbadc84SHeiko Thiery regulator-min-microvolt = <3075000>; 192*5dbadc84SHeiko Thiery regulator-max-microvolt = <3625000>; 193*5dbadc84SHeiko Thiery regulator-always-on; 194*5dbadc84SHeiko Thiery }; 195*5dbadc84SHeiko Thiery 196*5dbadc84SHeiko Thiery vgen6_reg: vgen6 { 197*5dbadc84SHeiko Thiery regulator-name = "V_2V8_CAM"; 198*5dbadc84SHeiko Thiery regulator-min-microvolt = <1800000>; 199*5dbadc84SHeiko Thiery regulator-max-microvolt = <3300000>; 200*5dbadc84SHeiko Thiery regulator-always-on; 201*5dbadc84SHeiko Thiery }; 202*5dbadc84SHeiko Thiery }; 203*5dbadc84SHeiko Thiery }; 204*5dbadc84SHeiko Thiery 205*5dbadc84SHeiko Thiery fan-controller@1b { 206*5dbadc84SHeiko Thiery compatible = "maxim,max6650"; 207*5dbadc84SHeiko Thiery reg = <0x1b>; 208*5dbadc84SHeiko Thiery maxim,fan-microvolt = <5000000>; 209*5dbadc84SHeiko Thiery }; 210*5dbadc84SHeiko Thiery 211*5dbadc84SHeiko Thiery rtc@32 { 212*5dbadc84SHeiko Thiery compatible = "microcrystal,rv8803"; 213*5dbadc84SHeiko Thiery reg = <0x32>; 214*5dbadc84SHeiko Thiery }; 215*5dbadc84SHeiko Thiery 216*5dbadc84SHeiko Thiery sensor@4b { 217*5dbadc84SHeiko Thiery compatible = "national,lm75b"; 218*5dbadc84SHeiko Thiery reg = <0x4b>; 219*5dbadc84SHeiko Thiery }; 220*5dbadc84SHeiko Thiery 221*5dbadc84SHeiko Thiery eeprom@51 { 222*5dbadc84SHeiko Thiery compatible = "atmel,24c32"; 223*5dbadc84SHeiko Thiery reg = <0x51>; 224*5dbadc84SHeiko Thiery pagesize = <32>; 225*5dbadc84SHeiko Thiery }; 226*5dbadc84SHeiko Thiery}; 227*5dbadc84SHeiko Thiery 228*5dbadc84SHeiko Thiery&i2c2 { 229*5dbadc84SHeiko Thiery clock-frequency = <100000>; 230*5dbadc84SHeiko Thiery pinctrl-names = "default"; 231*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_i2c2>; 232*5dbadc84SHeiko Thiery status = "okay"; 233*5dbadc84SHeiko Thiery}; 234*5dbadc84SHeiko Thiery 235*5dbadc84SHeiko Thiery&i2c3 { 236*5dbadc84SHeiko Thiery clock-frequency = <100000>; 237*5dbadc84SHeiko Thiery pinctrl-names = "default"; 238*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_i2c3>; 239*5dbadc84SHeiko Thiery status = "okay"; 240*5dbadc84SHeiko Thiery}; 241*5dbadc84SHeiko Thiery 242*5dbadc84SHeiko Thiery/* M.2 B-key slot */ 243*5dbadc84SHeiko Thiery&pcie0 { 244*5dbadc84SHeiko Thiery pinctrl-names = "default"; 245*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_pcie0>; 246*5dbadc84SHeiko Thiery reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; 247*5dbadc84SHeiko Thiery clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 248*5dbadc84SHeiko Thiery <&clk IMX8MQ_CLK_PCIE1_AUX>, 249*5dbadc84SHeiko Thiery <&clk IMX8MQ_CLK_PCIE1_PHY>, 250*5dbadc84SHeiko Thiery <&pcie0_refclk>; 251*5dbadc84SHeiko Thiery clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; 252*5dbadc84SHeiko Thiery status = "okay"; 253*5dbadc84SHeiko Thiery}; 254*5dbadc84SHeiko Thiery 255*5dbadc84SHeiko Thiery/* Intel Ethernet Controller I210/I211 */ 256*5dbadc84SHeiko Thiery&pcie1 { 257*5dbadc84SHeiko Thiery clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 258*5dbadc84SHeiko Thiery <&clk IMX8MQ_CLK_PCIE2_AUX>, 259*5dbadc84SHeiko Thiery <&clk IMX8MQ_CLK_PCIE2_PHY>, 260*5dbadc84SHeiko Thiery <&pcie1_refclk>; 261*5dbadc84SHeiko Thiery clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; 262*5dbadc84SHeiko Thiery fsl,max-link-speed = <1>; 263*5dbadc84SHeiko Thiery status = "okay"; 264*5dbadc84SHeiko Thiery}; 265*5dbadc84SHeiko Thiery 266*5dbadc84SHeiko Thiery&pgc_gpu { 267*5dbadc84SHeiko Thiery power-supply = <&sw1a_reg>; 268*5dbadc84SHeiko Thiery}; 269*5dbadc84SHeiko Thiery 270*5dbadc84SHeiko Thiery&pgc_vpu { 271*5dbadc84SHeiko Thiery power-supply = <&sw1c_reg>; 272*5dbadc84SHeiko Thiery}; 273*5dbadc84SHeiko Thiery 274*5dbadc84SHeiko Thiery&qspi0 { 275*5dbadc84SHeiko Thiery pinctrl-names = "default"; 276*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_qspi>; 277*5dbadc84SHeiko Thiery status = "okay"; 278*5dbadc84SHeiko Thiery 279*5dbadc84SHeiko Thiery flash@0 { 280*5dbadc84SHeiko Thiery compatible = "jedec,spi-nor"; 281*5dbadc84SHeiko Thiery #address-cells = <1>; 282*5dbadc84SHeiko Thiery #size-cells = <1>; 283*5dbadc84SHeiko Thiery reg = <0>; 284*5dbadc84SHeiko Thiery spi-tx-bus-width = <4>; 285*5dbadc84SHeiko Thiery spi-rx-bus-width = <4>; 286*5dbadc84SHeiko Thiery m25p,fast-read; 287*5dbadc84SHeiko Thiery spi-max-frequency = <50000000>; 288*5dbadc84SHeiko Thiery }; 289*5dbadc84SHeiko Thiery}; 290*5dbadc84SHeiko Thiery 291*5dbadc84SHeiko Thiery&snvs_pwrkey { 292*5dbadc84SHeiko Thiery status = "okay"; 293*5dbadc84SHeiko Thiery}; 294*5dbadc84SHeiko Thiery 295*5dbadc84SHeiko Thiery&uart1 { 296*5dbadc84SHeiko Thiery pinctrl-names = "default"; 297*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_uart1>; 298*5dbadc84SHeiko Thiery assigned-clocks = <&clk IMX8MQ_CLK_UART1>; 299*5dbadc84SHeiko Thiery assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 300*5dbadc84SHeiko Thiery status = "okay"; 301*5dbadc84SHeiko Thiery}; 302*5dbadc84SHeiko Thiery 303*5dbadc84SHeiko Thiery&uart2 { 304*5dbadc84SHeiko Thiery pinctrl-names = "default"; 305*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_uart2>; 306*5dbadc84SHeiko Thiery assigned-clocks = <&clk IMX8MQ_CLK_UART2>; 307*5dbadc84SHeiko Thiery assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 308*5dbadc84SHeiko Thiery status = "okay"; 309*5dbadc84SHeiko Thiery}; 310*5dbadc84SHeiko Thiery 311*5dbadc84SHeiko Thiery&uart3 { 312*5dbadc84SHeiko Thiery pinctrl-names = "default"; 313*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_uart3>; 314*5dbadc84SHeiko Thiery fsl,uart-has-rtscts; 315*5dbadc84SHeiko Thiery assigned-clocks = <&clk IMX8MQ_CLK_UART3>; 316*5dbadc84SHeiko Thiery assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; 317*5dbadc84SHeiko Thiery status = "okay"; 318*5dbadc84SHeiko Thiery}; 319*5dbadc84SHeiko Thiery 320*5dbadc84SHeiko Thiery&usb3_phy0 { 321*5dbadc84SHeiko Thiery status = "okay"; 322*5dbadc84SHeiko Thiery}; 323*5dbadc84SHeiko Thiery 324*5dbadc84SHeiko Thiery&usb3_phy1 { 325*5dbadc84SHeiko Thiery status = "okay"; 326*5dbadc84SHeiko Thiery}; 327*5dbadc84SHeiko Thiery 328*5dbadc84SHeiko Thiery&usb_dwc3_0 { 329*5dbadc84SHeiko Thiery pinctrl-names = "default"; 330*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_usb0>; 331*5dbadc84SHeiko Thiery dr_mode = "otg"; 332*5dbadc84SHeiko Thiery hnp-disable; 333*5dbadc84SHeiko Thiery srp-disable; 334*5dbadc84SHeiko Thiery adp-disable; 335*5dbadc84SHeiko Thiery maximum-speed = "high-speed"; 336*5dbadc84SHeiko Thiery status = "okay"; 337*5dbadc84SHeiko Thiery}; 338*5dbadc84SHeiko Thiery 339*5dbadc84SHeiko Thiery&usb_dwc3_1 { 340*5dbadc84SHeiko Thiery dr_mode = "host"; 341*5dbadc84SHeiko Thiery status = "okay"; 342*5dbadc84SHeiko Thiery}; 343*5dbadc84SHeiko Thiery 344*5dbadc84SHeiko Thiery&usdhc1 { 345*5dbadc84SHeiko Thiery assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 346*5dbadc84SHeiko Thiery assigned-clock-rates = <400000000>; 347*5dbadc84SHeiko Thiery pinctrl-names = "default", "state_100mhz", "state_200mhz"; 348*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_usdhc1>; 349*5dbadc84SHeiko Thiery pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 350*5dbadc84SHeiko Thiery pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 351*5dbadc84SHeiko Thiery vqmmc-supply = <&sw4_reg>; 352*5dbadc84SHeiko Thiery bus-width = <8>; 353*5dbadc84SHeiko Thiery non-removable; 354*5dbadc84SHeiko Thiery no-sd; 355*5dbadc84SHeiko Thiery no-sdio; 356*5dbadc84SHeiko Thiery status = "okay"; 357*5dbadc84SHeiko Thiery}; 358*5dbadc84SHeiko Thiery 359*5dbadc84SHeiko Thiery&usdhc2 { 360*5dbadc84SHeiko Thiery assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 361*5dbadc84SHeiko Thiery assigned-clock-rates = <200000000>; 362*5dbadc84SHeiko Thiery pinctrl-names = "default", "state_100mhz", "state_200mhz"; 363*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 364*5dbadc84SHeiko Thiery pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 365*5dbadc84SHeiko Thiery pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 366*5dbadc84SHeiko Thiery bus-width = <4>; 367*5dbadc84SHeiko Thiery cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 368*5dbadc84SHeiko Thiery wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 369*5dbadc84SHeiko Thiery vmmc-supply = <®_usdhc2_vmmc>; 370*5dbadc84SHeiko Thiery status = "okay"; 371*5dbadc84SHeiko Thiery}; 372*5dbadc84SHeiko Thiery 373*5dbadc84SHeiko Thiery&wdog1 { 374*5dbadc84SHeiko Thiery pinctrl-names = "default"; 375*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_wdog>; 376*5dbadc84SHeiko Thiery fsl,ext-reset-output; 377*5dbadc84SHeiko Thiery status = "okay"; 378*5dbadc84SHeiko Thiery}; 379*5dbadc84SHeiko Thiery 380*5dbadc84SHeiko Thiery&iomuxc { 381*5dbadc84SHeiko Thiery pinctrl-names = "default"; 382*5dbadc84SHeiko Thiery pinctrl-0 = <&pinctrl_hog>; 383*5dbadc84SHeiko Thiery 384*5dbadc84SHeiko Thiery pinctrl_hog: hoggrp { 385*5dbadc84SHeiko Thiery fsl,pins = < 386*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */ 387*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */ 388*5dbadc84SHeiko Thiery >; 389*5dbadc84SHeiko Thiery }; 390*5dbadc84SHeiko Thiery 391*5dbadc84SHeiko Thiery pinctrl_gpio: gpiogrp { 392*5dbadc84SHeiko Thiery fsl,pins = < 393*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */ 394*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */ 395*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */ 396*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */ 397*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */ 398*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */ 399*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */ 400*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */ 401*5dbadc84SHeiko Thiery >; 402*5dbadc84SHeiko Thiery }; 403*5dbadc84SHeiko Thiery 404*5dbadc84SHeiko Thiery pinctrl_pcie0: pcie0grp { 405*5dbadc84SHeiko Thiery fsl,pins = < 406*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */ 407*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */ 408*5dbadc84SHeiko Thiery >; 409*5dbadc84SHeiko Thiery }; 410*5dbadc84SHeiko Thiery 411*5dbadc84SHeiko Thiery pinctrl_reg_usdhc2: regusdhc2gpiogrp { 412*5dbadc84SHeiko Thiery fsl,pins = < 413*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 414*5dbadc84SHeiko Thiery >; 415*5dbadc84SHeiko Thiery }; 416*5dbadc84SHeiko Thiery 417*5dbadc84SHeiko Thiery pinctrl_fec1: fec1grp { 418*5dbadc84SHeiko Thiery fsl,pins = < 419*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 420*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 421*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 422*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 423*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 424*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 425*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 426*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 427*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 428*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 429*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 430*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 431*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 432*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 433*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 434*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 435*5dbadc84SHeiko Thiery >; 436*5dbadc84SHeiko Thiery }; 437*5dbadc84SHeiko Thiery 438*5dbadc84SHeiko Thiery pinctrl_i2c1: i2c1grp { 439*5dbadc84SHeiko Thiery fsl,pins = < 440*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 441*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 442*5dbadc84SHeiko Thiery >; 443*5dbadc84SHeiko Thiery }; 444*5dbadc84SHeiko Thiery 445*5dbadc84SHeiko Thiery pinctrl_i2c2: i2c2grp { 446*5dbadc84SHeiko Thiery fsl,pins = < 447*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f 448*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f 449*5dbadc84SHeiko Thiery >; 450*5dbadc84SHeiko Thiery }; 451*5dbadc84SHeiko Thiery 452*5dbadc84SHeiko Thiery pinctrl_i2c3: i2c3grp { 453*5dbadc84SHeiko Thiery fsl,pins = < 454*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f 455*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f 456*5dbadc84SHeiko Thiery >; 457*5dbadc84SHeiko Thiery }; 458*5dbadc84SHeiko Thiery 459*5dbadc84SHeiko Thiery pinctrl_qspi: qspigrp { 460*5dbadc84SHeiko Thiery fsl,pins = < 461*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 462*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 463*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 464*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 465*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 466*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 467*5dbadc84SHeiko Thiery >; 468*5dbadc84SHeiko Thiery }; 469*5dbadc84SHeiko Thiery 470*5dbadc84SHeiko Thiery pinctrl_ecspi2: ecspi2grp { 471*5dbadc84SHeiko Thiery fsl,pins = < 472*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 473*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 474*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 475*5dbadc84SHeiko Thiery >; 476*5dbadc84SHeiko Thiery }; 477*5dbadc84SHeiko Thiery 478*5dbadc84SHeiko Thiery pinctrl_ecspi2_cs: ecspi2csgrp { 479*5dbadc84SHeiko Thiery fsl,pins = < 480*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 481*5dbadc84SHeiko Thiery >; 482*5dbadc84SHeiko Thiery }; 483*5dbadc84SHeiko Thiery 484*5dbadc84SHeiko Thiery pinctrl_uart1: uart1grp { 485*5dbadc84SHeiko Thiery fsl,pins = < 486*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 487*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 488*5dbadc84SHeiko Thiery >; 489*5dbadc84SHeiko Thiery }; 490*5dbadc84SHeiko Thiery 491*5dbadc84SHeiko Thiery pinctrl_uart2: uart2grp { 492*5dbadc84SHeiko Thiery fsl,pins = < 493*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 494*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 495*5dbadc84SHeiko Thiery >; 496*5dbadc84SHeiko Thiery }; 497*5dbadc84SHeiko Thiery 498*5dbadc84SHeiko Thiery pinctrl_uart3: uart3grp { 499*5dbadc84SHeiko Thiery fsl,pins = < 500*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 501*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 502*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 503*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 504*5dbadc84SHeiko Thiery >; 505*5dbadc84SHeiko Thiery }; 506*5dbadc84SHeiko Thiery 507*5dbadc84SHeiko Thiery pinctrl_usdhc1: usdhc1grp { 508*5dbadc84SHeiko Thiery fsl,pins = < 509*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 510*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 511*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 512*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 513*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 514*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 515*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 516*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 517*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 518*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 519*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 520*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 521*5dbadc84SHeiko Thiery >; 522*5dbadc84SHeiko Thiery }; 523*5dbadc84SHeiko Thiery 524*5dbadc84SHeiko Thiery pinctrl_usdhc1_100mhz: usdhc1-100grp { 525*5dbadc84SHeiko Thiery fsl,pins = < 526*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 527*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 528*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 529*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 530*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 531*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 532*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 533*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 534*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 535*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 536*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 537*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 538*5dbadc84SHeiko Thiery >; 539*5dbadc84SHeiko Thiery }; 540*5dbadc84SHeiko Thiery 541*5dbadc84SHeiko Thiery pinctrl_usdhc1_200mhz: usdhc1-200grp { 542*5dbadc84SHeiko Thiery fsl,pins = < 543*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 544*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 545*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 546*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 547*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 548*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 549*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 550*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 551*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 552*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 553*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 554*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 555*5dbadc84SHeiko Thiery >; 556*5dbadc84SHeiko Thiery }; 557*5dbadc84SHeiko Thiery 558*5dbadc84SHeiko Thiery pinctrl_usdhc2_gpio: usdhc2gpiogrp { 559*5dbadc84SHeiko Thiery fsl,pins = < 560*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 561*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19 562*5dbadc84SHeiko Thiery >; 563*5dbadc84SHeiko Thiery }; 564*5dbadc84SHeiko Thiery 565*5dbadc84SHeiko Thiery pinctrl_usdhc2: usdhc2grp { 566*5dbadc84SHeiko Thiery fsl,pins = < 567*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 568*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 569*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 570*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 571*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 572*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 573*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 574*5dbadc84SHeiko Thiery >; 575*5dbadc84SHeiko Thiery }; 576*5dbadc84SHeiko Thiery 577*5dbadc84SHeiko Thiery pinctrl_usdhc2_100mhz: usdhc2-100grp { 578*5dbadc84SHeiko Thiery fsl,pins = < 579*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 580*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 581*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 582*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 583*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 584*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 585*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 586*5dbadc84SHeiko Thiery >; 587*5dbadc84SHeiko Thiery }; 588*5dbadc84SHeiko Thiery 589*5dbadc84SHeiko Thiery pinctrl_usdhc2_200mhz: usdhc2-200grp { 590*5dbadc84SHeiko Thiery fsl,pins = < 591*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 592*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf 593*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf 594*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf 595*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf 596*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf 597*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 598*5dbadc84SHeiko Thiery >; 599*5dbadc84SHeiko Thiery }; 600*5dbadc84SHeiko Thiery 601*5dbadc84SHeiko Thiery pinctrl_usb0: usb0grp { 602*5dbadc84SHeiko Thiery fsl,pins = < 603*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19 604*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 605*5dbadc84SHeiko Thiery >; 606*5dbadc84SHeiko Thiery }; 607*5dbadc84SHeiko Thiery 608*5dbadc84SHeiko Thiery pinctrl_wdog: wdoggrp { 609*5dbadc84SHeiko Thiery fsl,pins = < 610*5dbadc84SHeiko Thiery MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 611*5dbadc84SHeiko Thiery >; 612*5dbadc84SHeiko Thiery }; 613*5dbadc84SHeiko Thiery}; 614