1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7/dts-v1/;
8
9#include "imx8mq.dtsi"
10
11/ {
12	model = "NXP i.MX8MQ EVK";
13	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x00000000 0x40000000 0 0xc0000000>;
22	};
23
24	pcie0_refclk: pcie0-refclk {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <100000000>;
28	};
29
30	reg_pcie1: regulator-pcie {
31		compatible = "regulator-fixed";
32		pinctrl-names = "default";
33		pinctrl-0 = <&pinctrl_pcie1_reg>;
34		regulator-name = "MPCIE_3V3";
35		regulator-min-microvolt = <3300000>;
36		regulator-max-microvolt = <3300000>;
37		gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
38		enable-active-high;
39	};
40
41	reg_usdhc2_vmmc: regulator-vsd-3v3 {
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_reg_usdhc2>;
44		compatible = "regulator-fixed";
45		regulator-name = "VSD_3V3";
46		regulator-min-microvolt = <3300000>;
47		regulator-max-microvolt = <3300000>;
48		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
49		enable-active-high;
50	};
51
52	buck2_reg: regulator-buck2 {
53		pinctrl-names = "default";
54		pinctrl-0 = <&pinctrl_buck2>;
55		compatible = "regulator-gpio";
56		regulator-name = "vdd_arm";
57		regulator-min-microvolt = <900000>;
58		regulator-max-microvolt = <1000000>;
59		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
60		states = <1000000 0x0
61			  900000 0x1>;
62		regulator-boot-on;
63		regulator-always-on;
64	};
65
66	ir-receiver {
67		compatible = "gpio-ir-receiver";
68		gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
69		pinctrl-names = "default";
70		pinctrl-0 = <&pinctrl_ir>;
71		linux,autosuspend-period = <125>;
72	};
73
74	wm8524: audio-codec {
75		#sound-dai-cells = <0>;
76		compatible = "wlf,wm8524";
77		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
78	};
79
80	sound-wm8524 {
81		compatible = "simple-audio-card";
82		simple-audio-card,name = "wm8524-audio";
83		simple-audio-card,format = "i2s";
84		simple-audio-card,frame-master = <&cpudai>;
85		simple-audio-card,bitclock-master = <&cpudai>;
86		simple-audio-card,widgets =
87			"Line", "Left Line Out Jack",
88			"Line", "Right Line Out Jack";
89		simple-audio-card,routing =
90			"Left Line Out Jack", "LINEVOUTL",
91			"Right Line Out Jack", "LINEVOUTR";
92
93		cpudai: simple-audio-card,cpu {
94			sound-dai = <&sai2>;
95		};
96
97		link_codec: simple-audio-card,codec {
98			sound-dai = <&wm8524>;
99			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
100		};
101	};
102
103	sound-spdif {
104		compatible = "fsl,imx-audio-spdif";
105		model = "imx-spdif";
106		spdif-controller = <&spdif1>;
107		spdif-out;
108		spdif-in;
109	};
110
111	sound-hdmi-arc {
112		compatible = "fsl,imx-audio-spdif";
113		model = "imx-hdmi-arc";
114		spdif-controller = <&spdif2>;
115		spdif-in;
116	};
117};
118
119&A53_0 {
120	cpu-supply = <&buck2_reg>;
121};
122
123&A53_1 {
124	cpu-supply = <&buck2_reg>;
125};
126
127&A53_2 {
128	cpu-supply = <&buck2_reg>;
129};
130
131&A53_3 {
132	cpu-supply = <&buck2_reg>;
133};
134
135&ddrc {
136	operating-points-v2 = <&ddrc_opp_table>;
137	status = "okay";
138
139	ddrc_opp_table: opp-table {
140		compatible = "operating-points-v2";
141
142		opp-25M {
143			opp-hz = /bits/ 64 <25000000>;
144		};
145
146		opp-100M {
147			opp-hz = /bits/ 64 <100000000>;
148		};
149
150		/*
151		 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
152		 */
153		opp-166M {
154			opp-hz = /bits/ 64 <166935483>;
155		};
156
157		opp-800M {
158			opp-hz = /bits/ 64 <800000000>;
159		};
160	};
161};
162
163&dphy {
164	status = "okay";
165};
166
167&fec1 {
168	pinctrl-names = "default";
169	pinctrl-0 = <&pinctrl_fec1>;
170	phy-mode = "rgmii-id";
171	phy-handle = <&ethphy0>;
172	fsl,magic-packet;
173	status = "okay";
174
175	mdio {
176		#address-cells = <1>;
177		#size-cells = <0>;
178
179		ethphy0: ethernet-phy@0 {
180			compatible = "ethernet-phy-ieee802.3-c22";
181			reg = <0>;
182			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
183			reset-assert-us = <10000>;
184			qca,disable-smarteee;
185			vddio-supply = <&vddh>;
186
187			vddh: vddh-regulator {
188			};
189		};
190	};
191};
192
193&gpio5 {
194	pinctrl-names = "default";
195	pinctrl-0 = <&pinctrl_wifi_reset>;
196
197	wl-reg-on-hog {
198		gpio-hog;
199		gpios = <29 GPIO_ACTIVE_HIGH>;
200		output-high;
201	};
202};
203
204&i2c1 {
205	clock-frequency = <100000>;
206	pinctrl-names = "default";
207	pinctrl-0 = <&pinctrl_i2c1>;
208	status = "okay";
209
210	pmic@8 {
211		compatible = "fsl,pfuze100";
212		reg = <0x8>;
213
214		regulators {
215			sw1a_reg: sw1ab {
216				regulator-min-microvolt = <825000>;
217				regulator-max-microvolt = <1100000>;
218			};
219
220			sw1c_reg: sw1c {
221				regulator-min-microvolt = <825000>;
222				regulator-max-microvolt = <1100000>;
223			};
224
225			sw2_reg: sw2 {
226				regulator-min-microvolt = <1100000>;
227				regulator-max-microvolt = <1100000>;
228				regulator-always-on;
229			};
230
231			sw3a_reg: sw3ab {
232				regulator-min-microvolt = <825000>;
233				regulator-max-microvolt = <1100000>;
234				regulator-always-on;
235			};
236
237			sw4_reg: sw4 {
238				regulator-min-microvolt = <1800000>;
239				regulator-max-microvolt = <1800000>;
240				regulator-always-on;
241			};
242
243			swbst_reg: swbst {
244				regulator-min-microvolt = <5000000>;
245				regulator-max-microvolt = <5150000>;
246			};
247
248			snvs_reg: vsnvs {
249				regulator-min-microvolt = <1000000>;
250				regulator-max-microvolt = <3000000>;
251				regulator-always-on;
252			};
253
254			vref_reg: vrefddr {
255				regulator-always-on;
256			};
257
258			vgen1_reg: vgen1 {
259				regulator-min-microvolt = <800000>;
260				regulator-max-microvolt = <1550000>;
261			};
262
263			vgen2_reg: vgen2 {
264				regulator-min-microvolt = <850000>;
265				regulator-max-microvolt = <975000>;
266				regulator-always-on;
267			};
268
269			vgen3_reg: vgen3 {
270				regulator-min-microvolt = <1675000>;
271				regulator-max-microvolt = <1975000>;
272				regulator-always-on;
273			};
274
275			vgen4_reg: vgen4 {
276				regulator-min-microvolt = <1625000>;
277				regulator-max-microvolt = <1875000>;
278				regulator-always-on;
279			};
280
281			vgen5_reg: vgen5 {
282				regulator-min-microvolt = <3075000>;
283				regulator-max-microvolt = <3625000>;
284				regulator-always-on;
285			};
286
287			vgen6_reg: vgen6 {
288				regulator-min-microvolt = <1800000>;
289				regulator-max-microvolt = <3300000>;
290			};
291		};
292	};
293};
294
295&lcdif {
296	status = "okay";
297};
298
299&mipi_dsi {
300	#address-cells = <1>;
301	#size-cells = <0>;
302	status = "okay";
303
304	panel@0 {
305		pinctrl-0 = <&pinctrl_mipi_dsi>;
306		pinctrl-names = "default";
307		compatible = "raydium,rm67191";
308		reg = <0>;
309		reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
310		dsi-lanes = <4>;
311
312		port {
313			panel_in: endpoint {
314				remote-endpoint = <&mipi_dsi_out>;
315			};
316		};
317	};
318
319	ports {
320		port@1 {
321			reg = <1>;
322			mipi_dsi_out: endpoint {
323				remote-endpoint = <&panel_in>;
324			};
325		};
326	};
327};
328
329&pcie0 {
330	pinctrl-names = "default";
331	pinctrl-0 = <&pinctrl_pcie0>;
332	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
333	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
334		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
335		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
336		 <&pcie0_refclk>;
337	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
338	vph-supply = <&vgen5_reg>;
339	status = "okay";
340};
341
342&pcie1 {
343	pinctrl-names = "default";
344	pinctrl-0 = <&pinctrl_pcie1>;
345	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
346	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
347		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
348		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
349		 <&pcie0_refclk>;
350	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
351	vpcie-supply = <&reg_pcie1>;
352	vph-supply = <&vgen5_reg>;
353	status = "okay";
354};
355
356&pgc_gpu {
357	power-supply = <&sw1a_reg>;
358};
359
360&pgc_vpu {
361	power-supply = <&sw1c_reg>;
362};
363
364&qspi0 {
365	pinctrl-names = "default";
366	pinctrl-0 = <&pinctrl_qspi>;
367	status = "okay";
368
369	n25q256a: flash@0 {
370		reg = <0>;
371		#address-cells = <1>;
372		#size-cells = <1>;
373		compatible = "micron,n25q256a", "jedec,spi-nor";
374		spi-max-frequency = <29000000>;
375		spi-tx-bus-width = <1>;
376		spi-rx-bus-width = <4>;
377	};
378};
379
380&sai2 {
381	pinctrl-names = "default";
382	pinctrl-0 = <&pinctrl_sai2>;
383	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
384	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
385	assigned-clock-rates = <0>, <24576000>;
386	status = "okay";
387};
388
389&snvs_pwrkey {
390	status = "okay";
391};
392
393&spdif1 {
394	pinctrl-names = "default";
395	pinctrl-0 = <&pinctrl_spdif1>;
396	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
397	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
398	assigned-clock-rates = <24576000>;
399	status = "okay";
400};
401
402&spdif2 {
403	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
404	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
405	assigned-clock-rates = <24576000>;
406	status = "okay";
407};
408
409&uart1 {
410	pinctrl-names = "default";
411	pinctrl-0 = <&pinctrl_uart1>;
412	status = "okay";
413};
414
415&usb3_phy1 {
416	status = "okay";
417};
418
419&usb_dwc3_1 {
420	dr_mode = "host";
421	status = "okay";
422};
423
424&usdhc1 {
425	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
426	assigned-clock-rates = <400000000>;
427	pinctrl-names = "default", "state_100mhz", "state_200mhz";
428	pinctrl-0 = <&pinctrl_usdhc1>;
429	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
430	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
431	vqmmc-supply = <&sw4_reg>;
432	bus-width = <8>;
433	non-removable;
434	no-sd;
435	no-sdio;
436	status = "okay";
437};
438
439&usdhc2 {
440	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
441	assigned-clock-rates = <200000000>;
442	pinctrl-names = "default", "state_100mhz", "state_200mhz";
443	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
444	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
445	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
446	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
447	vmmc-supply = <&reg_usdhc2_vmmc>;
448	status = "okay";
449};
450
451&wdog1 {
452	pinctrl-names = "default";
453	pinctrl-0 = <&pinctrl_wdog>;
454	fsl,ext-reset-output;
455	status = "okay";
456};
457
458&iomuxc {
459	pinctrl_buck2: vddarmgrp {
460		fsl,pins = <
461			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
462		>;
463	};
464
465	pinctrl_fec1: fec1grp {
466		fsl,pins = <
467			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
468			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
469			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
470			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
471			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
472			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
473			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
474			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
475			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
476			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
477			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
478			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
479			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
480			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
481			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
482		>;
483	};
484
485	pinctrl_i2c1: i2c1grp {
486		fsl,pins = <
487			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
488			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
489		>;
490	};
491
492	pinctrl_ir: irgrp {
493		fsl,pins = <
494			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x4f
495		>;
496	};
497
498	pinctrl_mipi_dsi: mipidsigrp {
499		fsl,pins = <
500			MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6		0x16
501		>;
502	};
503
504	pinctrl_pcie0: pcie0grp {
505		fsl,pins = <
506			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76
507			MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28		0x16
508		>;
509	};
510
511	pinctrl_pcie1: pcie1grp {
512		fsl,pins = <
513			MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B		0x76
514			MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12		0x16
515		>;
516	};
517
518	pinctrl_pcie1_reg: pcie1reggrp {
519		fsl,pins = <
520			MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x16
521		>;
522	};
523
524	pinctrl_qspi: qspigrp {
525		fsl,pins = <
526			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
527			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
528			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
529			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
530			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
531			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
532		>;
533	};
534
535	pinctrl_reg_usdhc2: regusdhc2gpiogrp {
536		fsl,pins = <
537			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
538		>;
539	};
540
541	pinctrl_sai2: sai2grp {
542		fsl,pins = <
543			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
544			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
545			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
546			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
547			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
548		>;
549	};
550
551	pinctrl_spdif1: spdif1grp {
552		fsl,pins = <
553			MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
554			MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
555		>;
556	};
557
558	pinctrl_uart1: uart1grp {
559		fsl,pins = <
560			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
561			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
562		>;
563	};
564
565	pinctrl_usdhc1: usdhc1grp {
566		fsl,pins = <
567			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
568			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
569			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
570			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
571			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
572			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
573			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
574			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
575			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
576			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
577			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
578			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
579		>;
580	};
581
582	pinctrl_usdhc1_100mhz: usdhc1-100grp {
583		fsl,pins = <
584			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
585			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
586			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
587			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
588			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
589			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
590			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
591			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
592			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
593			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
594			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
595			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
596		>;
597	};
598
599	pinctrl_usdhc1_200mhz: usdhc1-200grp {
600		fsl,pins = <
601			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
602			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
603			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
604			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
605			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
606			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
607			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
608			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
609			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
610			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
611			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
612			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
613		>;
614	};
615
616	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
617		fsl,pins = <
618			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41
619		>;
620	};
621
622	pinctrl_usdhc2: usdhc2grp {
623		fsl,pins = <
624			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
625			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
626			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
627			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
628			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
629			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
630			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
631		>;
632	};
633
634	pinctrl_usdhc2_100mhz: usdhc2-100grp {
635		fsl,pins = <
636			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
637			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
638			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
639			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
640			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
641			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
642			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
643		>;
644	};
645
646	pinctrl_usdhc2_200mhz: usdhc2-200grp {
647		fsl,pins = <
648			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
649			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
650			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
651			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
652			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
653			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
654			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
655		>;
656	};
657
658	pinctrl_wdog: wdog1grp {
659		fsl,pins = <
660			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
661		>;
662	};
663
664	pinctrl_wifi_reset: wifiresetgrp {
665		fsl,pins = <
666			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16
667		>;
668	};
669};
670