1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7/dts-v1/;
8
9#include "imx8mq.dtsi"
10
11/ {
12	model = "NXP i.MX8MQ EVK";
13	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x00000000 0x40000000 0 0xc0000000>;
22	};
23
24	reg_usdhc2_vmmc: regulator-vsd-3v3 {
25		pinctrl-names = "default";
26		pinctrl-0 = <&pinctrl_reg_usdhc2>;
27		compatible = "regulator-fixed";
28		regulator-name = "VSD_3V3";
29		regulator-min-microvolt = <3300000>;
30		regulator-max-microvolt = <3300000>;
31		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
32		enable-active-high;
33	};
34};
35
36&fec1 {
37	pinctrl-names = "default";
38	pinctrl-0 = <&pinctrl_fec1>;
39	phy-mode = "rgmii-id";
40	phy-handle = <&ethphy0>;
41	fsl,magic-packet;
42	status = "okay";
43
44	mdio {
45		#address-cells = <1>;
46		#size-cells = <0>;
47
48		ethphy0: ethernet-phy@0 {
49			compatible = "ethernet-phy-ieee802.3-c22";
50			reg = <0>;
51		};
52	};
53};
54
55&i2c1 {
56	clock-frequency = <100000>;
57	pinctrl-names = "default";
58	pinctrl-0 = <&pinctrl_i2c1>;
59	status = "okay";
60
61	pmic@8 {
62		compatible = "fsl,pfuze100";
63		reg = <0x8>;
64
65		regulators {
66			sw1a_reg: sw1ab {
67				regulator-min-microvolt = <825000>;
68				regulator-max-microvolt = <1100000>;
69			};
70
71			sw1c_reg: sw1c {
72				regulator-min-microvolt = <825000>;
73				regulator-max-microvolt = <1100000>;
74			};
75
76			sw2_reg: sw2 {
77				regulator-min-microvolt = <1100000>;
78				regulator-max-microvolt = <1100000>;
79				regulator-always-on;
80			};
81
82			sw3a_reg: sw3ab {
83				regulator-min-microvolt = <825000>;
84				regulator-max-microvolt = <1100000>;
85				regulator-always-on;
86			};
87
88			sw4_reg: sw4 {
89				regulator-min-microvolt = <1800000>;
90				regulator-max-microvolt = <1800000>;
91				regulator-always-on;
92			};
93
94			swbst_reg: swbst {
95				regulator-min-microvolt = <5000000>;
96				regulator-max-microvolt = <5150000>;
97			};
98
99			snvs_reg: vsnvs {
100				regulator-min-microvolt = <1000000>;
101				regulator-max-microvolt = <3000000>;
102				regulator-always-on;
103			};
104
105			vref_reg: vrefddr {
106				regulator-always-on;
107			};
108
109			vgen1_reg: vgen1 {
110				regulator-min-microvolt = <800000>;
111				regulator-max-microvolt = <1550000>;
112			};
113
114			vgen2_reg: vgen2 {
115				regulator-min-microvolt = <850000>;
116				regulator-max-microvolt = <975000>;
117				regulator-always-on;
118			};
119
120			vgen3_reg: vgen3 {
121				regulator-min-microvolt = <1675000>;
122				regulator-max-microvolt = <1975000>;
123				regulator-always-on;
124			};
125
126			vgen4_reg: vgen4 {
127				regulator-min-microvolt = <1625000>;
128				regulator-max-microvolt = <1875000>;
129				regulator-always-on;
130			};
131
132			vgen5_reg: vgen5 {
133				regulator-min-microvolt = <3075000>;
134				regulator-max-microvolt = <3625000>;
135				regulator-always-on;
136			};
137
138			vgen6_reg: vgen6 {
139				regulator-min-microvolt = <1800000>;
140				regulator-max-microvolt = <3300000>;
141			};
142		};
143	};
144};
145
146&uart1 {
147	pinctrl-names = "default";
148	pinctrl-0 = <&pinctrl_uart1>;
149	status = "okay";
150};
151
152&usb3_phy1 {
153	status = "okay";
154};
155
156&usb_dwc3_1 {
157	dr_mode = "host";
158	status = "okay";
159};
160
161&qspi0 {
162	pinctrl-names = "default";
163	pinctrl-0 = <&pinctrl_qspi>;
164	status = "okay";
165
166	n25q256a: flash@0 {
167		reg = <0>;
168		#address-cells = <1>;
169		#size-cells = <1>;
170		compatible = "micron,n25q256a", "jedec,spi-nor";
171		spi-max-frequency = <29000000>;
172	};
173};
174
175&usdhc1 {
176	pinctrl-names = "default", "state_100mhz", "state_200mhz";
177	pinctrl-0 = <&pinctrl_usdhc1>;
178	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
179	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
180	vqmmc-supply = <&sw4_reg>;
181	bus-width = <8>;
182	non-removable;
183	no-sd;
184	no-sdio;
185	status = "okay";
186};
187
188&usdhc2 {
189	pinctrl-names = "default", "state_100mhz", "state_200mhz";
190	pinctrl-0 = <&pinctrl_usdhc2>;
191	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
192	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
193	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
194	vmmc-supply = <&reg_usdhc2_vmmc>;
195	status = "okay";
196};
197
198&wdog1 {
199	pinctrl-names = "default";
200	pinctrl-0 = <&pinctrl_wdog>;
201	fsl,ext-reset-output;
202	status = "okay";
203};
204
205&iomuxc {
206	pinctrl_fec1: fec1grp {
207		fsl,pins = <
208			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
209			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
210			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
211			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
212			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
213			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
214			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
215			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
216			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
217			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
218			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
219			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
220			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
221			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
222			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
223		>;
224	};
225
226	pinctrl_i2c1: i2c1grp {
227		fsl,pins = <
228			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
229			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
230		>;
231	};
232
233	pinctrl_qspi: qspigrp {
234		fsl,pins = <
235			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
236			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
237			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
238			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
239			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
240			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
241
242		>;
243	};
244
245	pinctrl_reg_usdhc2: regusdhc2grpgpio {
246		fsl,pins = <
247			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
248		>;
249	};
250
251	pinctrl_uart1: uart1grp {
252		fsl,pins = <
253			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
254			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
255		>;
256	};
257
258	pinctrl_usdhc1: usdhc1grp {
259		fsl,pins = <
260			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
261			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
262			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
263			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
264			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
265			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
266			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
267			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
268			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
269			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
270			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
271			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
272		>;
273	};
274
275	pinctrl_usdhc1_100mhz: usdhc1-100grp {
276		fsl,pins = <
277			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
278			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
279			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
280			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
281			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
282			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
283			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
284			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
285			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
286			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
287			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
288			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
289		>;
290	};
291
292	pinctrl_usdhc1_200mhz: usdhc1-200grp {
293		fsl,pins = <
294			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
295			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
296			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
297			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
298			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
299			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
300			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
301			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
302			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
303			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
304			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
305			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
306		>;
307	};
308
309	pinctrl_usdhc2: usdhc2grp {
310		fsl,pins = <
311			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
312			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
313			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
314			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
315			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
316			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
317			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
318		>;
319	};
320
321	pinctrl_usdhc2_100mhz: usdhc2-100grp {
322		fsl,pins = <
323			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
324			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
325			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
326			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
327			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
328			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
329			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
330		>;
331	};
332
333	pinctrl_usdhc2_200mhz: usdhc2-200grp {
334		fsl,pins = <
335			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
336			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
337			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
338			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
339			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
340			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
341			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
342		>;
343	};
344
345	pinctrl_wdog: wdog1grp {
346		fsl,pins = <
347			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
348		>;
349	};
350};
351