1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7/dts-v1/;
8
9#include "imx8mq.dtsi"
10
11/ {
12	model = "NXP i.MX8MQ EVK";
13	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x00000000 0x40000000 0 0xc0000000>;
22	};
23
24	pcie0_refclk: pcie0-refclk {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <100000000>;
28	};
29
30	reg_pcie1: regulator-pcie {
31		compatible = "regulator-fixed";
32		pinctrl-names = "default";
33		pinctrl-0 = <&pinctrl_pcie1_reg>;
34		regulator-name = "MPCIE_3V3";
35		regulator-min-microvolt = <3300000>;
36		regulator-max-microvolt = <3300000>;
37		gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
38		enable-active-high;
39	};
40
41	reg_usdhc2_vmmc: regulator-vsd-3v3 {
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_reg_usdhc2>;
44		compatible = "regulator-fixed";
45		regulator-name = "VSD_3V3";
46		regulator-min-microvolt = <3300000>;
47		regulator-max-microvolt = <3300000>;
48		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
49		enable-active-high;
50	};
51
52	buck2_reg: regulator-buck2 {
53		pinctrl-names = "default";
54		pinctrl-0 = <&pinctrl_buck2>;
55		compatible = "regulator-gpio";
56		regulator-name = "vdd_arm";
57		regulator-min-microvolt = <900000>;
58		regulator-max-microvolt = <1000000>;
59		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
60		states = <1000000 0x0
61			  900000 0x1>;
62		regulator-boot-on;
63		regulator-always-on;
64	};
65
66	ir-receiver {
67		compatible = "gpio-ir-receiver";
68		gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
69		pinctrl-names = "default";
70		pinctrl-0 = <&pinctrl_ir>;
71		linux,autosuspend-period = <125>;
72	};
73
74	audio_codec_bt_sco: audio-codec-bt-sco {
75		compatible = "linux,bt-sco";
76		#sound-dai-cells = <1>;
77	};
78
79	wm8524: audio-codec {
80		#sound-dai-cells = <0>;
81		compatible = "wlf,wm8524";
82		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
83	};
84
85	sound-bt-sco {
86		compatible = "simple-audio-card";
87		simple-audio-card,name = "bt-sco-audio";
88		simple-audio-card,format = "dsp_a";
89		simple-audio-card,bitclock-inversion;
90		simple-audio-card,frame-master = <&btcpu>;
91		simple-audio-card,bitclock-master = <&btcpu>;
92
93		btcpu: simple-audio-card,cpu {
94			sound-dai = <&sai3>;
95			dai-tdm-slot-num = <2>;
96			dai-tdm-slot-width = <16>;
97		};
98
99		simple-audio-card,codec {
100			sound-dai = <&audio_codec_bt_sco 1>;
101		};
102	};
103
104	sound-wm8524 {
105		compatible = "simple-audio-card";
106		simple-audio-card,name = "wm8524-audio";
107		simple-audio-card,format = "i2s";
108		simple-audio-card,frame-master = <&cpudai>;
109		simple-audio-card,bitclock-master = <&cpudai>;
110		simple-audio-card,widgets =
111			"Line", "Left Line Out Jack",
112			"Line", "Right Line Out Jack";
113		simple-audio-card,routing =
114			"Left Line Out Jack", "LINEVOUTL",
115			"Right Line Out Jack", "LINEVOUTR";
116
117		cpudai: simple-audio-card,cpu {
118			sound-dai = <&sai2>;
119		};
120
121		link_codec: simple-audio-card,codec {
122			sound-dai = <&wm8524>;
123			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
124		};
125	};
126
127	sound-spdif {
128		compatible = "fsl,imx-audio-spdif";
129		model = "imx-spdif";
130		spdif-controller = <&spdif1>;
131		spdif-out;
132		spdif-in;
133	};
134
135	sound-hdmi-arc {
136		compatible = "fsl,imx-audio-spdif";
137		model = "imx-hdmi-arc";
138		spdif-controller = <&spdif2>;
139		spdif-in;
140	};
141};
142
143&A53_0 {
144	cpu-supply = <&buck2_reg>;
145};
146
147&A53_1 {
148	cpu-supply = <&buck2_reg>;
149};
150
151&A53_2 {
152	cpu-supply = <&buck2_reg>;
153};
154
155&A53_3 {
156	cpu-supply = <&buck2_reg>;
157};
158
159&ddrc {
160	operating-points-v2 = <&ddrc_opp_table>;
161	status = "okay";
162
163	ddrc_opp_table: opp-table {
164		compatible = "operating-points-v2";
165
166		opp-25M {
167			opp-hz = /bits/ 64 <25000000>;
168		};
169
170		opp-100M {
171			opp-hz = /bits/ 64 <100000000>;
172		};
173
174		/*
175		 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
176		 */
177		opp-166M {
178			opp-hz = /bits/ 64 <166935483>;
179		};
180
181		opp-800M {
182			opp-hz = /bits/ 64 <800000000>;
183		};
184	};
185};
186
187&dphy {
188	status = "okay";
189};
190
191&fec1 {
192	pinctrl-names = "default";
193	pinctrl-0 = <&pinctrl_fec1>;
194	phy-mode = "rgmii-id";
195	phy-handle = <&ethphy0>;
196	fsl,magic-packet;
197	status = "okay";
198
199	mdio {
200		#address-cells = <1>;
201		#size-cells = <0>;
202
203		ethphy0: ethernet-phy@0 {
204			compatible = "ethernet-phy-ieee802.3-c22";
205			reg = <0>;
206			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
207			reset-assert-us = <10000>;
208			qca,disable-smarteee;
209			vddio-supply = <&vddh>;
210
211			vddh: vddh-regulator {
212			};
213		};
214	};
215};
216
217&gpio5 {
218	pinctrl-names = "default";
219	pinctrl-0 = <&pinctrl_wifi_reset>;
220
221	wl-reg-on-hog {
222		gpio-hog;
223		gpios = <29 GPIO_ACTIVE_HIGH>;
224		output-high;
225	};
226};
227
228&i2c1 {
229	clock-frequency = <100000>;
230	pinctrl-names = "default";
231	pinctrl-0 = <&pinctrl_i2c1>;
232	status = "okay";
233
234	pmic@8 {
235		compatible = "fsl,pfuze100";
236		reg = <0x8>;
237
238		regulators {
239			sw1a_reg: sw1ab {
240				regulator-min-microvolt = <825000>;
241				regulator-max-microvolt = <1100000>;
242			};
243
244			sw1c_reg: sw1c {
245				regulator-min-microvolt = <825000>;
246				regulator-max-microvolt = <1100000>;
247			};
248
249			sw2_reg: sw2 {
250				regulator-min-microvolt = <1100000>;
251				regulator-max-microvolt = <1100000>;
252				regulator-always-on;
253			};
254
255			sw3a_reg: sw3ab {
256				regulator-min-microvolt = <825000>;
257				regulator-max-microvolt = <1100000>;
258				regulator-always-on;
259			};
260
261			sw4_reg: sw4 {
262				regulator-min-microvolt = <1800000>;
263				regulator-max-microvolt = <1800000>;
264				regulator-always-on;
265			};
266
267			swbst_reg: swbst {
268				regulator-min-microvolt = <5000000>;
269				regulator-max-microvolt = <5150000>;
270			};
271
272			snvs_reg: vsnvs {
273				regulator-min-microvolt = <1000000>;
274				regulator-max-microvolt = <3000000>;
275				regulator-always-on;
276			};
277
278			vref_reg: vrefddr {
279				regulator-always-on;
280			};
281
282			vgen1_reg: vgen1 {
283				regulator-min-microvolt = <800000>;
284				regulator-max-microvolt = <1550000>;
285			};
286
287			vgen2_reg: vgen2 {
288				regulator-min-microvolt = <850000>;
289				regulator-max-microvolt = <975000>;
290				regulator-always-on;
291			};
292
293			vgen3_reg: vgen3 {
294				regulator-min-microvolt = <1675000>;
295				regulator-max-microvolt = <1975000>;
296				regulator-always-on;
297			};
298
299			vgen4_reg: vgen4 {
300				regulator-min-microvolt = <1625000>;
301				regulator-max-microvolt = <1875000>;
302				regulator-always-on;
303			};
304
305			vgen5_reg: vgen5 {
306				regulator-min-microvolt = <3075000>;
307				regulator-max-microvolt = <3625000>;
308				regulator-always-on;
309			};
310
311			vgen6_reg: vgen6 {
312				regulator-min-microvolt = <1800000>;
313				regulator-max-microvolt = <3300000>;
314			};
315		};
316	};
317};
318
319&lcdif {
320	status = "okay";
321};
322
323&mipi_dsi {
324	#address-cells = <1>;
325	#size-cells = <0>;
326	status = "okay";
327
328	panel@0 {
329		pinctrl-0 = <&pinctrl_mipi_dsi>;
330		pinctrl-names = "default";
331		compatible = "raydium,rm67191";
332		reg = <0>;
333		reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
334		dsi-lanes = <4>;
335
336		port {
337			panel_in: endpoint {
338				remote-endpoint = <&mipi_dsi_out>;
339			};
340		};
341	};
342
343	ports {
344		port@1 {
345			reg = <1>;
346			mipi_dsi_out: endpoint {
347				remote-endpoint = <&panel_in>;
348			};
349		};
350	};
351};
352
353&pcie0 {
354	pinctrl-names = "default";
355	pinctrl-0 = <&pinctrl_pcie0>;
356	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
357	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
358		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
359		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
360		 <&pcie0_refclk>;
361	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
362	vph-supply = <&vgen5_reg>;
363	status = "okay";
364};
365
366&pcie1 {
367	pinctrl-names = "default";
368	pinctrl-0 = <&pinctrl_pcie1>;
369	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
370	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
371		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
372		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
373		 <&pcie0_refclk>;
374	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
375	vpcie-supply = <&reg_pcie1>;
376	vph-supply = <&vgen5_reg>;
377	status = "okay";
378};
379
380&pgc_gpu {
381	power-supply = <&sw1a_reg>;
382};
383
384&pgc_vpu {
385	power-supply = <&sw1c_reg>;
386};
387
388&qspi0 {
389	pinctrl-names = "default";
390	pinctrl-0 = <&pinctrl_qspi>;
391	status = "okay";
392
393	n25q256a: flash@0 {
394		reg = <0>;
395		#address-cells = <1>;
396		#size-cells = <1>;
397		compatible = "micron,n25q256a", "jedec,spi-nor";
398		spi-max-frequency = <29000000>;
399		spi-tx-bus-width = <1>;
400		spi-rx-bus-width = <4>;
401	};
402};
403
404&sai2 {
405	pinctrl-names = "default";
406	pinctrl-0 = <&pinctrl_sai2>;
407	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
408	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
409	assigned-clock-rates = <0>, <24576000>;
410	status = "okay";
411};
412
413&sai3 {
414	#sound-dai-cells = <0>;
415	pinctrl-names = "default";
416	pinctrl-0 = <&pinctrl_sai3>;
417	assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
418	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
419	assigned-clock-rates = <24576000>;
420	status = "okay";
421};
422
423&snvs_pwrkey {
424	status = "okay";
425};
426
427&spdif1 {
428	pinctrl-names = "default";
429	pinctrl-0 = <&pinctrl_spdif1>;
430	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
431	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
432	assigned-clock-rates = <24576000>;
433	status = "okay";
434};
435
436&spdif2 {
437	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
438	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
439	assigned-clock-rates = <24576000>;
440	status = "okay";
441};
442
443&uart1 {
444	pinctrl-names = "default";
445	pinctrl-0 = <&pinctrl_uart1>;
446	status = "okay";
447};
448
449&usb3_phy1 {
450	status = "okay";
451};
452
453&usb_dwc3_1 {
454	dr_mode = "host";
455	status = "okay";
456};
457
458&usdhc1 {
459	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
460	assigned-clock-rates = <400000000>;
461	pinctrl-names = "default", "state_100mhz", "state_200mhz";
462	pinctrl-0 = <&pinctrl_usdhc1>;
463	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
464	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
465	vqmmc-supply = <&sw4_reg>;
466	bus-width = <8>;
467	non-removable;
468	no-sd;
469	no-sdio;
470	status = "okay";
471};
472
473&usdhc2 {
474	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
475	assigned-clock-rates = <200000000>;
476	pinctrl-names = "default", "state_100mhz", "state_200mhz";
477	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
478	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
479	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
480	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
481	vmmc-supply = <&reg_usdhc2_vmmc>;
482	status = "okay";
483};
484
485&wdog1 {
486	pinctrl-names = "default";
487	pinctrl-0 = <&pinctrl_wdog>;
488	fsl,ext-reset-output;
489	status = "okay";
490};
491
492&iomuxc {
493	pinctrl_buck2: vddarmgrp {
494		fsl,pins = <
495			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
496		>;
497	};
498
499	pinctrl_fec1: fec1grp {
500		fsl,pins = <
501			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
502			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
503			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
504			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
505			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
506			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
507			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
508			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
509			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
510			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
511			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
512			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
513			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
514			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
515			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
516		>;
517	};
518
519	pinctrl_i2c1: i2c1grp {
520		fsl,pins = <
521			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
522			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
523		>;
524	};
525
526	pinctrl_ir: irgrp {
527		fsl,pins = <
528			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x4f
529		>;
530	};
531
532	pinctrl_mipi_dsi: mipidsigrp {
533		fsl,pins = <
534			MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6		0x16
535		>;
536	};
537
538	pinctrl_pcie0: pcie0grp {
539		fsl,pins = <
540			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76
541			MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28		0x16
542		>;
543	};
544
545	pinctrl_pcie1: pcie1grp {
546		fsl,pins = <
547			MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B		0x76
548			MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12		0x16
549		>;
550	};
551
552	pinctrl_pcie1_reg: pcie1reggrp {
553		fsl,pins = <
554			MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x16
555		>;
556	};
557
558	pinctrl_qspi: qspigrp {
559		fsl,pins = <
560			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
561			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
562			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
563			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
564			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
565			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
566		>;
567	};
568
569	pinctrl_reg_usdhc2: regusdhc2gpiogrp {
570		fsl,pins = <
571			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
572		>;
573	};
574
575	pinctrl_sai2: sai2grp {
576		fsl,pins = <
577			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
578			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
579			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
580			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
581			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
582		>;
583	};
584
585	pinctrl_sai3: sai3grp {
586		fsl,pins = <
587			MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
588			MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
589			MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
590			MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
591		>;
592	};
593
594	pinctrl_spdif1: spdif1grp {
595		fsl,pins = <
596			MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
597			MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
598		>;
599	};
600
601	pinctrl_uart1: uart1grp {
602		fsl,pins = <
603			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
604			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
605		>;
606	};
607
608	pinctrl_usdhc1: usdhc1grp {
609		fsl,pins = <
610			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
611			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
612			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
613			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
614			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
615			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
616			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
617			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
618			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
619			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
620			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
621			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
622		>;
623	};
624
625	pinctrl_usdhc1_100mhz: usdhc1-100grp {
626		fsl,pins = <
627			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
628			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
629			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
630			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
631			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
632			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
633			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
634			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
635			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
636			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
637			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
638			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
639		>;
640	};
641
642	pinctrl_usdhc1_200mhz: usdhc1-200grp {
643		fsl,pins = <
644			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
645			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
646			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
647			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
648			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
649			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
650			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
651			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
652			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
653			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
654			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
655			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
656		>;
657	};
658
659	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
660		fsl,pins = <
661			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41
662		>;
663	};
664
665	pinctrl_usdhc2: usdhc2grp {
666		fsl,pins = <
667			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
668			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
669			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
670			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
671			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
672			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
673			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
674		>;
675	};
676
677	pinctrl_usdhc2_100mhz: usdhc2-100grp {
678		fsl,pins = <
679			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
680			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
681			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
682			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
683			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
684			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
685			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
686		>;
687	};
688
689	pinctrl_usdhc2_200mhz: usdhc2-200grp {
690		fsl,pins = <
691			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
692			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
693			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
694			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
695			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
696			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
697			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
698		>;
699	};
700
701	pinctrl_wdog: wdog1grp {
702		fsl,pins = <
703			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
704		>;
705	};
706
707	pinctrl_wifi_reset: wifiresetgrp {
708		fsl,pins = <
709			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16
710		>;
711	};
712};
713