1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7/dts-v1/;
8
9#include "imx8mq.dtsi"
10
11/ {
12	model = "NXP i.MX8MQ EVK";
13	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x00000000 0x40000000 0 0xc0000000>;
22	};
23
24	pcie0_refclk: pcie0-refclk {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <100000000>;
28	};
29
30	reg_usdhc2_vmmc: regulator-vsd-3v3 {
31		pinctrl-names = "default";
32		pinctrl-0 = <&pinctrl_reg_usdhc2>;
33		compatible = "regulator-fixed";
34		regulator-name = "VSD_3V3";
35		regulator-min-microvolt = <3300000>;
36		regulator-max-microvolt = <3300000>;
37		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
38		enable-active-high;
39	};
40
41	buck2_reg: regulator-buck2 {
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_buck2>;
44		compatible = "regulator-gpio";
45		regulator-name = "vdd_arm";
46		regulator-min-microvolt = <900000>;
47		regulator-max-microvolt = <1000000>;
48		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
49		states = <1000000 0x0
50			  900000 0x1>;
51	};
52
53	wm8524: audio-codec {
54		#sound-dai-cells = <0>;
55		compatible = "wlf,wm8524";
56		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
57	};
58
59	sound-wm8524 {
60		compatible = "simple-audio-card";
61		simple-audio-card,name = "wm8524-audio";
62		simple-audio-card,format = "i2s";
63		simple-audio-card,frame-master = <&cpudai>;
64		simple-audio-card,bitclock-master = <&cpudai>;
65		simple-audio-card,widgets =
66			"Line", "Left Line Out Jack",
67			"Line", "Right Line Out Jack";
68		simple-audio-card,routing =
69			"Left Line Out Jack", "LINEVOUTL",
70			"Right Line Out Jack", "LINEVOUTR";
71
72		cpudai: simple-audio-card,cpu {
73			sound-dai = <&sai2>;
74		};
75
76		link_codec: simple-audio-card,codec {
77			sound-dai = <&wm8524>;
78			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
79		};
80	};
81};
82
83&A53_0 {
84	cpu-supply = <&buck2_reg>;
85};
86
87&A53_1 {
88	cpu-supply = <&buck2_reg>;
89};
90
91&A53_2 {
92	cpu-supply = <&buck2_reg>;
93};
94
95&A53_3 {
96	cpu-supply = <&buck2_reg>;
97};
98
99&fec1 {
100	pinctrl-names = "default";
101	pinctrl-0 = <&pinctrl_fec1>;
102	phy-mode = "rgmii-id";
103	phy-handle = <&ethphy0>;
104	fsl,magic-packet;
105	status = "okay";
106
107	mdio {
108		#address-cells = <1>;
109		#size-cells = <0>;
110
111		ethphy0: ethernet-phy@0 {
112			compatible = "ethernet-phy-ieee802.3-c22";
113			reg = <0>;
114		};
115	};
116};
117
118&sai2 {
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_sai2>;
121	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
122	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
123	assigned-clock-rates = <24576000>;
124	status = "okay";
125};
126
127&gpio5 {
128	pinctrl-names = "default";
129	pinctrl-0 = <&pinctrl_wifi_reset>;
130
131	wl-reg-on {
132		gpio-hog;
133		gpios = <29 GPIO_ACTIVE_HIGH>;
134		output-high;
135	};
136};
137
138&i2c1 {
139	clock-frequency = <100000>;
140	pinctrl-names = "default";
141	pinctrl-0 = <&pinctrl_i2c1>;
142	status = "okay";
143
144	pmic@8 {
145		compatible = "fsl,pfuze100";
146		reg = <0x8>;
147
148		regulators {
149			sw1a_reg: sw1ab {
150				regulator-min-microvolt = <825000>;
151				regulator-max-microvolt = <1100000>;
152			};
153
154			sw1c_reg: sw1c {
155				regulator-min-microvolt = <825000>;
156				regulator-max-microvolt = <1100000>;
157			};
158
159			sw2_reg: sw2 {
160				regulator-min-microvolt = <1100000>;
161				regulator-max-microvolt = <1100000>;
162				regulator-always-on;
163			};
164
165			sw3a_reg: sw3ab {
166				regulator-min-microvolt = <825000>;
167				regulator-max-microvolt = <1100000>;
168				regulator-always-on;
169			};
170
171			sw4_reg: sw4 {
172				regulator-min-microvolt = <1800000>;
173				regulator-max-microvolt = <1800000>;
174				regulator-always-on;
175			};
176
177			swbst_reg: swbst {
178				regulator-min-microvolt = <5000000>;
179				regulator-max-microvolt = <5150000>;
180			};
181
182			snvs_reg: vsnvs {
183				regulator-min-microvolt = <1000000>;
184				regulator-max-microvolt = <3000000>;
185				regulator-always-on;
186			};
187
188			vref_reg: vrefddr {
189				regulator-always-on;
190			};
191
192			vgen1_reg: vgen1 {
193				regulator-min-microvolt = <800000>;
194				regulator-max-microvolt = <1550000>;
195			};
196
197			vgen2_reg: vgen2 {
198				regulator-min-microvolt = <850000>;
199				regulator-max-microvolt = <975000>;
200				regulator-always-on;
201			};
202
203			vgen3_reg: vgen3 {
204				regulator-min-microvolt = <1675000>;
205				regulator-max-microvolt = <1975000>;
206				regulator-always-on;
207			};
208
209			vgen4_reg: vgen4 {
210				regulator-min-microvolt = <1625000>;
211				regulator-max-microvolt = <1875000>;
212				regulator-always-on;
213			};
214
215			vgen5_reg: vgen5 {
216				regulator-min-microvolt = <3075000>;
217				regulator-max-microvolt = <3625000>;
218				regulator-always-on;
219			};
220
221			vgen6_reg: vgen6 {
222				regulator-min-microvolt = <1800000>;
223				regulator-max-microvolt = <3300000>;
224			};
225		};
226	};
227};
228
229&pcie0 {
230	pinctrl-names = "default";
231	pinctrl-0 = <&pinctrl_pcie0>;
232	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
233	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
234		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
235		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
236		 <&pcie0_refclk>;
237	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
238	status = "okay";
239};
240
241&pgc_gpu {
242	power-supply = <&sw1a_reg>;
243};
244
245&uart1 {
246	pinctrl-names = "default";
247	pinctrl-0 = <&pinctrl_uart1>;
248	status = "okay";
249};
250
251&usb3_phy1 {
252	status = "okay";
253};
254
255&usb_dwc3_1 {
256	dr_mode = "host";
257	status = "okay";
258};
259
260&qspi0 {
261	pinctrl-names = "default";
262	pinctrl-0 = <&pinctrl_qspi>;
263	status = "okay";
264
265	n25q256a: flash@0 {
266		reg = <0>;
267		#address-cells = <1>;
268		#size-cells = <1>;
269		compatible = "micron,n25q256a", "jedec,spi-nor";
270		spi-max-frequency = <29000000>;
271	};
272};
273
274&usdhc1 {
275	pinctrl-names = "default", "state_100mhz", "state_200mhz";
276	pinctrl-0 = <&pinctrl_usdhc1>;
277	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
278	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
279	vqmmc-supply = <&sw4_reg>;
280	bus-width = <8>;
281	non-removable;
282	no-sd;
283	no-sdio;
284	status = "okay";
285};
286
287&usdhc2 {
288	pinctrl-names = "default", "state_100mhz", "state_200mhz";
289	pinctrl-0 = <&pinctrl_usdhc2>;
290	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
291	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
292	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
293	vmmc-supply = <&reg_usdhc2_vmmc>;
294	status = "okay";
295};
296
297&wdog1 {
298	pinctrl-names = "default";
299	pinctrl-0 = <&pinctrl_wdog>;
300	fsl,ext-reset-output;
301	status = "okay";
302};
303
304&iomuxc {
305	pinctrl_buck2: vddarmgrp {
306		fsl,pins = <
307			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
308		>;
309
310	};
311
312	pinctrl_fec1: fec1grp {
313		fsl,pins = <
314			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
315			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
316			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
317			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
318			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
319			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
320			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
321			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
322			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
323			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
324			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
325			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
326			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
327			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
328			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
329		>;
330	};
331
332	pinctrl_i2c1: i2c1grp {
333		fsl,pins = <
334			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
335			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
336		>;
337	};
338
339	pinctrl_pcie0: pcie0grp {
340		fsl,pins = <
341			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76
342			MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28		0x16
343		>;
344	};
345
346	pinctrl_qspi: qspigrp {
347		fsl,pins = <
348			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
349			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
350			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
351			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
352			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
353			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
354
355		>;
356	};
357
358	pinctrl_reg_usdhc2: regusdhc2grpgpio {
359		fsl,pins = <
360			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
361		>;
362	};
363
364	pinctrl_sai2: sai2grp {
365		fsl,pins = <
366			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
367			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
368			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
369			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
370			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
371		>;
372	};
373
374	pinctrl_uart1: uart1grp {
375		fsl,pins = <
376			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
377			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
378		>;
379	};
380
381	pinctrl_usdhc1: usdhc1grp {
382		fsl,pins = <
383			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
384			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
385			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
386			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
387			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
388			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
389			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
390			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
391			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
392			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
393			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
394			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
395		>;
396	};
397
398	pinctrl_usdhc1_100mhz: usdhc1-100grp {
399		fsl,pins = <
400			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
401			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
402			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
403			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
404			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
405			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
406			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
407			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
408			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
409			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
410			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
411			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
412		>;
413	};
414
415	pinctrl_usdhc1_200mhz: usdhc1-200grp {
416		fsl,pins = <
417			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
418			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
419			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
420			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
421			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
422			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
423			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
424			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
425			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
426			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
427			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
428			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
429		>;
430	};
431
432	pinctrl_usdhc2: usdhc2grp {
433		fsl,pins = <
434			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
435			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
436			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
437			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
438			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
439			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
440			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
441		>;
442	};
443
444	pinctrl_usdhc2_100mhz: usdhc2-100grp {
445		fsl,pins = <
446			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
447			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
448			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
449			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
450			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
451			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
452			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
453		>;
454	};
455
456	pinctrl_usdhc2_200mhz: usdhc2-200grp {
457		fsl,pins = <
458			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
459			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
460			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
461			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
462			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
463			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
464			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
465		>;
466	};
467
468	pinctrl_wdog: wdog1grp {
469		fsl,pins = <
470			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
471		>;
472	};
473
474	pinctrl_wifi_reset: wifiresetgrp {
475		fsl,pins = <
476			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16
477		>;
478	};
479};
480