1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7/dts-v1/;
8
9#include "imx8mq.dtsi"
10
11/ {
12	model = "NXP i.MX8MQ EVK";
13	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x00000000 0x40000000 0 0xc0000000>;
22	};
23
24	pcie0_refclk: pcie0-refclk {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <100000000>;
28	};
29
30	reg_pcie1: regulator-pcie {
31		compatible = "regulator-fixed";
32		pinctrl-names = "default";
33		pinctrl-0 = <&pinctrl_pcie1_reg>;
34		regulator-name = "MPCIE_3V3";
35		regulator-min-microvolt = <3300000>;
36		regulator-max-microvolt = <3300000>;
37		gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
38		enable-active-high;
39	};
40
41	reg_usdhc2_vmmc: regulator-vsd-3v3 {
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_reg_usdhc2>;
44		compatible = "regulator-fixed";
45		regulator-name = "VSD_3V3";
46		regulator-min-microvolt = <3300000>;
47		regulator-max-microvolt = <3300000>;
48		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
49		off-on-delay-us = <20000>;
50		enable-active-high;
51	};
52
53	buck2_reg: regulator-buck2 {
54		pinctrl-names = "default";
55		pinctrl-0 = <&pinctrl_buck2>;
56		compatible = "regulator-gpio";
57		regulator-name = "vdd_arm";
58		regulator-min-microvolt = <900000>;
59		regulator-max-microvolt = <1000000>;
60		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
61		states = <1000000 0x0
62			  900000 0x1>;
63		regulator-boot-on;
64		regulator-always-on;
65	};
66
67	ir-receiver {
68		compatible = "gpio-ir-receiver";
69		gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
70		pinctrl-names = "default";
71		pinctrl-0 = <&pinctrl_ir>;
72		linux,autosuspend-period = <125>;
73	};
74
75	audio_codec_bt_sco: audio-codec-bt-sco {
76		compatible = "linux,bt-sco";
77		#sound-dai-cells = <1>;
78	};
79
80	wm8524: audio-codec {
81		#sound-dai-cells = <0>;
82		compatible = "wlf,wm8524";
83		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
84	};
85
86	sound-bt-sco {
87		compatible = "simple-audio-card";
88		simple-audio-card,name = "bt-sco-audio";
89		simple-audio-card,format = "dsp_a";
90		simple-audio-card,bitclock-inversion;
91		simple-audio-card,frame-master = <&btcpu>;
92		simple-audio-card,bitclock-master = <&btcpu>;
93
94		btcpu: simple-audio-card,cpu {
95			sound-dai = <&sai3>;
96			dai-tdm-slot-num = <2>;
97			dai-tdm-slot-width = <16>;
98		};
99
100		simple-audio-card,codec {
101			sound-dai = <&audio_codec_bt_sco 1>;
102		};
103	};
104
105	sound-wm8524 {
106		compatible = "simple-audio-card";
107		simple-audio-card,name = "wm8524-audio";
108		simple-audio-card,format = "i2s";
109		simple-audio-card,frame-master = <&cpudai>;
110		simple-audio-card,bitclock-master = <&cpudai>;
111		simple-audio-card,widgets =
112			"Line", "Left Line Out Jack",
113			"Line", "Right Line Out Jack";
114		simple-audio-card,routing =
115			"Left Line Out Jack", "LINEVOUTL",
116			"Right Line Out Jack", "LINEVOUTR";
117
118		cpudai: simple-audio-card,cpu {
119			sound-dai = <&sai2>;
120		};
121
122		link_codec: simple-audio-card,codec {
123			sound-dai = <&wm8524>;
124			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
125		};
126	};
127
128	sound-spdif {
129		compatible = "fsl,imx-audio-spdif";
130		model = "imx-spdif";
131		spdif-controller = <&spdif1>;
132		spdif-out;
133		spdif-in;
134	};
135
136	sound-hdmi-arc {
137		compatible = "fsl,imx-audio-spdif";
138		model = "imx-hdmi-arc";
139		spdif-controller = <&spdif2>;
140		spdif-in;
141	};
142};
143
144&A53_0 {
145	cpu-supply = <&buck2_reg>;
146};
147
148&A53_1 {
149	cpu-supply = <&buck2_reg>;
150};
151
152&A53_2 {
153	cpu-supply = <&buck2_reg>;
154};
155
156&A53_3 {
157	cpu-supply = <&buck2_reg>;
158};
159
160&ddrc {
161	operating-points-v2 = <&ddrc_opp_table>;
162	status = "okay";
163
164	ddrc_opp_table: opp-table {
165		compatible = "operating-points-v2";
166
167		opp-25000000 {
168			opp-hz = /bits/ 64 <25000000>;
169		};
170
171		opp-100000000 {
172			opp-hz = /bits/ 64 <100000000>;
173		};
174
175		/*
176		 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
177		 */
178		opp-166000000 {
179			opp-hz = /bits/ 64 <166935483>;
180		};
181
182		opp-800000000 {
183			opp-hz = /bits/ 64 <800000000>;
184		};
185	};
186};
187
188&dphy {
189	status = "okay";
190};
191
192&fec1 {
193	pinctrl-names = "default";
194	pinctrl-0 = <&pinctrl_fec1>;
195	phy-mode = "rgmii-id";
196	phy-handle = <&ethphy0>;
197	fsl,magic-packet;
198	status = "okay";
199
200	mdio {
201		#address-cells = <1>;
202		#size-cells = <0>;
203
204		ethphy0: ethernet-phy@0 {
205			compatible = "ethernet-phy-ieee802.3-c22";
206			reg = <0>;
207			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
208			reset-assert-us = <10000>;
209			qca,disable-smarteee;
210			vddio-supply = <&vddh>;
211
212			vddh: vddh-regulator {
213			};
214		};
215	};
216};
217
218&gpio5 {
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_wifi_reset>;
221
222	wl-reg-on-hog {
223		gpio-hog;
224		gpios = <29 GPIO_ACTIVE_HIGH>;
225		output-high;
226	};
227};
228
229&i2c1 {
230	clock-frequency = <100000>;
231	pinctrl-names = "default";
232	pinctrl-0 = <&pinctrl_i2c1>;
233	status = "okay";
234
235	pmic@8 {
236		compatible = "fsl,pfuze100";
237		reg = <0x8>;
238
239		regulators {
240			sw1a_reg: sw1ab {
241				regulator-min-microvolt = <825000>;
242				regulator-max-microvolt = <1100000>;
243			};
244
245			sw1c_reg: sw1c {
246				regulator-min-microvolt = <825000>;
247				regulator-max-microvolt = <1100000>;
248			};
249
250			sw2_reg: sw2 {
251				regulator-min-microvolt = <1100000>;
252				regulator-max-microvolt = <1100000>;
253				regulator-always-on;
254			};
255
256			sw3a_reg: sw3ab {
257				regulator-min-microvolt = <825000>;
258				regulator-max-microvolt = <1100000>;
259				regulator-always-on;
260			};
261
262			sw4_reg: sw4 {
263				regulator-min-microvolt = <1800000>;
264				regulator-max-microvolt = <1800000>;
265				regulator-always-on;
266			};
267
268			swbst_reg: swbst {
269				regulator-min-microvolt = <5000000>;
270				regulator-max-microvolt = <5150000>;
271			};
272
273			snvs_reg: vsnvs {
274				regulator-min-microvolt = <1000000>;
275				regulator-max-microvolt = <3000000>;
276				regulator-always-on;
277			};
278
279			vref_reg: vrefddr {
280				regulator-always-on;
281			};
282
283			vgen1_reg: vgen1 {
284				regulator-min-microvolt = <800000>;
285				regulator-max-microvolt = <1550000>;
286			};
287
288			vgen2_reg: vgen2 {
289				regulator-min-microvolt = <850000>;
290				regulator-max-microvolt = <975000>;
291				regulator-always-on;
292			};
293
294			vgen3_reg: vgen3 {
295				regulator-min-microvolt = <1675000>;
296				regulator-max-microvolt = <1975000>;
297				regulator-always-on;
298			};
299
300			vgen4_reg: vgen4 {
301				regulator-min-microvolt = <1625000>;
302				regulator-max-microvolt = <1875000>;
303				regulator-always-on;
304			};
305
306			vgen5_reg: vgen5 {
307				regulator-min-microvolt = <3075000>;
308				regulator-max-microvolt = <3625000>;
309				regulator-always-on;
310			};
311
312			vgen6_reg: vgen6 {
313				regulator-min-microvolt = <1800000>;
314				regulator-max-microvolt = <3300000>;
315			};
316		};
317	};
318};
319
320&lcdif {
321	status = "okay";
322};
323
324&mipi_dsi {
325	#address-cells = <1>;
326	#size-cells = <0>;
327	status = "okay";
328
329	panel@0 {
330		pinctrl-0 = <&pinctrl_mipi_dsi>;
331		pinctrl-names = "default";
332		compatible = "raydium,rm67191";
333		reg = <0>;
334		reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
335		dsi-lanes = <4>;
336
337		port {
338			panel_in: endpoint {
339				remote-endpoint = <&mipi_dsi_out>;
340			};
341		};
342	};
343
344	ports {
345		port@1 {
346			reg = <1>;
347			mipi_dsi_out: endpoint {
348				remote-endpoint = <&panel_in>;
349			};
350		};
351	};
352};
353
354&pcie0 {
355	pinctrl-names = "default";
356	pinctrl-0 = <&pinctrl_pcie0>;
357	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
358	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
359		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
360		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
361		 <&pcie0_refclk>;
362	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
363	vph-supply = <&vgen5_reg>;
364	status = "okay";
365};
366
367&pcie1 {
368	pinctrl-names = "default";
369	pinctrl-0 = <&pinctrl_pcie1>;
370	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
371	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
372		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
373		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
374		 <&pcie0_refclk>;
375	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
376	vpcie-supply = <&reg_pcie1>;
377	vph-supply = <&vgen5_reg>;
378	status = "okay";
379};
380
381&pgc_gpu {
382	power-supply = <&sw1a_reg>;
383};
384
385&pgc_vpu {
386	power-supply = <&sw1c_reg>;
387};
388
389&qspi0 {
390	pinctrl-names = "default";
391	pinctrl-0 = <&pinctrl_qspi>;
392	status = "okay";
393
394	n25q256a: flash@0 {
395		reg = <0>;
396		#address-cells = <1>;
397		#size-cells = <1>;
398		compatible = "micron,n25q256a", "jedec,spi-nor";
399		spi-max-frequency = <29000000>;
400		spi-tx-bus-width = <1>;
401		spi-rx-bus-width = <4>;
402	};
403};
404
405&sai2 {
406	pinctrl-names = "default";
407	pinctrl-0 = <&pinctrl_sai2>;
408	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
409	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
410	assigned-clock-rates = <0>, <24576000>;
411	status = "okay";
412};
413
414&sai3 {
415	#sound-dai-cells = <0>;
416	pinctrl-names = "default";
417	pinctrl-0 = <&pinctrl_sai3>;
418	assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
419	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
420	assigned-clock-rates = <24576000>;
421	status = "okay";
422};
423
424&snvs_pwrkey {
425	status = "okay";
426};
427
428&spdif1 {
429	pinctrl-names = "default";
430	pinctrl-0 = <&pinctrl_spdif1>;
431	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
432	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
433	assigned-clock-rates = <24576000>;
434	status = "okay";
435};
436
437&spdif2 {
438	assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
439	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
440	assigned-clock-rates = <24576000>;
441	status = "okay";
442};
443
444&uart1 {
445	pinctrl-names = "default";
446	pinctrl-0 = <&pinctrl_uart1>;
447	status = "okay";
448};
449
450&usb3_phy1 {
451	status = "okay";
452};
453
454&usb_dwc3_1 {
455	dr_mode = "host";
456	status = "okay";
457};
458
459&usdhc1 {
460	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
461	assigned-clock-rates = <400000000>;
462	pinctrl-names = "default", "state_100mhz", "state_200mhz";
463	pinctrl-0 = <&pinctrl_usdhc1>;
464	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
465	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
466	vqmmc-supply = <&sw4_reg>;
467	bus-width = <8>;
468	non-removable;
469	no-sd;
470	no-sdio;
471	status = "okay";
472};
473
474&usdhc2 {
475	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
476	assigned-clock-rates = <200000000>;
477	pinctrl-names = "default", "state_100mhz", "state_200mhz";
478	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
479	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
480	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
481	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
482	vmmc-supply = <&reg_usdhc2_vmmc>;
483	status = "okay";
484};
485
486&wdog1 {
487	pinctrl-names = "default";
488	pinctrl-0 = <&pinctrl_wdog>;
489	fsl,ext-reset-output;
490	status = "okay";
491};
492
493&iomuxc {
494	pinctrl_buck2: vddarmgrp {
495		fsl,pins = <
496			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
497		>;
498	};
499
500	pinctrl_fec1: fec1grp {
501		fsl,pins = <
502			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
503			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
504			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
505			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
506			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
507			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
508			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
509			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
510			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
511			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
512			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
513			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
514			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
515			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
516			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
517		>;
518	};
519
520	pinctrl_i2c1: i2c1grp {
521		fsl,pins = <
522			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
523			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
524		>;
525	};
526
527	pinctrl_ir: irgrp {
528		fsl,pins = <
529			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x4f
530		>;
531	};
532
533	pinctrl_mipi_dsi: mipidsigrp {
534		fsl,pins = <
535			MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6		0x16
536		>;
537	};
538
539	pinctrl_pcie0: pcie0grp {
540		fsl,pins = <
541			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76
542			MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28		0x16
543		>;
544	};
545
546	pinctrl_pcie1: pcie1grp {
547		fsl,pins = <
548			MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B		0x76
549			MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12		0x16
550		>;
551	};
552
553	pinctrl_pcie1_reg: pcie1reggrp {
554		fsl,pins = <
555			MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x16
556		>;
557	};
558
559	pinctrl_qspi: qspigrp {
560		fsl,pins = <
561			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
562			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
563			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
564			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
565			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
566			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
567		>;
568	};
569
570	pinctrl_reg_usdhc2: regusdhc2gpiogrp {
571		fsl,pins = <
572			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
573		>;
574	};
575
576	pinctrl_sai2: sai2grp {
577		fsl,pins = <
578			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
579			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
580			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
581			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
582			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
583		>;
584	};
585
586	pinctrl_sai3: sai3grp {
587		fsl,pins = <
588			MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
589			MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
590			MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
591			MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0     0xd6
592		>;
593	};
594
595	pinctrl_spdif1: spdif1grp {
596		fsl,pins = <
597			MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
598			MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
599		>;
600	};
601
602	pinctrl_uart1: uart1grp {
603		fsl,pins = <
604			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
605			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
606		>;
607	};
608
609	pinctrl_usdhc1: usdhc1grp {
610		fsl,pins = <
611			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
612			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
613			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
614			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
615			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
616			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
617			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
618			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
619			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
620			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
621			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
622			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
623		>;
624	};
625
626	pinctrl_usdhc1_100mhz: usdhc1-100grp {
627		fsl,pins = <
628			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
629			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
630			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
631			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
632			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
633			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
634			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
635			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
636			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
637			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
638			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
639			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
640		>;
641	};
642
643	pinctrl_usdhc1_200mhz: usdhc1-200grp {
644		fsl,pins = <
645			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
646			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
647			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
648			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
649			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
650			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
651			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
652			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
653			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
654			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
655			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
656			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
657		>;
658	};
659
660	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
661		fsl,pins = <
662			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41
663		>;
664	};
665
666	pinctrl_usdhc2: usdhc2grp {
667		fsl,pins = <
668			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
669			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
670			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
671			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
672			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
673			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
674			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
675		>;
676	};
677
678	pinctrl_usdhc2_100mhz: usdhc2-100grp {
679		fsl,pins = <
680			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
681			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
682			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
683			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
684			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
685			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
686			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
687		>;
688	};
689
690	pinctrl_usdhc2_200mhz: usdhc2-200grp {
691		fsl,pins = <
692			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
693			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
694			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
695			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
696			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
697			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
698			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
699		>;
700	};
701
702	pinctrl_wdog: wdog1grp {
703		fsl,pins = <
704			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
705		>;
706	};
707
708	pinctrl_wifi_reset: wifiresetgrp {
709		fsl,pins = <
710			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16
711		>;
712	};
713};
714