1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7/dts-v1/;
8
9#include "imx8mq.dtsi"
10
11/ {
12	model = "NXP i.MX8MQ EVK";
13	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14
15	chosen {
16		stdout-path = &uart1;
17	};
18
19	memory@40000000 {
20		device_type = "memory";
21		reg = <0x00000000 0x40000000 0 0xc0000000>;
22	};
23
24	pcie0_refclk: pcie0-refclk {
25		compatible = "fixed-clock";
26		#clock-cells = <0>;
27		clock-frequency = <100000000>;
28	};
29
30	reg_usdhc2_vmmc: regulator-vsd-3v3 {
31		pinctrl-names = "default";
32		pinctrl-0 = <&pinctrl_reg_usdhc2>;
33		compatible = "regulator-fixed";
34		regulator-name = "VSD_3V3";
35		regulator-min-microvolt = <3300000>;
36		regulator-max-microvolt = <3300000>;
37		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
38		enable-active-high;
39	};
40
41	buck2_reg: regulator-buck2 {
42		pinctrl-names = "default";
43		pinctrl-0 = <&pinctrl_buck2>;
44		compatible = "regulator-gpio";
45		regulator-name = "vdd_arm";
46		regulator-min-microvolt = <900000>;
47		regulator-max-microvolt = <1000000>;
48		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
49		states = <1000000 0x0
50			  900000 0x1>;
51		regulator-boot-on;
52		regulator-always-on;
53	};
54
55	ir-receiver {
56		compatible = "gpio-ir-receiver";
57		gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
58		pinctrl-names = "default";
59		pinctrl-0 = <&pinctrl_ir>;
60	};
61
62	wm8524: audio-codec {
63		#sound-dai-cells = <0>;
64		compatible = "wlf,wm8524";
65		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
66	};
67
68	sound-wm8524 {
69		compatible = "simple-audio-card";
70		simple-audio-card,name = "wm8524-audio";
71		simple-audio-card,format = "i2s";
72		simple-audio-card,frame-master = <&cpudai>;
73		simple-audio-card,bitclock-master = <&cpudai>;
74		simple-audio-card,widgets =
75			"Line", "Left Line Out Jack",
76			"Line", "Right Line Out Jack";
77		simple-audio-card,routing =
78			"Left Line Out Jack", "LINEVOUTL",
79			"Right Line Out Jack", "LINEVOUTR";
80
81		cpudai: simple-audio-card,cpu {
82			sound-dai = <&sai2>;
83		};
84
85		link_codec: simple-audio-card,codec {
86			sound-dai = <&wm8524>;
87			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
88		};
89	};
90};
91
92&A53_0 {
93	cpu-supply = <&buck2_reg>;
94};
95
96&A53_1 {
97	cpu-supply = <&buck2_reg>;
98};
99
100&A53_2 {
101	cpu-supply = <&buck2_reg>;
102};
103
104&A53_3 {
105	cpu-supply = <&buck2_reg>;
106};
107
108&ddrc {
109	operating-points-v2 = <&ddrc_opp_table>;
110
111	ddrc_opp_table: opp-table {
112		compatible = "operating-points-v2";
113
114		opp-25M {
115			opp-hz = /bits/ 64 <25000000>;
116		};
117
118		opp-100M {
119			opp-hz = /bits/ 64 <100000000>;
120		};
121
122		/*
123		 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
124		 */
125		opp-166M {
126			opp-hz = /bits/ 64 <166935483>;
127		};
128
129		opp-800M {
130			opp-hz = /bits/ 64 <800000000>;
131		};
132	};
133};
134
135&fec1 {
136	pinctrl-names = "default";
137	pinctrl-0 = <&pinctrl_fec1>;
138	phy-mode = "rgmii-id";
139	phy-handle = <&ethphy0>;
140	fsl,magic-packet;
141	status = "okay";
142
143	mdio {
144		#address-cells = <1>;
145		#size-cells = <0>;
146
147		ethphy0: ethernet-phy@0 {
148			compatible = "ethernet-phy-ieee802.3-c22";
149			reg = <0>;
150		};
151	};
152};
153
154&gpio5 {
155	pinctrl-names = "default";
156	pinctrl-0 = <&pinctrl_wifi_reset>;
157
158	wl-reg-on {
159		gpio-hog;
160		gpios = <29 GPIO_ACTIVE_HIGH>;
161		output-high;
162	};
163};
164
165&i2c1 {
166	clock-frequency = <100000>;
167	pinctrl-names = "default";
168	pinctrl-0 = <&pinctrl_i2c1>;
169	status = "okay";
170
171	pmic@8 {
172		compatible = "fsl,pfuze100";
173		reg = <0x8>;
174
175		regulators {
176			sw1a_reg: sw1ab {
177				regulator-min-microvolt = <825000>;
178				regulator-max-microvolt = <1100000>;
179			};
180
181			sw1c_reg: sw1c {
182				regulator-min-microvolt = <825000>;
183				regulator-max-microvolt = <1100000>;
184			};
185
186			sw2_reg: sw2 {
187				regulator-min-microvolt = <1100000>;
188				regulator-max-microvolt = <1100000>;
189				regulator-always-on;
190			};
191
192			sw3a_reg: sw3ab {
193				regulator-min-microvolt = <825000>;
194				regulator-max-microvolt = <1100000>;
195				regulator-always-on;
196			};
197
198			sw4_reg: sw4 {
199				regulator-min-microvolt = <1800000>;
200				regulator-max-microvolt = <1800000>;
201				regulator-always-on;
202			};
203
204			swbst_reg: swbst {
205				regulator-min-microvolt = <5000000>;
206				regulator-max-microvolt = <5150000>;
207			};
208
209			snvs_reg: vsnvs {
210				regulator-min-microvolt = <1000000>;
211				regulator-max-microvolt = <3000000>;
212				regulator-always-on;
213			};
214
215			vref_reg: vrefddr {
216				regulator-always-on;
217			};
218
219			vgen1_reg: vgen1 {
220				regulator-min-microvolt = <800000>;
221				regulator-max-microvolt = <1550000>;
222			};
223
224			vgen2_reg: vgen2 {
225				regulator-min-microvolt = <850000>;
226				regulator-max-microvolt = <975000>;
227				regulator-always-on;
228			};
229
230			vgen3_reg: vgen3 {
231				regulator-min-microvolt = <1675000>;
232				regulator-max-microvolt = <1975000>;
233				regulator-always-on;
234			};
235
236			vgen4_reg: vgen4 {
237				regulator-min-microvolt = <1625000>;
238				regulator-max-microvolt = <1875000>;
239				regulator-always-on;
240			};
241
242			vgen5_reg: vgen5 {
243				regulator-min-microvolt = <3075000>;
244				regulator-max-microvolt = <3625000>;
245				regulator-always-on;
246			};
247
248			vgen6_reg: vgen6 {
249				regulator-min-microvolt = <1800000>;
250				regulator-max-microvolt = <3300000>;
251			};
252		};
253	};
254};
255
256&pcie0 {
257	pinctrl-names = "default";
258	pinctrl-0 = <&pinctrl_pcie0>;
259	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
260	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
261		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
262		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
263		 <&pcie0_refclk>;
264	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
265	status = "okay";
266};
267
268&pgc_gpu {
269	power-supply = <&sw1a_reg>;
270};
271
272&qspi0 {
273	pinctrl-names = "default";
274	pinctrl-0 = <&pinctrl_qspi>;
275	status = "okay";
276
277	n25q256a: flash@0 {
278		reg = <0>;
279		#address-cells = <1>;
280		#size-cells = <1>;
281		compatible = "micron,n25q256a", "jedec,spi-nor";
282		spi-max-frequency = <29000000>;
283	};
284};
285
286&sai2 {
287	pinctrl-names = "default";
288	pinctrl-0 = <&pinctrl_sai2>;
289	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
290	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
291	assigned-clock-rates = <0>, <24576000>;
292	status = "okay";
293};
294
295&snvs_pwrkey {
296	status = "okay";
297};
298
299&uart1 {
300	pinctrl-names = "default";
301	pinctrl-0 = <&pinctrl_uart1>;
302	status = "okay";
303};
304
305&usb3_phy1 {
306	status = "okay";
307};
308
309&usb_dwc3_1 {
310	dr_mode = "host";
311	status = "okay";
312};
313
314&usdhc1 {
315	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
316	assigned-clock-rates = <400000000>;
317	pinctrl-names = "default", "state_100mhz", "state_200mhz";
318	pinctrl-0 = <&pinctrl_usdhc1>;
319	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
320	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
321	vqmmc-supply = <&sw4_reg>;
322	bus-width = <8>;
323	non-removable;
324	no-sd;
325	no-sdio;
326	status = "okay";
327};
328
329&usdhc2 {
330	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
331	assigned-clock-rates = <200000000>;
332	pinctrl-names = "default", "state_100mhz", "state_200mhz";
333	pinctrl-0 = <&pinctrl_usdhc2>;
334	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
335	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
336	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
337	vmmc-supply = <&reg_usdhc2_vmmc>;
338	status = "okay";
339};
340
341&wdog1 {
342	pinctrl-names = "default";
343	pinctrl-0 = <&pinctrl_wdog>;
344	fsl,ext-reset-output;
345	status = "okay";
346};
347
348&iomuxc {
349	pinctrl_buck2: vddarmgrp {
350		fsl,pins = <
351			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
352		>;
353
354	};
355
356	pinctrl_fec1: fec1grp {
357		fsl,pins = <
358			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
359			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
360			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
361			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
362			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
363			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
364			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
365			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
366			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
367			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
368			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
369			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
370			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
371			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
372			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
373		>;
374	};
375
376	pinctrl_i2c1: i2c1grp {
377		fsl,pins = <
378			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
379			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
380		>;
381	};
382
383	pinctrl_ir: irgrp {
384		fsl,pins = <
385			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x4f
386		>;
387	};
388
389	pinctrl_pcie0: pcie0grp {
390		fsl,pins = <
391			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76
392			MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28		0x16
393		>;
394	};
395
396	pinctrl_qspi: qspigrp {
397		fsl,pins = <
398			MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
399			MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
400			MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
401			MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
402			MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
403			MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
404
405		>;
406	};
407
408	pinctrl_reg_usdhc2: regusdhc2grpgpio {
409		fsl,pins = <
410			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
411		>;
412	};
413
414	pinctrl_sai2: sai2grp {
415		fsl,pins = <
416			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
417			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
418			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK        0xd6
419			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
420			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8       0xd6
421		>;
422	};
423
424	pinctrl_uart1: uart1grp {
425		fsl,pins = <
426			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
427			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
428		>;
429	};
430
431	pinctrl_usdhc1: usdhc1grp {
432		fsl,pins = <
433			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
434			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
435			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
436			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
437			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
438			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
439			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
440			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
441			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
442			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
443			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
444			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
445		>;
446	};
447
448	pinctrl_usdhc1_100mhz: usdhc1-100grp {
449		fsl,pins = <
450			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
451			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
452			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
453			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
454			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
455			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
456			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
457			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
458			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
459			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
460			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
461			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
462		>;
463	};
464
465	pinctrl_usdhc1_200mhz: usdhc1-200grp {
466		fsl,pins = <
467			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
468			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
469			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
470			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
471			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
472			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
473			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
474			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
475			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
476			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
477			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
478			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
479		>;
480	};
481
482	pinctrl_usdhc2: usdhc2grp {
483		fsl,pins = <
484			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
485			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
486			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
487			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
488			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
489			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
490			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
491		>;
492	};
493
494	pinctrl_usdhc2_100mhz: usdhc2-100grp {
495		fsl,pins = <
496			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
497			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
498			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
499			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
500			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
501			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
502			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
503		>;
504	};
505
506	pinctrl_usdhc2_200mhz: usdhc2-200grp {
507		fsl,pins = <
508			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
509			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
510			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
511			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
512			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
513			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
514			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
515		>;
516	};
517
518	pinctrl_wdog: wdog1grp {
519		fsl,pins = <
520			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
521		>;
522	};
523
524	pinctrl_wifi_reset: wifiresetgrp {
525		fsl,pins = <
526			MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29		0x16
527		>;
528	};
529};
530