1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 A53_0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&A53_L2>; 64 nvmem-cells = <&cpu_speed_grade>; 65 nvmem-cell-names = "speed_grade"; 66 operating-points-v2 = <&a53_opp_table>; 67 #cooling-cells = <2>; 68 }; 69 70 A53_1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x1>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MP_CLK_ARM>; 76 enable-method = "psci"; 77 i-cache-size = <0x8000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <128>; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A53_2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x2>; 92 clock-latency = <61036>; 93 clocks = <&clk IMX8MP_CLK_ARM>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 }; 105 106 A53_3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x3>; 110 clock-latency = <61036>; 111 clocks = <&clk IMX8MP_CLK_ARM>; 112 enable-method = "psci"; 113 i-cache-size = <0x8000>; 114 i-cache-line-size = <64>; 115 i-cache-sets = <256>; 116 d-cache-size = <0x8000>; 117 d-cache-line-size = <64>; 118 d-cache-sets = <128>; 119 next-level-cache = <&A53_L2>; 120 operating-points-v2 = <&a53_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A53_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-unified; 127 cache-level = <2>; 128 cache-size = <0x80000>; 129 cache-line-size = <64>; 130 cache-sets = <512>; 131 }; 132 }; 133 134 a53_opp_table: opp-table { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-1200000000 { 139 opp-hz = /bits/ 64 <1200000000>; 140 opp-microvolt = <850000>; 141 opp-supported-hw = <0x8a0>, <0x7>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 146 opp-1600000000 { 147 opp-hz = /bits/ 64 <1600000000>; 148 opp-microvolt = <950000>; 149 opp-supported-hw = <0xa0>, <0x7>; 150 clock-latency-ns = <150000>; 151 opp-suspend; 152 }; 153 154 opp-1800000000 { 155 opp-hz = /bits/ 64 <1800000000>; 156 opp-microvolt = <1000000>; 157 opp-supported-hw = <0x20>, <0x3>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 }; 162 163 osc_32k: clock-osc-32k { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <32768>; 167 clock-output-names = "osc_32k"; 168 }; 169 170 osc_24m: clock-osc-24m { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <24000000>; 174 clock-output-names = "osc_24m"; 175 }; 176 177 clk_ext1: clock-ext1 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext1"; 182 }; 183 184 clk_ext2: clock-ext2 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <133000000>; 188 clock-output-names = "clk_ext2"; 189 }; 190 191 clk_ext3: clock-ext3 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext3"; 196 }; 197 198 clk_ext4: clock-ext4 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext4"; 203 }; 204 205 reserved-memory { 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges; 209 210 dsp_reserved: dsp@92400000 { 211 reg = <0 0x92400000 0 0x2000000>; 212 no-map; 213 }; 214 }; 215 216 pmu { 217 compatible = "arm,cortex-a53-pmu"; 218 interrupts = <GIC_PPI 7 219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0"; 224 method = "smc"; 225 }; 226 227 thermal-zones { 228 cpu-thermal { 229 polling-delay-passive = <250>; 230 polling-delay = <2000>; 231 thermal-sensors = <&tmu 0>; 232 trips { 233 cpu_alert0: trip0 { 234 temperature = <85000>; 235 hysteresis = <2000>; 236 type = "passive"; 237 }; 238 239 cpu_crit0: trip1 { 240 temperature = <95000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 }; 245 246 cooling-maps { 247 map0 { 248 trip = <&cpu_alert0>; 249 cooling-device = 250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 254 }; 255 }; 256 }; 257 258 soc-thermal { 259 polling-delay-passive = <250>; 260 polling-delay = <2000>; 261 thermal-sensors = <&tmu 1>; 262 trips { 263 soc_alert0: trip0 { 264 temperature = <85000>; 265 hysteresis = <2000>; 266 type = "passive"; 267 }; 268 269 soc_crit0: trip1 { 270 temperature = <95000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 276 cooling-maps { 277 map0 { 278 trip = <&soc_alert0>; 279 cooling-device = 280 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 281 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 282 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 283 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 284 }; 285 }; 286 }; 287 }; 288 289 timer { 290 compatible = "arm,armv8-timer"; 291 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 293 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 294 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 295 clock-frequency = <8000000>; 296 arm,no-tick-in-suspend; 297 }; 298 299 soc: soc@0 { 300 compatible = "fsl,imx8mp-soc", "simple-bus"; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0x0 0x0 0x0 0x3e000000>; 304 nvmem-cells = <&imx8mp_uid>; 305 nvmem-cell-names = "soc_unique_id"; 306 307 etm0: etm@28440000 { 308 compatible = "arm,coresight-etm4x", "arm,primecell"; 309 reg = <0x28440000 0x1000>; 310 cpu = <&A53_0>; 311 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 312 clock-names = "apb_pclk"; 313 314 out-ports { 315 port { 316 etm0_out_port: endpoint { 317 remote-endpoint = <&ca_funnel_in_port0>; 318 }; 319 }; 320 }; 321 }; 322 323 etm1: etm@28540000 { 324 compatible = "arm,coresight-etm4x", "arm,primecell"; 325 reg = <0x28540000 0x1000>; 326 cpu = <&A53_1>; 327 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 328 clock-names = "apb_pclk"; 329 330 out-ports { 331 port { 332 etm1_out_port: endpoint { 333 remote-endpoint = <&ca_funnel_in_port1>; 334 }; 335 }; 336 }; 337 }; 338 339 etm2: etm@28640000 { 340 compatible = "arm,coresight-etm4x", "arm,primecell"; 341 reg = <0x28640000 0x1000>; 342 cpu = <&A53_2>; 343 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 344 clock-names = "apb_pclk"; 345 346 out-ports { 347 port { 348 etm2_out_port: endpoint { 349 remote-endpoint = <&ca_funnel_in_port2>; 350 }; 351 }; 352 }; 353 }; 354 355 etm3: etm@28740000 { 356 compatible = "arm,coresight-etm4x", "arm,primecell"; 357 reg = <0x28740000 0x1000>; 358 cpu = <&A53_3>; 359 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 360 clock-names = "apb_pclk"; 361 362 out-ports { 363 port { 364 etm3_out_port: endpoint { 365 remote-endpoint = <&ca_funnel_in_port3>; 366 }; 367 }; 368 }; 369 }; 370 371 funnel { 372 /* 373 * non-configurable funnel don't show up on the AMBA 374 * bus. As such no need to add "arm,primecell". 375 */ 376 compatible = "arm,coresight-static-funnel"; 377 378 in-ports { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 382 port@0 { 383 reg = <0>; 384 385 ca_funnel_in_port0: endpoint { 386 remote-endpoint = <&etm0_out_port>; 387 }; 388 }; 389 390 port@1 { 391 reg = <1>; 392 393 ca_funnel_in_port1: endpoint { 394 remote-endpoint = <&etm1_out_port>; 395 }; 396 }; 397 398 port@2 { 399 reg = <2>; 400 401 ca_funnel_in_port2: endpoint { 402 remote-endpoint = <&etm2_out_port>; 403 }; 404 }; 405 406 port@3 { 407 reg = <3>; 408 409 ca_funnel_in_port3: endpoint { 410 remote-endpoint = <&etm3_out_port>; 411 }; 412 }; 413 }; 414 415 out-ports { 416 port { 417 ca_funnel_out_port0: endpoint { 418 remote-endpoint = <&hugo_funnel_in_port0>; 419 }; 420 }; 421 }; 422 }; 423 424 funnel@28c03000 { 425 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 426 reg = <0x28c03000 0x1000>; 427 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 428 clock-names = "apb_pclk"; 429 430 in-ports { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 port@0 { 435 reg = <0>; 436 437 hugo_funnel_in_port0: endpoint { 438 remote-endpoint = <&ca_funnel_out_port0>; 439 }; 440 }; 441 442 port@1 { 443 reg = <1>; 444 445 hugo_funnel_in_port1: endpoint { 446 /* M7 input */ 447 }; 448 }; 449 450 port@2 { 451 reg = <2>; 452 453 hugo_funnel_in_port2: endpoint { 454 /* DSP input */ 455 }; 456 }; 457 /* the other input ports are not connect to anything */ 458 }; 459 460 out-ports { 461 port { 462 hugo_funnel_out_port0: endpoint { 463 remote-endpoint = <&etf_in_port>; 464 }; 465 }; 466 }; 467 }; 468 469 etf@28c04000 { 470 compatible = "arm,coresight-tmc", "arm,primecell"; 471 reg = <0x28c04000 0x1000>; 472 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 473 clock-names = "apb_pclk"; 474 475 in-ports { 476 port { 477 etf_in_port: endpoint { 478 remote-endpoint = <&hugo_funnel_out_port0>; 479 }; 480 }; 481 }; 482 483 out-ports { 484 port { 485 etf_out_port: endpoint { 486 remote-endpoint = <&etr_in_port>; 487 }; 488 }; 489 }; 490 }; 491 492 etr@28c06000 { 493 compatible = "arm,coresight-tmc", "arm,primecell"; 494 reg = <0x28c06000 0x1000>; 495 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 496 clock-names = "apb_pclk"; 497 498 in-ports { 499 port { 500 etr_in_port: endpoint { 501 remote-endpoint = <&etf_out_port>; 502 }; 503 }; 504 }; 505 }; 506 507 aips1: bus@30000000 { 508 compatible = "fsl,aips-bus", "simple-bus"; 509 reg = <0x30000000 0x400000>; 510 #address-cells = <1>; 511 #size-cells = <1>; 512 ranges; 513 514 gpio1: gpio@30200000 { 515 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 516 reg = <0x30200000 0x10000>; 517 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 520 gpio-controller; 521 #gpio-cells = <2>; 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 gpio-ranges = <&iomuxc 0 5 30>; 525 }; 526 527 gpio2: gpio@30210000 { 528 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 529 reg = <0x30210000 0x10000>; 530 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 533 gpio-controller; 534 #gpio-cells = <2>; 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 gpio-ranges = <&iomuxc 0 35 21>; 538 }; 539 540 gpio3: gpio@30220000 { 541 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 542 reg = <0x30220000 0x10000>; 543 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 546 gpio-controller; 547 #gpio-cells = <2>; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 551 }; 552 553 gpio4: gpio@30230000 { 554 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 555 reg = <0x30230000 0x10000>; 556 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 559 gpio-controller; 560 #gpio-cells = <2>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 gpio-ranges = <&iomuxc 0 82 32>; 564 }; 565 566 gpio5: gpio@30240000 { 567 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 568 reg = <0x30240000 0x10000>; 569 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 572 gpio-controller; 573 #gpio-cells = <2>; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 gpio-ranges = <&iomuxc 0 114 30>; 577 }; 578 579 tmu: tmu@30260000 { 580 compatible = "fsl,imx8mp-tmu"; 581 reg = <0x30260000 0x10000>; 582 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 583 nvmem-cells = <&tmu_calib>; 584 nvmem-cell-names = "calib"; 585 #thermal-sensor-cells = <1>; 586 }; 587 588 wdog1: watchdog@30280000 { 589 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 590 reg = <0x30280000 0x10000>; 591 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 593 status = "disabled"; 594 }; 595 596 wdog2: watchdog@30290000 { 597 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 598 reg = <0x30290000 0x10000>; 599 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 601 status = "disabled"; 602 }; 603 604 wdog3: watchdog@302a0000 { 605 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 606 reg = <0x302a0000 0x10000>; 607 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 609 status = "disabled"; 610 }; 611 612 gpt1: timer@302d0000 { 613 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 614 reg = <0x302d0000 0x10000>; 615 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; 617 clock-names = "ipg", "per"; 618 }; 619 620 gpt2: timer@302e0000 { 621 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 622 reg = <0x302e0000 0x10000>; 623 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; 625 clock-names = "ipg", "per"; 626 }; 627 628 gpt3: timer@302f0000 { 629 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 630 reg = <0x302f0000 0x10000>; 631 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; 633 clock-names = "ipg", "per"; 634 }; 635 636 iomuxc: pinctrl@30330000 { 637 compatible = "fsl,imx8mp-iomuxc"; 638 reg = <0x30330000 0x10000>; 639 }; 640 641 gpr: syscon@30340000 { 642 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 643 reg = <0x30340000 0x10000>; 644 }; 645 646 ocotp: efuse@30350000 { 647 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 648 reg = <0x30350000 0x10000>; 649 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 650 /* For nvmem subnodes */ 651 #address-cells = <1>; 652 #size-cells = <1>; 653 654 /* 655 * The register address below maps to the MX8M 656 * Fusemap Description Table entries this way. 657 * Assuming 658 * reg = <ADDR SIZE>; 659 * then 660 * Fuse Address = (ADDR * 4) + 0x400 661 * Note that if SIZE is greater than 4, then 662 * each subsequent fuse is located at offset 663 * +0x10 in Fusemap Description Table (e.g. 664 * reg = <0x8 0x8> describes fuses 0x420 and 665 * 0x430). 666 */ 667 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 668 reg = <0x8 0x8>; 669 }; 670 671 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 672 reg = <0x10 4>; 673 }; 674 675 eth_mac1: mac-address@90 { /* 0x640 */ 676 reg = <0x90 6>; 677 }; 678 679 eth_mac2: mac-address@96 { /* 0x658 */ 680 reg = <0x96 6>; 681 }; 682 683 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 684 reg = <0x264 0x10>; 685 }; 686 }; 687 688 anatop: clock-controller@30360000 { 689 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 690 reg = <0x30360000 0x10000>; 691 #clock-cells = <1>; 692 }; 693 694 snvs: snvs@30370000 { 695 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 696 reg = <0x30370000 0x10000>; 697 698 snvs_rtc: snvs-rtc-lp { 699 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 700 regmap = <&snvs>; 701 offset = <0x34>; 702 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 705 clock-names = "snvs-rtc"; 706 }; 707 708 snvs_pwrkey: snvs-powerkey { 709 compatible = "fsl,sec-v4.0-pwrkey"; 710 regmap = <&snvs>; 711 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 713 clock-names = "snvs-pwrkey"; 714 linux,keycode = <KEY_POWER>; 715 wakeup-source; 716 status = "disabled"; 717 }; 718 719 snvs_lpgpr: snvs-lpgpr { 720 compatible = "fsl,imx8mp-snvs-lpgpr", 721 "fsl,imx7d-snvs-lpgpr"; 722 }; 723 }; 724 725 clk: clock-controller@30380000 { 726 compatible = "fsl,imx8mp-ccm"; 727 reg = <0x30380000 0x10000>; 728 #clock-cells = <1>; 729 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 730 <&clk_ext3>, <&clk_ext4>; 731 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 732 "clk_ext3", "clk_ext4"; 733 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 734 <&clk IMX8MP_CLK_A53_CORE>, 735 <&clk IMX8MP_CLK_NOC>, 736 <&clk IMX8MP_CLK_NOC_IO>, 737 <&clk IMX8MP_CLK_GIC>; 738 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 739 <&clk IMX8MP_ARM_PLL_OUT>, 740 <&clk IMX8MP_SYS_PLL2_1000M>, 741 <&clk IMX8MP_SYS_PLL1_800M>, 742 <&clk IMX8MP_SYS_PLL2_500M>; 743 assigned-clock-rates = <0>, <0>, 744 <1000000000>, 745 <800000000>, 746 <500000000>; 747 }; 748 749 src: reset-controller@30390000 { 750 compatible = "fsl,imx8mp-src", "syscon"; 751 reg = <0x30390000 0x10000>; 752 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 753 #reset-cells = <1>; 754 }; 755 756 gpc: gpc@303a0000 { 757 compatible = "fsl,imx8mp-gpc"; 758 reg = <0x303a0000 0x1000>; 759 interrupt-parent = <&gic>; 760 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-controller; 762 #interrupt-cells = <3>; 763 764 pgc { 765 #address-cells = <1>; 766 #size-cells = <0>; 767 768 pgc_mipi_phy1: power-domain@0 { 769 #power-domain-cells = <0>; 770 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 771 }; 772 773 pgc_pcie_phy: power-domain@1 { 774 #power-domain-cells = <0>; 775 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 776 }; 777 778 pgc_usb1_phy: power-domain@2 { 779 #power-domain-cells = <0>; 780 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 781 }; 782 783 pgc_usb2_phy: power-domain@3 { 784 #power-domain-cells = <0>; 785 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 786 }; 787 788 pgc_mlmix: power-domain@4 { 789 #power-domain-cells = <0>; 790 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 791 clocks = <&clk IMX8MP_CLK_ML_AXI>, 792 <&clk IMX8MP_CLK_ML_AHB>, 793 <&clk IMX8MP_CLK_NPU_ROOT>; 794 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 795 <&clk IMX8MP_CLK_ML_AXI>, 796 <&clk IMX8MP_CLK_ML_AHB>; 797 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 798 <&clk IMX8MP_SYS_PLL1_800M>, 799 <&clk IMX8MP_SYS_PLL1_800M>; 800 assigned-clock-rates = <800000000>, 801 <800000000>, 802 <300000000>; 803 }; 804 805 pgc_audio: power-domain@5 { 806 #power-domain-cells = <0>; 807 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; 808 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 809 <&clk IMX8MP_CLK_AUDIO_AXI>; 810 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, 811 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; 812 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 813 <&clk IMX8MP_SYS_PLL1_800M>; 814 assigned-clock-rates = <400000000>, 815 <600000000>; 816 }; 817 818 pgc_gpu2d: power-domain@6 { 819 #power-domain-cells = <0>; 820 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 821 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 822 power-domains = <&pgc_gpumix>; 823 }; 824 825 pgc_gpumix: power-domain@7 { 826 #power-domain-cells = <0>; 827 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 828 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 829 <&clk IMX8MP_CLK_GPU_AHB>; 830 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 831 <&clk IMX8MP_CLK_GPU_AHB>; 832 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 833 <&clk IMX8MP_SYS_PLL1_800M>; 834 assigned-clock-rates = <800000000>, <400000000>; 835 }; 836 837 pgc_vpumix: power-domain@8 { 838 #power-domain-cells = <0>; 839 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 840 clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 841 }; 842 843 pgc_gpu3d: power-domain@9 { 844 #power-domain-cells = <0>; 845 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 846 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 847 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 848 power-domains = <&pgc_gpumix>; 849 }; 850 851 pgc_mediamix: power-domain@10 { 852 #power-domain-cells = <0>; 853 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 854 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 855 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 856 }; 857 858 pgc_vpu_g1: power-domain@11 { 859 #power-domain-cells = <0>; 860 power-domains = <&pgc_vpumix>; 861 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 862 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 863 }; 864 865 pgc_vpu_g2: power-domain@12 { 866 #power-domain-cells = <0>; 867 power-domains = <&pgc_vpumix>; 868 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 869 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 870 871 }; 872 873 pgc_vpu_vc8000e: power-domain@13 { 874 #power-domain-cells = <0>; 875 power-domains = <&pgc_vpumix>; 876 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 877 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 878 }; 879 880 pgc_hdmimix: power-domain@14 { 881 #power-domain-cells = <0>; 882 reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>; 883 clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, 884 <&clk IMX8MP_CLK_HDMI_APB>; 885 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, 886 <&clk IMX8MP_CLK_HDMI_APB>; 887 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, 888 <&clk IMX8MP_SYS_PLL1_133M>; 889 assigned-clock-rates = <500000000>, <133000000>; 890 }; 891 892 pgc_hdmi_phy: power-domain@15 { 893 #power-domain-cells = <0>; 894 reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>; 895 }; 896 897 pgc_mipi_phy2: power-domain@16 { 898 #power-domain-cells = <0>; 899 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 900 }; 901 902 pgc_hsiomix: power-domain@17 { 903 #power-domain-cells = <0>; 904 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 905 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 906 <&clk IMX8MP_CLK_HSIO_ROOT>; 907 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 908 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 909 assigned-clock-rates = <500000000>; 910 }; 911 912 pgc_ispdwp: power-domain@18 { 913 #power-domain-cells = <0>; 914 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 915 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 916 }; 917 }; 918 }; 919 }; 920 921 aips2: bus@30400000 { 922 compatible = "fsl,aips-bus", "simple-bus"; 923 reg = <0x30400000 0x400000>; 924 #address-cells = <1>; 925 #size-cells = <1>; 926 ranges; 927 928 pwm1: pwm@30660000 { 929 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 930 reg = <0x30660000 0x10000>; 931 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 933 <&clk IMX8MP_CLK_PWM1_ROOT>; 934 clock-names = "ipg", "per"; 935 #pwm-cells = <3>; 936 status = "disabled"; 937 }; 938 939 pwm2: pwm@30670000 { 940 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 941 reg = <0x30670000 0x10000>; 942 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 944 <&clk IMX8MP_CLK_PWM2_ROOT>; 945 clock-names = "ipg", "per"; 946 #pwm-cells = <3>; 947 status = "disabled"; 948 }; 949 950 pwm3: pwm@30680000 { 951 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 952 reg = <0x30680000 0x10000>; 953 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 955 <&clk IMX8MP_CLK_PWM3_ROOT>; 956 clock-names = "ipg", "per"; 957 #pwm-cells = <3>; 958 status = "disabled"; 959 }; 960 961 pwm4: pwm@30690000 { 962 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 963 reg = <0x30690000 0x10000>; 964 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 966 <&clk IMX8MP_CLK_PWM4_ROOT>; 967 clock-names = "ipg", "per"; 968 #pwm-cells = <3>; 969 status = "disabled"; 970 }; 971 972 system_counter: timer@306a0000 { 973 compatible = "nxp,sysctr-timer"; 974 reg = <0x306a0000 0x20000>; 975 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&osc_24m>; 977 clock-names = "per"; 978 }; 979 980 gpt6: timer@306e0000 { 981 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 982 reg = <0x306e0000 0x10000>; 983 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; 985 clock-names = "ipg", "per"; 986 }; 987 988 gpt5: timer@306f0000 { 989 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 990 reg = <0x306f0000 0x10000>; 991 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; 993 clock-names = "ipg", "per"; 994 }; 995 996 gpt4: timer@30700000 { 997 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 998 reg = <0x30700000 0x10000>; 999 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; 1001 clock-names = "ipg", "per"; 1002 }; 1003 }; 1004 1005 aips3: bus@30800000 { 1006 compatible = "fsl,aips-bus", "simple-bus"; 1007 reg = <0x30800000 0x400000>; 1008 #address-cells = <1>; 1009 #size-cells = <1>; 1010 ranges; 1011 1012 spba-bus@30800000 { 1013 compatible = "fsl,spba-bus", "simple-bus"; 1014 reg = <0x30800000 0x100000>; 1015 #address-cells = <1>; 1016 #size-cells = <1>; 1017 ranges; 1018 1019 ecspi1: spi@30820000 { 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1023 reg = <0x30820000 0x10000>; 1024 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 1026 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 1027 clock-names = "ipg", "per"; 1028 assigned-clock-rates = <80000000>; 1029 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 1030 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1031 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 1032 dma-names = "rx", "tx"; 1033 status = "disabled"; 1034 }; 1035 1036 ecspi2: spi@30830000 { 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1040 reg = <0x30830000 0x10000>; 1041 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 1043 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 1044 clock-names = "ipg", "per"; 1045 assigned-clock-rates = <80000000>; 1046 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 1047 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1048 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 1049 dma-names = "rx", "tx"; 1050 status = "disabled"; 1051 }; 1052 1053 ecspi3: spi@30840000 { 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1057 reg = <0x30840000 0x10000>; 1058 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 1060 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 1061 clock-names = "ipg", "per"; 1062 assigned-clock-rates = <80000000>; 1063 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 1064 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1065 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 1066 dma-names = "rx", "tx"; 1067 status = "disabled"; 1068 }; 1069 1070 uart1: serial@30860000 { 1071 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1072 reg = <0x30860000 0x10000>; 1073 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 1075 <&clk IMX8MP_CLK_UART1_ROOT>; 1076 clock-names = "ipg", "per"; 1077 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 1078 dma-names = "rx", "tx"; 1079 status = "disabled"; 1080 }; 1081 1082 uart3: serial@30880000 { 1083 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1084 reg = <0x30880000 0x10000>; 1085 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 1087 <&clk IMX8MP_CLK_UART3_ROOT>; 1088 clock-names = "ipg", "per"; 1089 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 1090 dma-names = "rx", "tx"; 1091 status = "disabled"; 1092 }; 1093 1094 uart2: serial@30890000 { 1095 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1096 reg = <0x30890000 0x10000>; 1097 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 1099 <&clk IMX8MP_CLK_UART2_ROOT>; 1100 clock-names = "ipg", "per"; 1101 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 1102 dma-names = "rx", "tx"; 1103 status = "disabled"; 1104 }; 1105 1106 flexcan1: can@308c0000 { 1107 compatible = "fsl,imx8mp-flexcan"; 1108 reg = <0x308c0000 0x10000>; 1109 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1111 <&clk IMX8MP_CLK_CAN1_ROOT>; 1112 clock-names = "ipg", "per"; 1113 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 1114 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1115 assigned-clock-rates = <40000000>; 1116 fsl,clk-source = /bits/ 8 <0>; 1117 fsl,stop-mode = <&gpr 0x10 4>; 1118 status = "disabled"; 1119 }; 1120 1121 flexcan2: can@308d0000 { 1122 compatible = "fsl,imx8mp-flexcan"; 1123 reg = <0x308d0000 0x10000>; 1124 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1126 <&clk IMX8MP_CLK_CAN2_ROOT>; 1127 clock-names = "ipg", "per"; 1128 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 1129 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1130 assigned-clock-rates = <40000000>; 1131 fsl,clk-source = /bits/ 8 <0>; 1132 fsl,stop-mode = <&gpr 0x10 5>; 1133 status = "disabled"; 1134 }; 1135 }; 1136 1137 crypto: crypto@30900000 { 1138 compatible = "fsl,sec-v4.0"; 1139 #address-cells = <1>; 1140 #size-cells = <1>; 1141 reg = <0x30900000 0x40000>; 1142 ranges = <0 0x30900000 0x40000>; 1143 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&clk IMX8MP_CLK_AHB>, 1145 <&clk IMX8MP_CLK_IPG_ROOT>; 1146 clock-names = "aclk", "ipg"; 1147 1148 sec_jr0: jr@1000 { 1149 compatible = "fsl,sec-v4.0-job-ring"; 1150 reg = <0x1000 0x1000>; 1151 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1152 status = "disabled"; 1153 }; 1154 1155 sec_jr1: jr@2000 { 1156 compatible = "fsl,sec-v4.0-job-ring"; 1157 reg = <0x2000 0x1000>; 1158 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1159 }; 1160 1161 sec_jr2: jr@3000 { 1162 compatible = "fsl,sec-v4.0-job-ring"; 1163 reg = <0x3000 0x1000>; 1164 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1165 }; 1166 }; 1167 1168 i2c1: i2c@30a20000 { 1169 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 reg = <0x30a20000 0x10000>; 1173 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 1175 status = "disabled"; 1176 }; 1177 1178 i2c2: i2c@30a30000 { 1179 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 reg = <0x30a30000 0x10000>; 1183 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 1185 status = "disabled"; 1186 }; 1187 1188 i2c3: i2c@30a40000 { 1189 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 reg = <0x30a40000 0x10000>; 1193 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 1195 status = "disabled"; 1196 }; 1197 1198 i2c4: i2c@30a50000 { 1199 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 reg = <0x30a50000 0x10000>; 1203 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1204 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 1205 status = "disabled"; 1206 }; 1207 1208 uart4: serial@30a60000 { 1209 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1210 reg = <0x30a60000 0x10000>; 1211 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 1213 <&clk IMX8MP_CLK_UART4_ROOT>; 1214 clock-names = "ipg", "per"; 1215 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1216 dma-names = "rx", "tx"; 1217 status = "disabled"; 1218 }; 1219 1220 mu: mailbox@30aa0000 { 1221 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1222 reg = <0x30aa0000 0x10000>; 1223 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1224 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 1225 #mbox-cells = <2>; 1226 }; 1227 1228 mu2: mailbox@30e60000 { 1229 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1230 reg = <0x30e60000 0x10000>; 1231 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1232 #mbox-cells = <2>; 1233 status = "disabled"; 1234 }; 1235 1236 i2c5: i2c@30ad0000 { 1237 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 reg = <0x30ad0000 0x10000>; 1241 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1242 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 1243 status = "disabled"; 1244 }; 1245 1246 i2c6: i2c@30ae0000 { 1247 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 reg = <0x30ae0000 0x10000>; 1251 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 1253 status = "disabled"; 1254 }; 1255 1256 usdhc1: mmc@30b40000 { 1257 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1258 reg = <0x30b40000 0x10000>; 1259 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1261 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1262 <&clk IMX8MP_CLK_USDHC1_ROOT>; 1263 clock-names = "ipg", "ahb", "per"; 1264 fsl,tuning-start-tap = <20>; 1265 fsl,tuning-step = <2>; 1266 bus-width = <4>; 1267 status = "disabled"; 1268 }; 1269 1270 usdhc2: mmc@30b50000 { 1271 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1272 reg = <0x30b50000 0x10000>; 1273 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1275 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1276 <&clk IMX8MP_CLK_USDHC2_ROOT>; 1277 clock-names = "ipg", "ahb", "per"; 1278 fsl,tuning-start-tap = <20>; 1279 fsl,tuning-step = <2>; 1280 bus-width = <4>; 1281 status = "disabled"; 1282 }; 1283 1284 usdhc3: mmc@30b60000 { 1285 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1286 reg = <0x30b60000 0x10000>; 1287 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1289 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1290 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1291 clock-names = "ipg", "ahb", "per"; 1292 fsl,tuning-start-tap = <20>; 1293 fsl,tuning-step = <2>; 1294 bus-width = <4>; 1295 status = "disabled"; 1296 }; 1297 1298 flexspi: spi@30bb0000 { 1299 compatible = "nxp,imx8mp-fspi"; 1300 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1301 reg-names = "fspi_base", "fspi_mmap"; 1302 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1304 <&clk IMX8MP_CLK_QSPI_ROOT>; 1305 clock-names = "fspi_en", "fspi"; 1306 assigned-clock-rates = <80000000>; 1307 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1308 #address-cells = <1>; 1309 #size-cells = <0>; 1310 status = "disabled"; 1311 }; 1312 1313 sdma1: dma-controller@30bd0000 { 1314 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1315 reg = <0x30bd0000 0x10000>; 1316 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1317 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1318 <&clk IMX8MP_CLK_AHB>; 1319 clock-names = "ipg", "ahb"; 1320 #dma-cells = <3>; 1321 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1322 }; 1323 1324 fec: ethernet@30be0000 { 1325 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1326 reg = <0x30be0000 0x10000>; 1327 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1331 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1332 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1333 <&clk IMX8MP_CLK_ENET_TIMER>, 1334 <&clk IMX8MP_CLK_ENET_REF>, 1335 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1336 clock-names = "ipg", "ahb", "ptp", 1337 "enet_clk_ref", "enet_out"; 1338 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1339 <&clk IMX8MP_CLK_ENET_TIMER>, 1340 <&clk IMX8MP_CLK_ENET_REF>, 1341 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1342 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1343 <&clk IMX8MP_SYS_PLL2_100M>, 1344 <&clk IMX8MP_SYS_PLL2_125M>, 1345 <&clk IMX8MP_SYS_PLL2_50M>; 1346 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1347 fsl,num-tx-queues = <3>; 1348 fsl,num-rx-queues = <3>; 1349 nvmem-cells = <ð_mac1>; 1350 nvmem-cell-names = "mac-address"; 1351 fsl,stop-mode = <&gpr 0x10 3>; 1352 status = "disabled"; 1353 }; 1354 1355 eqos: ethernet@30bf0000 { 1356 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1357 reg = <0x30bf0000 0x10000>; 1358 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1360 interrupt-names = "macirq", "eth_wake_irq"; 1361 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1362 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1363 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1364 <&clk IMX8MP_CLK_ENET_QOS>; 1365 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1366 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1367 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1368 <&clk IMX8MP_CLK_ENET_QOS>; 1369 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1370 <&clk IMX8MP_SYS_PLL2_100M>, 1371 <&clk IMX8MP_SYS_PLL2_125M>; 1372 assigned-clock-rates = <0>, <100000000>, <125000000>; 1373 nvmem-cells = <ð_mac2>; 1374 nvmem-cell-names = "mac-address"; 1375 intf_mode = <&gpr 0x4>; 1376 status = "disabled"; 1377 }; 1378 }; 1379 1380 aips5: bus@30c00000 { 1381 compatible = "fsl,aips-bus", "simple-bus"; 1382 reg = <0x30c00000 0x400000>; 1383 #address-cells = <1>; 1384 #size-cells = <1>; 1385 ranges; 1386 1387 spba-bus@30c00000 { 1388 compatible = "fsl,spba-bus", "simple-bus"; 1389 reg = <0x30c00000 0x100000>; 1390 #address-cells = <1>; 1391 #size-cells = <1>; 1392 ranges; 1393 1394 sai1: sai@30c10000 { 1395 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1396 reg = <0x30c10000 0x10000>; 1397 #sound-dai-cells = <0>; 1398 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, 1399 <&clk IMX8MP_CLK_DUMMY>, 1400 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, 1401 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, 1402 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; 1403 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1404 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 1405 dma-names = "rx", "tx"; 1406 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1407 status = "disabled"; 1408 }; 1409 1410 sai2: sai@30c20000 { 1411 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1412 reg = <0x30c20000 0x10000>; 1413 #sound-dai-cells = <0>; 1414 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, 1415 <&clk IMX8MP_CLK_DUMMY>, 1416 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, 1417 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, 1418 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; 1419 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1420 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 1421 dma-names = "rx", "tx"; 1422 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1423 status = "disabled"; 1424 }; 1425 1426 sai3: sai@30c30000 { 1427 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1428 reg = <0x30c30000 0x10000>; 1429 #sound-dai-cells = <0>; 1430 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, 1431 <&clk IMX8MP_CLK_DUMMY>, 1432 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, 1433 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, 1434 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; 1435 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1436 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 1437 dma-names = "rx", "tx"; 1438 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1439 status = "disabled"; 1440 }; 1441 1442 sai5: sai@30c50000 { 1443 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1444 reg = <0x30c50000 0x10000>; 1445 #sound-dai-cells = <0>; 1446 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, 1447 <&clk IMX8MP_CLK_DUMMY>, 1448 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, 1449 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, 1450 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; 1451 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1452 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 1453 dma-names = "rx", "tx"; 1454 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1455 status = "disabled"; 1456 }; 1457 1458 sai6: sai@30c60000 { 1459 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1460 reg = <0x30c60000 0x10000>; 1461 #sound-dai-cells = <0>; 1462 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, 1463 <&clk IMX8MP_CLK_DUMMY>, 1464 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, 1465 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, 1466 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; 1467 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1468 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 1469 dma-names = "rx", "tx"; 1470 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1471 status = "disabled"; 1472 }; 1473 1474 sai7: sai@30c80000 { 1475 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1476 reg = <0x30c80000 0x10000>; 1477 #sound-dai-cells = <0>; 1478 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, 1479 <&clk IMX8MP_CLK_DUMMY>, 1480 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, 1481 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, 1482 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; 1483 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1484 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 1485 dma-names = "rx", "tx"; 1486 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1487 status = "disabled"; 1488 }; 1489 }; 1490 1491 sdma3: dma-controller@30e00000 { 1492 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1493 reg = <0x30e00000 0x10000>; 1494 #dma-cells = <3>; 1495 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, 1496 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1497 clock-names = "ipg", "ahb"; 1498 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1499 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1500 }; 1501 1502 sdma2: dma-controller@30e10000 { 1503 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1504 reg = <0x30e10000 0x10000>; 1505 #dma-cells = <3>; 1506 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, 1507 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1508 clock-names = "ipg", "ahb"; 1509 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1510 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1511 }; 1512 1513 audio_blk_ctrl: clock-controller@30e20000 { 1514 compatible = "fsl,imx8mp-audio-blk-ctrl"; 1515 reg = <0x30e20000 0x10000>; 1516 #clock-cells = <1>; 1517 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 1518 <&clk IMX8MP_CLK_SAI1>, 1519 <&clk IMX8MP_CLK_SAI2>, 1520 <&clk IMX8MP_CLK_SAI3>, 1521 <&clk IMX8MP_CLK_SAI5>, 1522 <&clk IMX8MP_CLK_SAI6>, 1523 <&clk IMX8MP_CLK_SAI7>; 1524 clock-names = "ahb", 1525 "sai1", "sai2", "sai3", 1526 "sai5", "sai6", "sai7"; 1527 power-domains = <&pgc_audio>; 1528 }; 1529 }; 1530 1531 noc: interconnect@32700000 { 1532 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1533 reg = <0x32700000 0x100000>; 1534 clocks = <&clk IMX8MP_CLK_NOC>; 1535 #interconnect-cells = <1>; 1536 operating-points-v2 = <&noc_opp_table>; 1537 1538 noc_opp_table: opp-table { 1539 compatible = "operating-points-v2"; 1540 1541 opp-200000000 { 1542 opp-hz = /bits/ 64 <200000000>; 1543 }; 1544 1545 opp-1000000000 { 1546 opp-hz = /bits/ 64 <1000000000>; 1547 }; 1548 }; 1549 }; 1550 1551 aips4: bus@32c00000 { 1552 compatible = "fsl,aips-bus", "simple-bus"; 1553 reg = <0x32c00000 0x400000>; 1554 #address-cells = <1>; 1555 #size-cells = <1>; 1556 ranges; 1557 1558 isi_0: isi@32e00000 { 1559 compatible = "fsl,imx8mp-isi"; 1560 reg = <0x32e00000 0x4000>; 1561 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1562 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1563 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1564 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1565 clock-names = "axi", "apb"; 1566 fsl,blk-ctrl = <&media_blk_ctrl>; 1567 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; 1568 status = "disabled"; 1569 1570 ports { 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 1574 port@0 { 1575 reg = <0>; 1576 1577 isi_in_0: endpoint { 1578 remote-endpoint = <&mipi_csi_0_out>; 1579 }; 1580 }; 1581 1582 port@1 { 1583 reg = <1>; 1584 1585 isi_in_1: endpoint { 1586 remote-endpoint = <&mipi_csi_1_out>; 1587 }; 1588 }; 1589 }; 1590 }; 1591 1592 dewarp: dwe@32e30000 { 1593 compatible = "nxp,imx8mp-dw100"; 1594 reg = <0x32e30000 0x10000>; 1595 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1596 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1597 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1598 clock-names = "axi", "ahb"; 1599 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; 1600 }; 1601 1602 mipi_csi_0: csi@32e40000 { 1603 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1604 reg = <0x32e40000 0x10000>; 1605 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1606 clock-frequency = <500000000>; 1607 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1608 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1609 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1610 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1611 clock-names = "pclk", "wrap", "phy", "axi"; 1612 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>; 1613 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1614 assigned-clock-rates = <500000000>; 1615 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; 1616 status = "disabled"; 1617 1618 ports { 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 port@0 { 1623 reg = <0>; 1624 }; 1625 1626 port@1 { 1627 reg = <1>; 1628 1629 mipi_csi_0_out: endpoint { 1630 remote-endpoint = <&isi_in_0>; 1631 }; 1632 }; 1633 }; 1634 }; 1635 1636 mipi_csi_1: csi@32e50000 { 1637 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1638 reg = <0x32e50000 0x10000>; 1639 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1640 clock-frequency = <266000000>; 1641 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1642 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1643 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1644 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1645 clock-names = "pclk", "wrap", "phy", "axi"; 1646 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>; 1647 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1648 assigned-clock-rates = <266000000>; 1649 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; 1650 status = "disabled"; 1651 1652 ports { 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 1656 port@0 { 1657 reg = <0>; 1658 }; 1659 1660 port@1 { 1661 reg = <1>; 1662 1663 mipi_csi_1_out: endpoint { 1664 remote-endpoint = <&isi_in_1>; 1665 }; 1666 }; 1667 }; 1668 }; 1669 1670 mipi_dsi: dsi@32e60000 { 1671 compatible = "fsl,imx8mp-mipi-dsim"; 1672 reg = <0x32e60000 0x400>; 1673 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1674 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1675 clock-names = "bus_clk", "sclk_mipi"; 1676 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, 1677 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1678 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1679 <&clk IMX8MP_CLK_24M>; 1680 assigned-clock-rates = <200000000>, <24000000>; 1681 samsung,pll-clock-frequency = <24000000>; 1682 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1683 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; 1684 status = "disabled"; 1685 1686 ports { 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 1690 port@0 { 1691 reg = <0>; 1692 1693 dsim_from_lcdif1: endpoint { 1694 remote-endpoint = <&lcdif1_to_dsim>; 1695 }; 1696 }; 1697 }; 1698 }; 1699 1700 lcdif1: display-controller@32e80000 { 1701 compatible = "fsl,imx8mp-lcdif"; 1702 reg = <0x32e80000 0x10000>; 1703 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1704 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1705 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1706 clock-names = "pix", "axi", "disp_axi"; 1707 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1708 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; 1709 status = "disabled"; 1710 1711 port { 1712 lcdif1_to_dsim: endpoint { 1713 remote-endpoint = <&dsim_from_lcdif1>; 1714 }; 1715 }; 1716 }; 1717 1718 lcdif2: display-controller@32e90000 { 1719 compatible = "fsl,imx8mp-lcdif"; 1720 reg = <0x32e90000 0x10000>; 1721 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1722 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1723 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1724 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1725 clock-names = "pix", "axi", "disp_axi"; 1726 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1727 status = "disabled"; 1728 1729 port { 1730 lcdif2_to_ldb: endpoint { 1731 remote-endpoint = <&ldb_from_lcdif2>; 1732 }; 1733 }; 1734 }; 1735 1736 media_blk_ctrl: blk-ctrl@32ec0000 { 1737 compatible = "fsl,imx8mp-media-blk-ctrl", 1738 "syscon"; 1739 reg = <0x32ec0000 0x10000>; 1740 #address-cells = <1>; 1741 #size-cells = <1>; 1742 power-domains = <&pgc_mediamix>, 1743 <&pgc_mipi_phy1>, 1744 <&pgc_mipi_phy1>, 1745 <&pgc_mediamix>, 1746 <&pgc_mediamix>, 1747 <&pgc_mipi_phy2>, 1748 <&pgc_mediamix>, 1749 <&pgc_ispdwp>, 1750 <&pgc_ispdwp>, 1751 <&pgc_mipi_phy2>; 1752 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1753 "lcdif1", "isi", "mipi-csi2", 1754 "lcdif2", "isp", "dwe", 1755 "mipi-dsi2"; 1756 interconnects = 1757 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1758 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1759 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1760 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1761 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1762 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1763 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1764 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1765 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1766 "isi1", "isi2", "isp0", "isp1", 1767 "dwe"; 1768 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1769 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1770 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1771 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1772 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1773 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1774 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1775 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1776 clock-names = "apb", "axi", "cam1", "cam2", 1777 "disp1", "disp2", "isp", "phy"; 1778 1779 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1780 <&clk IMX8MP_CLK_MEDIA_APB>, 1781 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 1782 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1783 <&clk IMX8MP_VIDEO_PLL1>; 1784 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1785 <&clk IMX8MP_SYS_PLL1_800M>, 1786 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1787 <&clk IMX8MP_VIDEO_PLL1_OUT>; 1788 assigned-clock-rates = <500000000>, <200000000>, 1789 <0>, <0>, <1039500000>; 1790 #power-domain-cells = <1>; 1791 1792 lvds_bridge: bridge@5c { 1793 compatible = "fsl,imx8mp-ldb"; 1794 reg = <0x5c 0x4>, <0x128 0x4>; 1795 reg-names = "ldb", "lvds"; 1796 clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1797 clock-names = "ldb"; 1798 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1799 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1800 status = "disabled"; 1801 1802 ports { 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 1806 port@0 { 1807 reg = <0>; 1808 1809 ldb_from_lcdif2: endpoint { 1810 remote-endpoint = <&lcdif2_to_ldb>; 1811 }; 1812 }; 1813 1814 port@1 { 1815 reg = <1>; 1816 1817 ldb_lvds_ch0: endpoint { 1818 }; 1819 }; 1820 1821 port@2 { 1822 reg = <2>; 1823 1824 ldb_lvds_ch1: endpoint { 1825 }; 1826 }; 1827 }; 1828 }; 1829 }; 1830 1831 pcie_phy: pcie-phy@32f00000 { 1832 compatible = "fsl,imx8mp-pcie-phy"; 1833 reg = <0x32f00000 0x10000>; 1834 resets = <&src IMX8MP_RESET_PCIEPHY>, 1835 <&src IMX8MP_RESET_PCIEPHY_PERST>; 1836 reset-names = "pciephy", "perst"; 1837 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 1838 #phy-cells = <0>; 1839 status = "disabled"; 1840 }; 1841 1842 hsio_blk_ctrl: blk-ctrl@32f10000 { 1843 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 1844 reg = <0x32f10000 0x24>; 1845 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1846 <&clk IMX8MP_CLK_PCIE_ROOT>; 1847 clock-names = "usb", "pcie"; 1848 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 1849 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 1850 <&pgc_hsiomix>, <&pgc_pcie_phy>; 1851 power-domain-names = "bus", "usb", "usb-phy1", 1852 "usb-phy2", "pcie", "pcie-phy"; 1853 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 1854 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 1855 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 1856 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 1857 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 1858 #power-domain-cells = <1>; 1859 #clock-cells = <0>; 1860 }; 1861 1862 hdmi_blk_ctrl: blk-ctrl@32fc0000 { 1863 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; 1864 reg = <0x32fc0000 0x1000>; 1865 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 1866 <&clk IMX8MP_CLK_HDMI_ROOT>, 1867 <&clk IMX8MP_CLK_HDMI_REF_266M>, 1868 <&clk IMX8MP_CLK_HDMI_24M>, 1869 <&clk IMX8MP_CLK_HDMI_FDCC_TST>; 1870 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; 1871 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, 1872 <&pgc_hdmimix>, <&pgc_hdmimix>, 1873 <&pgc_hdmimix>, <&pgc_hdmimix>, 1874 <&pgc_hdmimix>, <&pgc_hdmi_phy>, 1875 <&pgc_hdmimix>, <&pgc_hdmimix>; 1876 power-domain-names = "bus", "irqsteer", "lcdif", 1877 "pai", "pvi", "trng", 1878 "hdmi-tx", "hdmi-tx-phy", 1879 "hdcp", "hrv"; 1880 #power-domain-cells = <1>; 1881 }; 1882 }; 1883 1884 pcie: pcie@33800000 { 1885 compatible = "fsl,imx8mp-pcie"; 1886 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1887 reg-names = "dbi", "config"; 1888 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1889 <&clk IMX8MP_CLK_HSIO_AXI>, 1890 <&clk IMX8MP_CLK_PCIE_ROOT>; 1891 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1892 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 1893 assigned-clock-rates = <10000000>; 1894 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 1895 #address-cells = <3>; 1896 #size-cells = <2>; 1897 device_type = "pci"; 1898 bus-range = <0x00 0xff>; 1899 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1900 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1901 num-lanes = <1>; 1902 num-viewport = <4>; 1903 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1904 interrupt-names = "msi"; 1905 #interrupt-cells = <1>; 1906 interrupt-map-mask = <0 0 0 0x7>; 1907 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1908 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1909 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1910 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1911 fsl,max-link-speed = <3>; 1912 linux,pci-domain = <0>; 1913 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1914 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1915 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1916 reset-names = "apps", "turnoff"; 1917 phys = <&pcie_phy>; 1918 phy-names = "pcie-phy"; 1919 status = "disabled"; 1920 }; 1921 1922 pcie_ep: pcie-ep@33800000 { 1923 compatible = "fsl,imx8mp-pcie-ep"; 1924 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; 1925 reg-names = "dbi", "addr_space"; 1926 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1927 <&clk IMX8MP_CLK_HSIO_AXI>, 1928 <&clk IMX8MP_CLK_PCIE_ROOT>; 1929 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1930 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 1931 assigned-clock-rates = <10000000>; 1932 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 1933 num-lanes = <1>; 1934 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 1935 interrupt-names = "dma"; 1936 fsl,max-link-speed = <3>; 1937 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1938 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1939 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1940 reset-names = "apps", "turnoff"; 1941 phys = <&pcie_phy>; 1942 phy-names = "pcie-phy"; 1943 num-ib-windows = <4>; 1944 num-ob-windows = <4>; 1945 status = "disabled"; 1946 }; 1947 1948 gpu3d: gpu@38000000 { 1949 compatible = "vivante,gc"; 1950 reg = <0x38000000 0x8000>; 1951 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1952 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 1953 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 1954 <&clk IMX8MP_CLK_GPU_ROOT>, 1955 <&clk IMX8MP_CLK_GPU_AHB>; 1956 clock-names = "core", "shader", "bus", "reg"; 1957 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 1958 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 1959 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1960 <&clk IMX8MP_SYS_PLL1_800M>; 1961 assigned-clock-rates = <800000000>, <800000000>; 1962 power-domains = <&pgc_gpu3d>; 1963 }; 1964 1965 gpu2d: gpu@38008000 { 1966 compatible = "vivante,gc"; 1967 reg = <0x38008000 0x8000>; 1968 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1969 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 1970 <&clk IMX8MP_CLK_GPU_ROOT>, 1971 <&clk IMX8MP_CLK_GPU_AHB>; 1972 clock-names = "core", "bus", "reg"; 1973 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 1974 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1975 assigned-clock-rates = <800000000>; 1976 power-domains = <&pgc_gpu2d>; 1977 }; 1978 1979 vpu_g1: video-codec@38300000 { 1980 compatible = "nxp,imx8mm-vpu-g1"; 1981 reg = <0x38300000 0x10000>; 1982 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1983 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 1984 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 1985 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 1986 assigned-clock-rates = <600000000>; 1987 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 1988 }; 1989 1990 vpu_g2: video-codec@38310000 { 1991 compatible = "nxp,imx8mq-vpu-g2"; 1992 reg = <0x38310000 0x10000>; 1993 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1994 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 1995 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; 1996 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1997 assigned-clock-rates = <500000000>; 1998 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 1999 }; 2000 2001 vpumix_blk_ctrl: blk-ctrl@38330000 { 2002 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 2003 reg = <0x38330000 0x100>; 2004 #power-domain-cells = <1>; 2005 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 2006 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 2007 power-domain-names = "bus", "g1", "g2", "vc8000e"; 2008 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 2009 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 2010 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 2011 clock-names = "g1", "g2", "vc8000e"; 2012 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; 2013 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2014 assigned-clock-rates = <600000000>, <600000000>; 2015 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 2016 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 2017 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 2018 interconnect-names = "g1", "g2", "vc8000e"; 2019 }; 2020 2021 npu: npu@38500000 { 2022 compatible = "vivante,gc"; 2023 reg = <0x38500000 0x200000>; 2024 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2025 clocks = <&clk IMX8MP_CLK_NPU_ROOT>, 2026 <&clk IMX8MP_CLK_NPU_ROOT>, 2027 <&clk IMX8MP_CLK_ML_AXI>, 2028 <&clk IMX8MP_CLK_ML_AHB>; 2029 clock-names = "core", "shader", "bus", "reg"; 2030 power-domains = <&pgc_mlmix>; 2031 }; 2032 2033 gic: interrupt-controller@38800000 { 2034 compatible = "arm,gic-v3"; 2035 reg = <0x38800000 0x10000>, 2036 <0x38880000 0xc0000>; 2037 #interrupt-cells = <3>; 2038 interrupt-controller; 2039 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2040 interrupt-parent = <&gic>; 2041 }; 2042 2043 edacmc: memory-controller@3d400000 { 2044 compatible = "snps,ddrc-3.80a"; 2045 reg = <0x3d400000 0x400000>; 2046 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2047 }; 2048 2049 ddr-pmu@3d800000 { 2050 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 2051 reg = <0x3d800000 0x400000>; 2052 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2053 }; 2054 2055 usb3_phy0: usb-phy@381f0040 { 2056 compatible = "fsl,imx8mp-usb-phy"; 2057 reg = <0x381f0040 0x40>; 2058 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2059 clock-names = "phy"; 2060 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2061 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2062 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 2063 #phy-cells = <0>; 2064 status = "disabled"; 2065 }; 2066 2067 usb3_0: usb@32f10100 { 2068 compatible = "fsl,imx8mp-dwc3"; 2069 reg = <0x32f10100 0x8>, 2070 <0x381f0000 0x20>; 2071 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2072 <&clk IMX8MP_CLK_USB_SUSP>; 2073 clock-names = "hsio", "suspend"; 2074 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2075 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2076 #address-cells = <1>; 2077 #size-cells = <1>; 2078 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2079 ranges; 2080 status = "disabled"; 2081 2082 usb_dwc3_0: usb@38100000 { 2083 compatible = "snps,dwc3"; 2084 reg = <0x38100000 0x10000>; 2085 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2086 <&clk IMX8MP_CLK_USB_CORE_REF>, 2087 <&clk IMX8MP_CLK_USB_SUSP>; 2088 clock-names = "bus_early", "ref", "suspend"; 2089 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2090 phys = <&usb3_phy0>, <&usb3_phy0>; 2091 phy-names = "usb2-phy", "usb3-phy"; 2092 snps,gfladj-refclk-lpm-sel-quirk; 2093 snps,parkmode-disable-ss-quirk; 2094 }; 2095 2096 }; 2097 2098 usb3_phy1: usb-phy@382f0040 { 2099 compatible = "fsl,imx8mp-usb-phy"; 2100 reg = <0x382f0040 0x40>; 2101 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2102 clock-names = "phy"; 2103 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2104 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2105 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 2106 #phy-cells = <0>; 2107 status = "disabled"; 2108 }; 2109 2110 usb3_1: usb@32f10108 { 2111 compatible = "fsl,imx8mp-dwc3"; 2112 reg = <0x32f10108 0x8>, 2113 <0x382f0000 0x20>; 2114 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2115 <&clk IMX8MP_CLK_USB_SUSP>; 2116 clock-names = "hsio", "suspend"; 2117 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2118 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2119 #address-cells = <1>; 2120 #size-cells = <1>; 2121 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2122 ranges; 2123 status = "disabled"; 2124 2125 usb_dwc3_1: usb@38200000 { 2126 compatible = "snps,dwc3"; 2127 reg = <0x38200000 0x10000>; 2128 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2129 <&clk IMX8MP_CLK_USB_CORE_REF>, 2130 <&clk IMX8MP_CLK_USB_SUSP>; 2131 clock-names = "bus_early", "ref", "suspend"; 2132 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 2133 phys = <&usb3_phy1>, <&usb3_phy1>; 2134 phy-names = "usb2-phy", "usb3-phy"; 2135 snps,gfladj-refclk-lpm-sel-quirk; 2136 snps,parkmode-disable-ss-quirk; 2137 }; 2138 }; 2139 2140 dsp: dsp@3b6e8000 { 2141 compatible = "fsl,imx8mp-dsp"; 2142 reg = <0x3b6e8000 0x88000>; 2143 mbox-names = "txdb0", "txdb1", 2144 "rxdb0", "rxdb1"; 2145 mboxes = <&mu2 2 0>, <&mu2 2 1>, 2146 <&mu2 3 0>, <&mu2 3 1>; 2147 memory-region = <&dsp_reserved>; 2148 status = "disabled"; 2149 }; 2150 }; 2151}; 2152