1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mp-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 i2c0 = &i2c1; 27 i2c1 = &i2c2; 28 i2c2 = &i2c3; 29 i2c3 = &i2c4; 30 i2c4 = &i2c5; 31 i2c5 = &i2c6; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 }; 40 41 cpus { 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 A53_0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53"; 48 reg = <0x0>; 49 clock-latency = <61036>; 50 clocks = <&clk IMX8MP_CLK_ARM>; 51 enable-method = "psci"; 52 next-level-cache = <&A53_L2>; 53 #cooling-cells = <2>; 54 }; 55 56 A53_1: cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x1>; 60 clock-latency = <61036>; 61 clocks = <&clk IMX8MP_CLK_ARM>; 62 enable-method = "psci"; 63 next-level-cache = <&A53_L2>; 64 #cooling-cells = <2>; 65 }; 66 67 A53_2: cpu@2 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x2>; 71 clock-latency = <61036>; 72 clocks = <&clk IMX8MP_CLK_ARM>; 73 enable-method = "psci"; 74 next-level-cache = <&A53_L2>; 75 #cooling-cells = <2>; 76 }; 77 78 A53_3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x3>; 82 clock-latency = <61036>; 83 clocks = <&clk IMX8MP_CLK_ARM>; 84 enable-method = "psci"; 85 next-level-cache = <&A53_L2>; 86 #cooling-cells = <2>; 87 }; 88 89 A53_L2: l2-cache0 { 90 compatible = "cache"; 91 }; 92 }; 93 94 osc_32k: clock-osc-32k { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <32768>; 98 clock-output-names = "osc_32k"; 99 }; 100 101 osc_24m: clock-osc-24m { 102 compatible = "fixed-clock"; 103 #clock-cells = <0>; 104 clock-frequency = <24000000>; 105 clock-output-names = "osc_24m"; 106 }; 107 108 clk_ext1: clock-ext1 { 109 compatible = "fixed-clock"; 110 #clock-cells = <0>; 111 clock-frequency = <133000000>; 112 clock-output-names = "clk_ext1"; 113 }; 114 115 clk_ext2: clock-ext2 { 116 compatible = "fixed-clock"; 117 #clock-cells = <0>; 118 clock-frequency = <133000000>; 119 clock-output-names = "clk_ext2"; 120 }; 121 122 clk_ext3: clock-ext3 { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 clock-frequency = <133000000>; 126 clock-output-names = "clk_ext3"; 127 }; 128 129 clk_ext4: clock-ext4 { 130 compatible = "fixed-clock"; 131 #clock-cells = <0>; 132 clock-frequency= <133000000>; 133 clock-output-names = "clk_ext4"; 134 }; 135 136 psci { 137 compatible = "arm,psci-1.0"; 138 method = "smc"; 139 }; 140 141 thermal-zones { 142 cpu-thermal { 143 polling-delay-passive = <250>; 144 polling-delay = <2000>; 145 thermal-sensors = <&tmu 0>; 146 trips { 147 cpu_alert0: trip0 { 148 temperature = <85000>; 149 hysteresis = <2000>; 150 type = "passive"; 151 }; 152 153 cpu_crit0: trip1 { 154 temperature = <95000>; 155 hysteresis = <2000>; 156 type = "critical"; 157 }; 158 }; 159 160 cooling-maps { 161 map0 { 162 trip = <&cpu_alert0>; 163 cooling-device = 164 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 165 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 166 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 167 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 168 }; 169 }; 170 }; 171 172 soc-thermal { 173 polling-delay-passive = <250>; 174 polling-delay = <2000>; 175 thermal-sensors = <&tmu 1>; 176 trips { 177 soc_alert0: trip0 { 178 temperature = <85000>; 179 hysteresis = <2000>; 180 type = "passive"; 181 }; 182 183 soc_crit0: trip1 { 184 temperature = <95000>; 185 hysteresis = <2000>; 186 type = "critical"; 187 }; 188 }; 189 190 cooling-maps { 191 map0 { 192 trip = <&soc_alert0>; 193 cooling-device = 194 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 195 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 196 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 197 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 198 }; 199 }; 200 }; 201 }; 202 203 timer { 204 compatible = "arm,armv8-timer"; 205 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 206 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 207 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 208 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 209 clock-frequency = <8000000>; 210 arm,no-tick-in-suspend; 211 }; 212 213 soc@0 { 214 compatible = "simple-bus"; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges = <0x0 0x0 0x0 0x3e000000>; 218 219 aips1: bus@30000000 { 220 compatible = "fsl,aips-bus", "simple-bus"; 221 reg = <0x30000000 0x400000>; 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges; 225 226 gpio1: gpio@30200000 { 227 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 228 reg = <0x30200000 0x10000>; 229 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 232 gpio-controller; 233 #gpio-cells = <2>; 234 interrupt-controller; 235 #interrupt-cells = <2>; 236 gpio-ranges = <&iomuxc 0 5 30>; 237 }; 238 239 gpio2: gpio@30210000 { 240 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 241 reg = <0x30210000 0x10000>; 242 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 245 gpio-controller; 246 #gpio-cells = <2>; 247 interrupt-controller; 248 #interrupt-cells = <2>; 249 gpio-ranges = <&iomuxc 0 35 21>; 250 }; 251 252 gpio3: gpio@30220000 { 253 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 254 reg = <0x30220000 0x10000>; 255 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 258 gpio-controller; 259 #gpio-cells = <2>; 260 interrupt-controller; 261 #interrupt-cells = <2>; 262 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>; 263 }; 264 265 gpio4: gpio@30230000 { 266 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 267 reg = <0x30230000 0x10000>; 268 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 271 gpio-controller; 272 #gpio-cells = <2>; 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 gpio-ranges = <&iomuxc 0 82 32>; 276 }; 277 278 gpio5: gpio@30240000 { 279 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 280 reg = <0x30240000 0x10000>; 281 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 284 gpio-controller; 285 #gpio-cells = <2>; 286 interrupt-controller; 287 #interrupt-cells = <2>; 288 gpio-ranges = <&iomuxc 0 114 30>; 289 }; 290 291 tmu: tmu@30260000 { 292 compatible = "fsl,imx8mp-tmu"; 293 reg = <0x30260000 0x10000>; 294 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 295 #thermal-sensor-cells = <1>; 296 }; 297 298 wdog1: watchdog@30280000 { 299 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 300 reg = <0x30280000 0x10000>; 301 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 303 status = "disabled"; 304 }; 305 306 iomuxc: pinctrl@30330000 { 307 compatible = "fsl,imx8mp-iomuxc"; 308 reg = <0x30330000 0x10000>; 309 }; 310 311 gpr: iomuxc-gpr@30340000 { 312 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 313 reg = <0x30340000 0x10000>; 314 }; 315 316 ocotp: efuse@30350000 { 317 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 318 reg = <0x30350000 0x10000>; 319 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 320 /* For nvmem subnodes */ 321 #address-cells = <1>; 322 #size-cells = <1>; 323 324 cpu_speed_grade: speed-grade@10 { 325 reg = <0x10 4>; 326 }; 327 }; 328 329 anatop: anatop@30360000 { 330 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", 331 "syscon"; 332 reg = <0x30360000 0x10000>; 333 }; 334 335 snvs: snvs@30370000 { 336 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 337 reg = <0x30370000 0x10000>; 338 339 snvs_rtc: snvs-rtc-lp { 340 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 341 regmap =<&snvs>; 342 offset = <0x34>; 343 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 346 clock-names = "snvs-rtc"; 347 }; 348 349 snvs_pwrkey: snvs-powerkey { 350 compatible = "fsl,sec-v4.0-pwrkey"; 351 regmap = <&snvs>; 352 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 354 clock-names = "snvs-pwrkey"; 355 linux,keycode = <KEY_POWER>; 356 wakeup-source; 357 status = "disabled"; 358 }; 359 }; 360 361 clk: clock-controller@30380000 { 362 compatible = "fsl,imx8mp-ccm"; 363 reg = <0x30380000 0x10000>; 364 #clock-cells = <1>; 365 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 366 <&clk_ext3>, <&clk_ext4>; 367 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 368 "clk_ext3", "clk_ext4"; 369 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 370 <&clk IMX8MP_CLK_A53_CORE>, 371 <&clk IMX8MP_CLK_NOC>, 372 <&clk IMX8MP_CLK_NOC_IO>, 373 <&clk IMX8MP_CLK_GIC>, 374 <&clk IMX8MP_CLK_AUDIO_AHB>, 375 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, 376 <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, 377 <&clk IMX8MP_AUDIO_PLL1>, 378 <&clk IMX8MP_AUDIO_PLL2>; 379 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 380 <&clk IMX8MP_ARM_PLL_OUT>, 381 <&clk IMX8MP_SYS_PLL2_1000M>, 382 <&clk IMX8MP_SYS_PLL1_800M>, 383 <&clk IMX8MP_SYS_PLL2_500M>, 384 <&clk IMX8MP_SYS_PLL1_800M>, 385 <&clk IMX8MP_SYS_PLL1_800M>; 386 assigned-clock-rates = <0>, <0>, 387 <1000000000>, 388 <800000000>, 389 <500000000>, 390 <400000000>, 391 <800000000>, 392 <400000000>, 393 <393216000>, 394 <361267200>; 395 }; 396 397 src: reset-controller@30390000 { 398 compatible = "fsl,imx8mp-src", "syscon"; 399 reg = <0x30390000 0x10000>; 400 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 401 #reset-cells = <1>; 402 }; 403 }; 404 405 aips2: bus@30400000 { 406 compatible = "fsl,aips-bus", "simple-bus"; 407 reg = <0x30400000 0x400000>; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 ranges; 411 412 pwm1: pwm@30660000 { 413 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 414 reg = <0x30660000 0x10000>; 415 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 417 <&clk IMX8MP_CLK_PWM1_ROOT>; 418 clock-names = "ipg", "per"; 419 #pwm-cells = <2>; 420 status = "disabled"; 421 }; 422 423 pwm2: pwm@30670000 { 424 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 425 reg = <0x30670000 0x10000>; 426 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 428 <&clk IMX8MP_CLK_PWM2_ROOT>; 429 clock-names = "ipg", "per"; 430 #pwm-cells = <2>; 431 status = "disabled"; 432 }; 433 434 pwm3: pwm@30680000 { 435 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 436 reg = <0x30680000 0x10000>; 437 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 439 <&clk IMX8MP_CLK_PWM3_ROOT>; 440 clock-names = "ipg", "per"; 441 #pwm-cells = <2>; 442 status = "disabled"; 443 }; 444 445 pwm4: pwm@30690000 { 446 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 447 reg = <0x30690000 0x10000>; 448 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 450 <&clk IMX8MP_CLK_PWM4_ROOT>; 451 clock-names = "ipg", "per"; 452 #pwm-cells = <2>; 453 status = "disabled"; 454 }; 455 456 system_counter: timer@306a0000 { 457 compatible = "nxp,sysctr-timer"; 458 reg = <0x306a0000 0x20000>; 459 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&osc_24m>; 461 clock-names = "per"; 462 }; 463 }; 464 465 aips3: bus@30800000 { 466 compatible = "fsl,aips-bus", "simple-bus"; 467 reg = <0x30800000 0x400000>; 468 #address-cells = <1>; 469 #size-cells = <1>; 470 ranges; 471 472 ecspi1: spi@30820000 { 473 #address-cells = <1>; 474 #size-cells = <0>; 475 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 476 reg = <0x30820000 0x10000>; 477 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 478 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 479 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 480 clock-names = "ipg", "per"; 481 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 482 dma-names = "rx", "tx"; 483 status = "disabled"; 484 }; 485 486 ecspi2: spi@30830000 { 487 #address-cells = <1>; 488 #size-cells = <0>; 489 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 490 reg = <0x30830000 0x10000>; 491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 493 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 494 clock-names = "ipg", "per"; 495 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 496 dma-names = "rx", "tx"; 497 status = "disabled"; 498 }; 499 500 ecspi3: spi@30840000 { 501 #address-cells = <1>; 502 #size-cells = <0>; 503 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 504 reg = <0x30840000 0x10000>; 505 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 507 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 508 clock-names = "ipg", "per"; 509 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 510 dma-names = "rx", "tx"; 511 status = "disabled"; 512 }; 513 514 uart1: serial@30860000 { 515 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 516 reg = <0x30860000 0x10000>; 517 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 519 <&clk IMX8MP_CLK_UART1_ROOT>; 520 clock-names = "ipg", "per"; 521 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 522 dma-names = "rx", "tx"; 523 status = "disabled"; 524 }; 525 526 uart3: serial@30880000 { 527 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 528 reg = <0x30880000 0x10000>; 529 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 531 <&clk IMX8MP_CLK_UART3_ROOT>; 532 clock-names = "ipg", "per"; 533 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 534 dma-names = "rx", "tx"; 535 status = "disabled"; 536 }; 537 538 uart2: serial@30890000 { 539 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 540 reg = <0x30890000 0x10000>; 541 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 543 <&clk IMX8MP_CLK_UART2_ROOT>; 544 clock-names = "ipg", "per"; 545 status = "disabled"; 546 }; 547 548 crypto: crypto@30900000 { 549 compatible = "fsl,sec-v4.0"; 550 #address-cells = <1>; 551 #size-cells = <1>; 552 reg = <0x30900000 0x40000>; 553 ranges = <0 0x30900000 0x40000>; 554 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&clk IMX8MP_CLK_AHB>, 556 <&clk IMX8MP_CLK_IPG_ROOT>; 557 clock-names = "aclk", "ipg"; 558 559 sec_jr0: jr@1000 { 560 compatible = "fsl,sec-v4.0-job-ring"; 561 reg = <0x1000 0x1000>; 562 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 563 }; 564 565 sec_jr1: jr@2000 { 566 compatible = "fsl,sec-v4.0-job-ring"; 567 reg = <0x2000 0x1000>; 568 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 569 }; 570 571 sec_jr2: jr@3000 { 572 compatible = "fsl,sec-v4.0-job-ring"; 573 reg = <0x3000 0x1000>; 574 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 575 }; 576 }; 577 578 i2c1: i2c@30a20000 { 579 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 reg = <0x30a20000 0x10000>; 583 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 585 status = "disabled"; 586 }; 587 588 i2c2: i2c@30a30000 { 589 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 reg = <0x30a30000 0x10000>; 593 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 595 status = "disabled"; 596 }; 597 598 i2c3: i2c@30a40000 { 599 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 reg = <0x30a40000 0x10000>; 603 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 605 status = "disabled"; 606 }; 607 608 i2c4: i2c@30a50000 { 609 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 reg = <0x30a50000 0x10000>; 613 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 615 status = "disabled"; 616 }; 617 618 uart4: serial@30a60000 { 619 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 620 reg = <0x30a60000 0x10000>; 621 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 623 <&clk IMX8MP_CLK_UART4_ROOT>; 624 clock-names = "ipg", "per"; 625 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 626 dma-names = "rx", "tx"; 627 status = "disabled"; 628 }; 629 630 mu: mailbox@30aa0000 { 631 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 632 reg = <0x30aa0000 0x10000>; 633 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 635 #mbox-cells = <2>; 636 }; 637 638 i2c5: i2c@30ad0000 { 639 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 reg = <0x30ad0000 0x10000>; 643 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 645 status = "disabled"; 646 }; 647 648 i2c6: i2c@30ae0000 { 649 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 reg = <0x30ae0000 0x10000>; 653 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 655 status = "disabled"; 656 }; 657 658 usdhc1: mmc@30b40000 { 659 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 660 reg = <0x30b40000 0x10000>; 661 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&clk IMX8MP_CLK_DUMMY>, 663 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 664 <&clk IMX8MP_CLK_USDHC1_ROOT>; 665 clock-names = "ipg", "ahb", "per"; 666 fsl,tuning-start-tap = <20>; 667 fsl,tuning-step= <2>; 668 bus-width = <4>; 669 status = "disabled"; 670 }; 671 672 usdhc2: mmc@30b50000 { 673 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 674 reg = <0x30b50000 0x10000>; 675 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&clk IMX8MP_CLK_DUMMY>, 677 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 678 <&clk IMX8MP_CLK_USDHC2_ROOT>; 679 clock-names = "ipg", "ahb", "per"; 680 fsl,tuning-start-tap = <20>; 681 fsl,tuning-step= <2>; 682 bus-width = <4>; 683 status = "disabled"; 684 }; 685 686 usdhc3: mmc@30b60000 { 687 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 688 reg = <0x30b60000 0x10000>; 689 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&clk IMX8MP_CLK_DUMMY>, 691 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 692 <&clk IMX8MP_CLK_USDHC3_ROOT>; 693 clock-names = "ipg", "ahb", "per"; 694 fsl,tuning-start-tap = <20>; 695 fsl,tuning-step= <2>; 696 bus-width = <4>; 697 status = "disabled"; 698 }; 699 700 sdma1: dma-controller@30bd0000 { 701 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 702 reg = <0x30bd0000 0x10000>; 703 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 705 <&clk IMX8MP_CLK_SDMA1_ROOT>; 706 clock-names = "ipg", "ahb"; 707 #dma-cells = <3>; 708 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 709 }; 710 711 fec: ethernet@30be0000 { 712 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 713 reg = <0x30be0000 0x10000>; 714 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 718 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 719 <&clk IMX8MP_CLK_ENET_TIMER>, 720 <&clk IMX8MP_CLK_ENET_REF>, 721 <&clk IMX8MP_CLK_ENET_PHY_REF>; 722 clock-names = "ipg", "ahb", "ptp", 723 "enet_clk_ref", "enet_out"; 724 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 725 <&clk IMX8MP_CLK_ENET_TIMER>, 726 <&clk IMX8MP_CLK_ENET_REF>, 727 <&clk IMX8MP_CLK_ENET_TIMER>; 728 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 729 <&clk IMX8MP_SYS_PLL2_100M>, 730 <&clk IMX8MP_SYS_PLL2_125M>; 731 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 732 fsl,num-tx-queues = <3>; 733 fsl,num-rx-queues = <3>; 734 status = "disabled"; 735 }; 736 }; 737 738 gic: interrupt-controller@38800000 { 739 compatible = "arm,gic-v3"; 740 reg = <0x38800000 0x10000>, 741 <0x38880000 0xc0000>; 742 #interrupt-cells = <3>; 743 interrupt-controller; 744 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 745 interrupt-parent = <&gic>; 746 }; 747 748 ddr-pmu@3d800000 { 749 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 750 reg = <0x3d800000 0x400000>; 751 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 752 }; 753 }; 754}; 755