1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 A53_0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&A53_L2>; 64 nvmem-cells = <&cpu_speed_grade>; 65 nvmem-cell-names = "speed_grade"; 66 operating-points-v2 = <&a53_opp_table>; 67 #cooling-cells = <2>; 68 }; 69 70 A53_1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x1>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MP_CLK_ARM>; 76 enable-method = "psci"; 77 i-cache-size = <0x8000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <128>; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A53_2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x2>; 92 clock-latency = <61036>; 93 clocks = <&clk IMX8MP_CLK_ARM>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 }; 105 106 A53_3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x3>; 110 clock-latency = <61036>; 111 clocks = <&clk IMX8MP_CLK_ARM>; 112 enable-method = "psci"; 113 i-cache-size = <0x8000>; 114 i-cache-line-size = <64>; 115 i-cache-sets = <256>; 116 d-cache-size = <0x8000>; 117 d-cache-line-size = <64>; 118 d-cache-sets = <128>; 119 next-level-cache = <&A53_L2>; 120 operating-points-v2 = <&a53_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A53_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-unified; 127 cache-level = <2>; 128 cache-size = <0x80000>; 129 cache-line-size = <64>; 130 cache-sets = <512>; 131 }; 132 }; 133 134 a53_opp_table: opp-table { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-1200000000 { 139 opp-hz = /bits/ 64 <1200000000>; 140 opp-microvolt = <850000>; 141 opp-supported-hw = <0x8a0>, <0x7>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 146 opp-1600000000 { 147 opp-hz = /bits/ 64 <1600000000>; 148 opp-microvolt = <950000>; 149 opp-supported-hw = <0xa0>, <0x7>; 150 clock-latency-ns = <150000>; 151 opp-suspend; 152 }; 153 154 opp-1800000000 { 155 opp-hz = /bits/ 64 <1800000000>; 156 opp-microvolt = <1000000>; 157 opp-supported-hw = <0x20>, <0x3>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 }; 162 163 osc_32k: clock-osc-32k { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <32768>; 167 clock-output-names = "osc_32k"; 168 }; 169 170 osc_24m: clock-osc-24m { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <24000000>; 174 clock-output-names = "osc_24m"; 175 }; 176 177 clk_ext1: clock-ext1 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext1"; 182 }; 183 184 clk_ext2: clock-ext2 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <133000000>; 188 clock-output-names = "clk_ext2"; 189 }; 190 191 clk_ext3: clock-ext3 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext3"; 196 }; 197 198 clk_ext4: clock-ext4 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext4"; 203 }; 204 205 reserved-memory { 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges; 209 210 dsp_reserved: dsp@92400000 { 211 reg = <0 0x92400000 0 0x2000000>; 212 no-map; 213 }; 214 }; 215 216 pmu { 217 compatible = "arm,cortex-a53-pmu"; 218 interrupts = <GIC_PPI 7 219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0"; 224 method = "smc"; 225 }; 226 227 thermal-zones { 228 cpu-thermal { 229 polling-delay-passive = <250>; 230 polling-delay = <2000>; 231 thermal-sensors = <&tmu 0>; 232 trips { 233 cpu_alert0: trip0 { 234 temperature = <85000>; 235 hysteresis = <2000>; 236 type = "passive"; 237 }; 238 239 cpu_crit0: trip1 { 240 temperature = <95000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 }; 245 246 cooling-maps { 247 map0 { 248 trip = <&cpu_alert0>; 249 cooling-device = 250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 254 }; 255 }; 256 }; 257 258 soc-thermal { 259 polling-delay-passive = <250>; 260 polling-delay = <2000>; 261 thermal-sensors = <&tmu 1>; 262 trips { 263 soc_alert0: trip0 { 264 temperature = <85000>; 265 hysteresis = <2000>; 266 type = "passive"; 267 }; 268 269 soc_crit0: trip1 { 270 temperature = <95000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 276 cooling-maps { 277 map0 { 278 trip = <&soc_alert0>; 279 cooling-device = 280 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 281 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 282 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 283 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 284 }; 285 }; 286 }; 287 }; 288 289 timer { 290 compatible = "arm,armv8-timer"; 291 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 293 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 294 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 295 clock-frequency = <8000000>; 296 arm,no-tick-in-suspend; 297 }; 298 299 soc: soc@0 { 300 compatible = "fsl,imx8mp-soc", "simple-bus"; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0x0 0x0 0x0 0x3e000000>; 304 nvmem-cells = <&imx8mp_uid>; 305 nvmem-cell-names = "soc_unique_id"; 306 307 aips1: bus@30000000 { 308 compatible = "fsl,aips-bus", "simple-bus"; 309 reg = <0x30000000 0x400000>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges; 313 314 gpio1: gpio@30200000 { 315 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 316 reg = <0x30200000 0x10000>; 317 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 gpio-ranges = <&iomuxc 0 5 30>; 325 }; 326 327 gpio2: gpio@30210000 { 328 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 329 reg = <0x30210000 0x10000>; 330 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 gpio-ranges = <&iomuxc 0 35 21>; 338 }; 339 340 gpio3: gpio@30220000 { 341 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 342 reg = <0x30220000 0x10000>; 343 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 351 }; 352 353 gpio4: gpio@30230000 { 354 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 355 reg = <0x30230000 0x10000>; 356 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 gpio-ranges = <&iomuxc 0 82 32>; 364 }; 365 366 gpio5: gpio@30240000 { 367 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 368 reg = <0x30240000 0x10000>; 369 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 gpio-ranges = <&iomuxc 0 114 30>; 377 }; 378 379 tmu: tmu@30260000 { 380 compatible = "fsl,imx8mp-tmu"; 381 reg = <0x30260000 0x10000>; 382 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 383 nvmem-cells = <&tmu_calib>; 384 nvmem-cell-names = "calib"; 385 #thermal-sensor-cells = <1>; 386 }; 387 388 wdog1: watchdog@30280000 { 389 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 390 reg = <0x30280000 0x10000>; 391 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 393 status = "disabled"; 394 }; 395 396 wdog2: watchdog@30290000 { 397 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 398 reg = <0x30290000 0x10000>; 399 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 401 status = "disabled"; 402 }; 403 404 wdog3: watchdog@302a0000 { 405 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 406 reg = <0x302a0000 0x10000>; 407 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 409 status = "disabled"; 410 }; 411 412 gpt1: timer@302d0000 { 413 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 414 reg = <0x302d0000 0x10000>; 415 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; 417 clock-names = "ipg", "per"; 418 }; 419 420 gpt2: timer@302e0000 { 421 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 422 reg = <0x302e0000 0x10000>; 423 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; 425 clock-names = "ipg", "per"; 426 }; 427 428 gpt3: timer@302f0000 { 429 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 430 reg = <0x302f0000 0x10000>; 431 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; 433 clock-names = "ipg", "per"; 434 }; 435 436 iomuxc: pinctrl@30330000 { 437 compatible = "fsl,imx8mp-iomuxc"; 438 reg = <0x30330000 0x10000>; 439 }; 440 441 gpr: syscon@30340000 { 442 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 443 reg = <0x30340000 0x10000>; 444 }; 445 446 ocotp: efuse@30350000 { 447 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 448 reg = <0x30350000 0x10000>; 449 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 450 /* For nvmem subnodes */ 451 #address-cells = <1>; 452 #size-cells = <1>; 453 454 /* 455 * The register address below maps to the MX8M 456 * Fusemap Description Table entries this way. 457 * Assuming 458 * reg = <ADDR SIZE>; 459 * then 460 * Fuse Address = (ADDR * 4) + 0x400 461 * Note that if SIZE is greater than 4, then 462 * each subsequent fuse is located at offset 463 * +0x10 in Fusemap Description Table (e.g. 464 * reg = <0x8 0x8> describes fuses 0x420 and 465 * 0x430). 466 */ 467 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 468 reg = <0x8 0x8>; 469 }; 470 471 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 472 reg = <0x10 4>; 473 }; 474 475 eth_mac1: mac-address@90 { /* 0x640 */ 476 reg = <0x90 6>; 477 }; 478 479 eth_mac2: mac-address@96 { /* 0x658 */ 480 reg = <0x96 6>; 481 }; 482 483 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 484 reg = <0x264 0x10>; 485 }; 486 }; 487 488 anatop: clock-controller@30360000 { 489 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 490 reg = <0x30360000 0x10000>; 491 #clock-cells = <1>; 492 }; 493 494 snvs: snvs@30370000 { 495 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 496 reg = <0x30370000 0x10000>; 497 498 snvs_rtc: snvs-rtc-lp { 499 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 500 regmap =<&snvs>; 501 offset = <0x34>; 502 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 505 clock-names = "snvs-rtc"; 506 }; 507 508 snvs_pwrkey: snvs-powerkey { 509 compatible = "fsl,sec-v4.0-pwrkey"; 510 regmap = <&snvs>; 511 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 513 clock-names = "snvs-pwrkey"; 514 linux,keycode = <KEY_POWER>; 515 wakeup-source; 516 status = "disabled"; 517 }; 518 519 snvs_lpgpr: snvs-lpgpr { 520 compatible = "fsl,imx8mp-snvs-lpgpr", 521 "fsl,imx7d-snvs-lpgpr"; 522 }; 523 }; 524 525 clk: clock-controller@30380000 { 526 compatible = "fsl,imx8mp-ccm"; 527 reg = <0x30380000 0x10000>; 528 #clock-cells = <1>; 529 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 530 <&clk_ext3>, <&clk_ext4>; 531 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 532 "clk_ext3", "clk_ext4"; 533 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 534 <&clk IMX8MP_CLK_A53_CORE>, 535 <&clk IMX8MP_CLK_NOC>, 536 <&clk IMX8MP_CLK_NOC_IO>, 537 <&clk IMX8MP_CLK_GIC>, 538 <&clk IMX8MP_CLK_AUDIO_AHB>, 539 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, 540 <&clk IMX8MP_AUDIO_PLL1>, 541 <&clk IMX8MP_AUDIO_PLL2>; 542 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 543 <&clk IMX8MP_ARM_PLL_OUT>, 544 <&clk IMX8MP_SYS_PLL2_1000M>, 545 <&clk IMX8MP_SYS_PLL1_800M>, 546 <&clk IMX8MP_SYS_PLL2_500M>, 547 <&clk IMX8MP_SYS_PLL1_800M>, 548 <&clk IMX8MP_SYS_PLL1_800M>; 549 assigned-clock-rates = <0>, <0>, 550 <1000000000>, 551 <800000000>, 552 <500000000>, 553 <400000000>, 554 <800000000>, 555 <393216000>, 556 <361267200>; 557 }; 558 559 src: reset-controller@30390000 { 560 compatible = "fsl,imx8mp-src", "syscon"; 561 reg = <0x30390000 0x10000>; 562 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 563 #reset-cells = <1>; 564 }; 565 566 gpc: gpc@303a0000 { 567 compatible = "fsl,imx8mp-gpc"; 568 reg = <0x303a0000 0x1000>; 569 interrupt-parent = <&gic>; 570 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 571 interrupt-controller; 572 #interrupt-cells = <3>; 573 574 pgc { 575 #address-cells = <1>; 576 #size-cells = <0>; 577 578 pgc_mipi_phy1: power-domain@0 { 579 #power-domain-cells = <0>; 580 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 581 }; 582 583 pgc_pcie_phy: power-domain@1 { 584 #power-domain-cells = <0>; 585 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 586 }; 587 588 pgc_usb1_phy: power-domain@2 { 589 #power-domain-cells = <0>; 590 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 591 }; 592 593 pgc_usb2_phy: power-domain@3 { 594 #power-domain-cells = <0>; 595 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 596 }; 597 598 pgc_gpu2d: power-domain@6 { 599 #power-domain-cells = <0>; 600 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 601 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 602 power-domains = <&pgc_gpumix>; 603 }; 604 605 pgc_gpumix: power-domain@7 { 606 #power-domain-cells = <0>; 607 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 608 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 609 <&clk IMX8MP_CLK_GPU_AHB>; 610 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 611 <&clk IMX8MP_CLK_GPU_AHB>; 612 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 613 <&clk IMX8MP_SYS_PLL1_800M>; 614 assigned-clock-rates = <800000000>, <400000000>; 615 }; 616 617 pgc_gpu3d: power-domain@9 { 618 #power-domain-cells = <0>; 619 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 620 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 621 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 622 power-domains = <&pgc_gpumix>; 623 }; 624 625 pgc_mediamix: power-domain@10 { 626 #power-domain-cells = <0>; 627 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 628 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 629 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 630 }; 631 632 pgc_mipi_phy2: power-domain@16 { 633 #power-domain-cells = <0>; 634 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 635 }; 636 637 pgc_hsiomix: power-domain@17 { 638 #power-domain-cells = <0>; 639 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 640 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 641 <&clk IMX8MP_CLK_HSIO_ROOT>; 642 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 643 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 644 assigned-clock-rates = <500000000>; 645 }; 646 647 pgc_ispdwp: power-domain@18 { 648 #power-domain-cells = <0>; 649 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 650 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 651 }; 652 653 pgc_vpumix: power-domain@19 { 654 #power-domain-cells = <0>; 655 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 656 clocks =<&clk IMX8MP_CLK_VPU_ROOT>; 657 }; 658 659 pgc_vpu_g1: power-domain@20 { 660 #power-domain-cells = <0>; 661 power-domains = <&pgc_vpumix>; 662 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 663 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 664 }; 665 666 pgc_vpu_g2: power-domain@21 { 667 #power-domain-cells = <0>; 668 power-domains = <&pgc_vpumix>; 669 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 670 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 671 }; 672 673 pgc_vpu_vc8000e: power-domain@22 { 674 #power-domain-cells = <0>; 675 power-domains = <&pgc_vpumix>; 676 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 677 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 678 }; 679 680 pgc_mlmix: power-domain@24 { 681 #power-domain-cells = <0>; 682 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 683 clocks = <&clk IMX8MP_CLK_ML_AXI>, 684 <&clk IMX8MP_CLK_ML_AHB>, 685 <&clk IMX8MP_CLK_NPU_ROOT>; 686 }; 687 }; 688 }; 689 }; 690 691 aips2: bus@30400000 { 692 compatible = "fsl,aips-bus", "simple-bus"; 693 reg = <0x30400000 0x400000>; 694 #address-cells = <1>; 695 #size-cells = <1>; 696 ranges; 697 698 pwm1: pwm@30660000 { 699 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 700 reg = <0x30660000 0x10000>; 701 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 703 <&clk IMX8MP_CLK_PWM1_ROOT>; 704 clock-names = "ipg", "per"; 705 #pwm-cells = <3>; 706 status = "disabled"; 707 }; 708 709 pwm2: pwm@30670000 { 710 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 711 reg = <0x30670000 0x10000>; 712 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 714 <&clk IMX8MP_CLK_PWM2_ROOT>; 715 clock-names = "ipg", "per"; 716 #pwm-cells = <3>; 717 status = "disabled"; 718 }; 719 720 pwm3: pwm@30680000 { 721 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 722 reg = <0x30680000 0x10000>; 723 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 725 <&clk IMX8MP_CLK_PWM3_ROOT>; 726 clock-names = "ipg", "per"; 727 #pwm-cells = <3>; 728 status = "disabled"; 729 }; 730 731 pwm4: pwm@30690000 { 732 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 733 reg = <0x30690000 0x10000>; 734 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 736 <&clk IMX8MP_CLK_PWM4_ROOT>; 737 clock-names = "ipg", "per"; 738 #pwm-cells = <3>; 739 status = "disabled"; 740 }; 741 742 system_counter: timer@306a0000 { 743 compatible = "nxp,sysctr-timer"; 744 reg = <0x306a0000 0x20000>; 745 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&osc_24m>; 747 clock-names = "per"; 748 }; 749 750 gpt6: timer@306e0000 { 751 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 752 reg = <0x306e0000 0x10000>; 753 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; 755 clock-names = "ipg", "per"; 756 }; 757 758 gpt5: timer@306f0000 { 759 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 760 reg = <0x306f0000 0x10000>; 761 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; 763 clock-names = "ipg", "per"; 764 }; 765 766 gpt4: timer@30700000 { 767 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 768 reg = <0x30700000 0x10000>; 769 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; 771 clock-names = "ipg", "per"; 772 }; 773 }; 774 775 aips3: bus@30800000 { 776 compatible = "fsl,aips-bus", "simple-bus"; 777 reg = <0x30800000 0x400000>; 778 #address-cells = <1>; 779 #size-cells = <1>; 780 ranges; 781 782 spba-bus@30800000 { 783 compatible = "fsl,spba-bus", "simple-bus"; 784 reg = <0x30800000 0x100000>; 785 #address-cells = <1>; 786 #size-cells = <1>; 787 ranges; 788 789 ecspi1: spi@30820000 { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 793 reg = <0x30820000 0x10000>; 794 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 796 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 797 clock-names = "ipg", "per"; 798 assigned-clock-rates = <80000000>; 799 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 800 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 801 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 802 dma-names = "rx", "tx"; 803 status = "disabled"; 804 }; 805 806 ecspi2: spi@30830000 { 807 #address-cells = <1>; 808 #size-cells = <0>; 809 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 810 reg = <0x30830000 0x10000>; 811 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 813 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 814 clock-names = "ipg", "per"; 815 assigned-clock-rates = <80000000>; 816 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 817 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 818 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 819 dma-names = "rx", "tx"; 820 status = "disabled"; 821 }; 822 823 ecspi3: spi@30840000 { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 827 reg = <0x30840000 0x10000>; 828 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 830 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 831 clock-names = "ipg", "per"; 832 assigned-clock-rates = <80000000>; 833 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 834 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 835 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 836 dma-names = "rx", "tx"; 837 status = "disabled"; 838 }; 839 840 uart1: serial@30860000 { 841 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 842 reg = <0x30860000 0x10000>; 843 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 845 <&clk IMX8MP_CLK_UART1_ROOT>; 846 clock-names = "ipg", "per"; 847 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 848 dma-names = "rx", "tx"; 849 status = "disabled"; 850 }; 851 852 uart3: serial@30880000 { 853 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 854 reg = <0x30880000 0x10000>; 855 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 857 <&clk IMX8MP_CLK_UART3_ROOT>; 858 clock-names = "ipg", "per"; 859 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 860 dma-names = "rx", "tx"; 861 status = "disabled"; 862 }; 863 864 uart2: serial@30890000 { 865 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 866 reg = <0x30890000 0x10000>; 867 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 869 <&clk IMX8MP_CLK_UART2_ROOT>; 870 clock-names = "ipg", "per"; 871 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 872 dma-names = "rx", "tx"; 873 status = "disabled"; 874 }; 875 876 flexcan1: can@308c0000 { 877 compatible = "fsl,imx8mp-flexcan"; 878 reg = <0x308c0000 0x10000>; 879 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 881 <&clk IMX8MP_CLK_CAN1_ROOT>; 882 clock-names = "ipg", "per"; 883 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 884 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 885 assigned-clock-rates = <40000000>; 886 fsl,clk-source = /bits/ 8 <0>; 887 fsl,stop-mode = <&gpr 0x10 4>; 888 status = "disabled"; 889 }; 890 891 flexcan2: can@308d0000 { 892 compatible = "fsl,imx8mp-flexcan"; 893 reg = <0x308d0000 0x10000>; 894 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 896 <&clk IMX8MP_CLK_CAN2_ROOT>; 897 clock-names = "ipg", "per"; 898 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 899 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 900 assigned-clock-rates = <40000000>; 901 fsl,clk-source = /bits/ 8 <0>; 902 fsl,stop-mode = <&gpr 0x10 5>; 903 status = "disabled"; 904 }; 905 }; 906 907 crypto: crypto@30900000 { 908 compatible = "fsl,sec-v4.0"; 909 #address-cells = <1>; 910 #size-cells = <1>; 911 reg = <0x30900000 0x40000>; 912 ranges = <0 0x30900000 0x40000>; 913 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&clk IMX8MP_CLK_AHB>, 915 <&clk IMX8MP_CLK_IPG_ROOT>; 916 clock-names = "aclk", "ipg"; 917 918 sec_jr0: jr@1000 { 919 compatible = "fsl,sec-v4.0-job-ring"; 920 reg = <0x1000 0x1000>; 921 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 922 status = "disabled"; 923 }; 924 925 sec_jr1: jr@2000 { 926 compatible = "fsl,sec-v4.0-job-ring"; 927 reg = <0x2000 0x1000>; 928 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 929 }; 930 931 sec_jr2: jr@3000 { 932 compatible = "fsl,sec-v4.0-job-ring"; 933 reg = <0x3000 0x1000>; 934 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 935 }; 936 }; 937 938 i2c1: i2c@30a20000 { 939 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 reg = <0x30a20000 0x10000>; 943 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 945 status = "disabled"; 946 }; 947 948 i2c2: i2c@30a30000 { 949 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 reg = <0x30a30000 0x10000>; 953 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 955 status = "disabled"; 956 }; 957 958 i2c3: i2c@30a40000 { 959 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 reg = <0x30a40000 0x10000>; 963 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 965 status = "disabled"; 966 }; 967 968 i2c4: i2c@30a50000 { 969 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 reg = <0x30a50000 0x10000>; 973 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 975 status = "disabled"; 976 }; 977 978 uart4: serial@30a60000 { 979 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 980 reg = <0x30a60000 0x10000>; 981 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 983 <&clk IMX8MP_CLK_UART4_ROOT>; 984 clock-names = "ipg", "per"; 985 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 986 dma-names = "rx", "tx"; 987 status = "disabled"; 988 }; 989 990 mu: mailbox@30aa0000 { 991 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 992 reg = <0x30aa0000 0x10000>; 993 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 995 #mbox-cells = <2>; 996 }; 997 998 mu2: mailbox@30e60000 { 999 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1000 reg = <0x30e60000 0x10000>; 1001 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1002 #mbox-cells = <2>; 1003 status = "disabled"; 1004 }; 1005 1006 i2c5: i2c@30ad0000 { 1007 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 reg = <0x30ad0000 0x10000>; 1011 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 1013 status = "disabled"; 1014 }; 1015 1016 i2c6: i2c@30ae0000 { 1017 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 reg = <0x30ae0000 0x10000>; 1021 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 1023 status = "disabled"; 1024 }; 1025 1026 usdhc1: mmc@30b40000 { 1027 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1028 reg = <0x30b40000 0x10000>; 1029 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&clk IMX8MP_CLK_DUMMY>, 1031 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1032 <&clk IMX8MP_CLK_USDHC1_ROOT>; 1033 clock-names = "ipg", "ahb", "per"; 1034 fsl,tuning-start-tap = <20>; 1035 fsl,tuning-step = <2>; 1036 bus-width = <4>; 1037 status = "disabled"; 1038 }; 1039 1040 usdhc2: mmc@30b50000 { 1041 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1042 reg = <0x30b50000 0x10000>; 1043 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&clk IMX8MP_CLK_DUMMY>, 1045 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1046 <&clk IMX8MP_CLK_USDHC2_ROOT>; 1047 clock-names = "ipg", "ahb", "per"; 1048 fsl,tuning-start-tap = <20>; 1049 fsl,tuning-step = <2>; 1050 bus-width = <4>; 1051 status = "disabled"; 1052 }; 1053 1054 usdhc3: mmc@30b60000 { 1055 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1056 reg = <0x30b60000 0x10000>; 1057 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&clk IMX8MP_CLK_DUMMY>, 1059 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1060 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1061 clock-names = "ipg", "ahb", "per"; 1062 fsl,tuning-start-tap = <20>; 1063 fsl,tuning-step = <2>; 1064 bus-width = <4>; 1065 status = "disabled"; 1066 }; 1067 1068 flexspi: spi@30bb0000 { 1069 compatible = "nxp,imx8mp-fspi"; 1070 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1071 reg-names = "fspi_base", "fspi_mmap"; 1072 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1074 <&clk IMX8MP_CLK_QSPI_ROOT>; 1075 clock-names = "fspi_en", "fspi"; 1076 assigned-clock-rates = <80000000>; 1077 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 1083 sdma1: dma-controller@30bd0000 { 1084 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1085 reg = <0x30bd0000 0x10000>; 1086 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1087 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1088 <&clk IMX8MP_CLK_AHB>; 1089 clock-names = "ipg", "ahb"; 1090 #dma-cells = <3>; 1091 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1092 }; 1093 1094 fec: ethernet@30be0000 { 1095 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1096 reg = <0x30be0000 0x10000>; 1097 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1101 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1102 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1103 <&clk IMX8MP_CLK_ENET_TIMER>, 1104 <&clk IMX8MP_CLK_ENET_REF>, 1105 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1106 clock-names = "ipg", "ahb", "ptp", 1107 "enet_clk_ref", "enet_out"; 1108 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1109 <&clk IMX8MP_CLK_ENET_TIMER>, 1110 <&clk IMX8MP_CLK_ENET_REF>, 1111 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1112 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1113 <&clk IMX8MP_SYS_PLL2_100M>, 1114 <&clk IMX8MP_SYS_PLL2_125M>, 1115 <&clk IMX8MP_SYS_PLL2_50M>; 1116 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1117 fsl,num-tx-queues = <3>; 1118 fsl,num-rx-queues = <3>; 1119 nvmem-cells = <ð_mac1>; 1120 nvmem-cell-names = "mac-address"; 1121 fsl,stop-mode = <&gpr 0x10 3>; 1122 status = "disabled"; 1123 }; 1124 1125 eqos: ethernet@30bf0000 { 1126 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1127 reg = <0x30bf0000 0x10000>; 1128 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1130 interrupt-names = "macirq", "eth_wake_irq"; 1131 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1132 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1133 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1134 <&clk IMX8MP_CLK_ENET_QOS>; 1135 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1136 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1137 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1138 <&clk IMX8MP_CLK_ENET_QOS>; 1139 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1140 <&clk IMX8MP_SYS_PLL2_100M>, 1141 <&clk IMX8MP_SYS_PLL2_125M>; 1142 assigned-clock-rates = <0>, <100000000>, <125000000>; 1143 nvmem-cells = <ð_mac2>; 1144 nvmem-cell-names = "mac-address"; 1145 intf_mode = <&gpr 0x4>; 1146 status = "disabled"; 1147 }; 1148 }; 1149 1150 noc: interconnect@32700000 { 1151 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1152 reg = <0x32700000 0x100000>; 1153 clocks = <&clk IMX8MP_CLK_NOC>; 1154 #interconnect-cells = <1>; 1155 operating-points-v2 = <&noc_opp_table>; 1156 1157 noc_opp_table: opp-table { 1158 compatible = "operating-points-v2"; 1159 1160 opp-200000000 { 1161 opp-hz = /bits/ 64 <200000000>; 1162 }; 1163 1164 opp-1000000000 { 1165 opp-hz = /bits/ 64 <1000000000>; 1166 }; 1167 }; 1168 }; 1169 1170 aips4: bus@32c00000 { 1171 compatible = "fsl,aips-bus", "simple-bus"; 1172 reg = <0x32c00000 0x400000>; 1173 #address-cells = <1>; 1174 #size-cells = <1>; 1175 ranges; 1176 1177 mipi_dsi: dsi@32e60000 { 1178 compatible = "fsl,imx8mp-mipi-dsim"; 1179 reg = <0x32e60000 0x400>; 1180 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1181 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1182 clock-names = "bus_clk", "sclk_mipi"; 1183 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, 1184 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1185 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1186 <&clk IMX8MP_CLK_24M>; 1187 assigned-clock-rates = <200000000>, <24000000>; 1188 samsung,pll-clock-frequency = <24000000>; 1189 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1190 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; 1191 status = "disabled"; 1192 1193 ports { 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 1197 port@0 { 1198 reg = <0>; 1199 1200 dsim_from_lcdif1: endpoint { 1201 remote-endpoint = <&lcdif1_to_dsim>; 1202 }; 1203 }; 1204 }; 1205 }; 1206 1207 lcdif1: display-controller@32e80000 { 1208 compatible = "fsl,imx8mp-lcdif"; 1209 reg = <0x32e80000 0x10000>; 1210 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1211 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1212 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1213 clock-names = "pix", "axi", "disp_axi"; 1214 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1215 <&clk IMX8MP_CLK_MEDIA_AXI>, 1216 <&clk IMX8MP_CLK_MEDIA_APB>; 1217 assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 1218 <&clk IMX8MP_SYS_PLL2_1000M>, 1219 <&clk IMX8MP_SYS_PLL1_800M>; 1220 assigned-clock-rates = <594000000>, <500000000>, <200000000>; 1221 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1222 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; 1223 status = "disabled"; 1224 1225 port { 1226 lcdif1_to_dsim: endpoint { 1227 remote-endpoint = <&dsim_from_lcdif1>; 1228 }; 1229 }; 1230 }; 1231 1232 lcdif2: display-controller@32e90000 { 1233 compatible = "fsl,imx8mp-lcdif"; 1234 reg = <0x32e90000 0x10000>; 1235 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1236 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1237 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1238 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1239 clock-names = "pix", "axi", "disp_axi"; 1240 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1241 <&clk IMX8MP_VIDEO_PLL1>; 1242 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, 1243 <&clk IMX8MP_VIDEO_PLL1_REF_SEL>; 1244 assigned-clock-rates = <0>, <1039500000>; 1245 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1246 status = "disabled"; 1247 1248 port { 1249 lcdif2_to_ldb: endpoint { 1250 remote-endpoint = <&ldb_from_lcdif2>; 1251 }; 1252 }; 1253 }; 1254 1255 media_blk_ctrl: blk-ctrl@32ec0000 { 1256 compatible = "fsl,imx8mp-media-blk-ctrl", 1257 "syscon"; 1258 reg = <0x32ec0000 0x10000>; 1259 #address-cells = <1>; 1260 #size-cells = <1>; 1261 power-domains = <&pgc_mediamix>, 1262 <&pgc_mipi_phy1>, 1263 <&pgc_mipi_phy1>, 1264 <&pgc_mediamix>, 1265 <&pgc_mediamix>, 1266 <&pgc_mipi_phy2>, 1267 <&pgc_mediamix>, 1268 <&pgc_ispdwp>, 1269 <&pgc_ispdwp>, 1270 <&pgc_mipi_phy2>; 1271 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1272 "lcdif1", "isi", "mipi-csi2", 1273 "lcdif2", "isp", "dwe", 1274 "mipi-dsi2"; 1275 interconnects = 1276 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1277 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1278 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1279 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1280 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1281 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1282 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1283 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1284 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1285 "isi1", "isi2", "isp0", "isp1", 1286 "dwe"; 1287 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1288 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1289 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1290 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1291 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1292 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1293 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1294 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1295 clock-names = "apb", "axi", "cam1", "cam2", 1296 "disp1", "disp2", "isp", "phy"; 1297 1298 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1299 <&clk IMX8MP_CLK_MEDIA_APB>; 1300 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1301 <&clk IMX8MP_SYS_PLL1_800M>; 1302 assigned-clock-rates = <500000000>, <200000000>; 1303 1304 #power-domain-cells = <1>; 1305 1306 lvds_bridge: bridge@5c { 1307 compatible = "fsl,imx8mp-ldb"; 1308 reg = <0x5c 0x4>, <0x128 0x4>; 1309 reg-names = "ldb", "lvds"; 1310 clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1311 clock-names = "ldb"; 1312 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1313 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1314 status = "disabled"; 1315 1316 ports { 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 1320 port@0 { 1321 reg = <0>; 1322 1323 ldb_from_lcdif2: endpoint { 1324 remote-endpoint = <&lcdif2_to_ldb>; 1325 }; 1326 }; 1327 1328 port@1 { 1329 reg = <1>; 1330 1331 ldb_lvds_ch0: endpoint { 1332 }; 1333 }; 1334 1335 port@2 { 1336 reg = <2>; 1337 1338 ldb_lvds_ch1: endpoint { 1339 }; 1340 }; 1341 }; 1342 }; 1343 }; 1344 1345 pcie_phy: pcie-phy@32f00000 { 1346 compatible = "fsl,imx8mp-pcie-phy"; 1347 reg = <0x32f00000 0x10000>; 1348 resets = <&src IMX8MP_RESET_PCIEPHY>, 1349 <&src IMX8MP_RESET_PCIEPHY_PERST>; 1350 reset-names = "pciephy", "perst"; 1351 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 1352 #phy-cells = <0>; 1353 status = "disabled"; 1354 }; 1355 1356 hsio_blk_ctrl: blk-ctrl@32f10000 { 1357 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 1358 reg = <0x32f10000 0x24>; 1359 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1360 <&clk IMX8MP_CLK_PCIE_ROOT>; 1361 clock-names = "usb", "pcie"; 1362 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 1363 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 1364 <&pgc_hsiomix>, <&pgc_pcie_phy>; 1365 power-domain-names = "bus", "usb", "usb-phy1", 1366 "usb-phy2", "pcie", "pcie-phy"; 1367 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 1368 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 1369 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 1370 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 1371 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 1372 #power-domain-cells = <1>; 1373 #clock-cells = <0>; 1374 }; 1375 }; 1376 1377 pcie: pcie@33800000 { 1378 compatible = "fsl,imx8mp-pcie"; 1379 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1380 reg-names = "dbi", "config"; 1381 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1382 <&clk IMX8MP_CLK_HSIO_AXI>, 1383 <&clk IMX8MP_CLK_PCIE_ROOT>; 1384 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1385 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 1386 assigned-clock-rates = <10000000>; 1387 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 1388 #address-cells = <3>; 1389 #size-cells = <2>; 1390 device_type = "pci"; 1391 bus-range = <0x00 0xff>; 1392 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1393 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1394 num-lanes = <1>; 1395 num-viewport = <4>; 1396 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1397 interrupt-names = "msi"; 1398 #interrupt-cells = <1>; 1399 interrupt-map-mask = <0 0 0 0x7>; 1400 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1401 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1402 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1403 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1404 fsl,max-link-speed = <3>; 1405 linux,pci-domain = <0>; 1406 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1407 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1408 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1409 reset-names = "apps", "turnoff"; 1410 phys = <&pcie_phy>; 1411 phy-names = "pcie-phy"; 1412 status = "disabled"; 1413 }; 1414 1415 pcie_ep: pcie-ep@33800000 { 1416 compatible = "fsl,imx8mp-pcie-ep"; 1417 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; 1418 reg-names = "dbi", "addr_space"; 1419 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1420 <&clk IMX8MP_CLK_HSIO_AXI>, 1421 <&clk IMX8MP_CLK_PCIE_ROOT>; 1422 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1423 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 1424 assigned-clock-rates = <10000000>; 1425 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 1426 num-lanes = <1>; 1427 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 1428 interrupt-names = "dma"; 1429 fsl,max-link-speed = <3>; 1430 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1431 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1432 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1433 reset-names = "apps", "turnoff"; 1434 phys = <&pcie_phy>; 1435 phy-names = "pcie-phy"; 1436 num-ib-windows = <4>; 1437 num-ob-windows = <4>; 1438 status = "disabled"; 1439 }; 1440 1441 gpu3d: gpu@38000000 { 1442 compatible = "vivante,gc"; 1443 reg = <0x38000000 0x8000>; 1444 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1445 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 1446 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 1447 <&clk IMX8MP_CLK_GPU_ROOT>, 1448 <&clk IMX8MP_CLK_GPU_AHB>; 1449 clock-names = "core", "shader", "bus", "reg"; 1450 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 1451 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 1452 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1453 <&clk IMX8MP_SYS_PLL1_800M>; 1454 assigned-clock-rates = <800000000>, <800000000>; 1455 power-domains = <&pgc_gpu3d>; 1456 }; 1457 1458 gpu2d: gpu@38008000 { 1459 compatible = "vivante,gc"; 1460 reg = <0x38008000 0x8000>; 1461 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1462 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 1463 <&clk IMX8MP_CLK_GPU_ROOT>, 1464 <&clk IMX8MP_CLK_GPU_AHB>; 1465 clock-names = "core", "bus", "reg"; 1466 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 1467 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1468 assigned-clock-rates = <800000000>; 1469 power-domains = <&pgc_gpu2d>; 1470 }; 1471 1472 vpu_g1: video-codec@38300000 { 1473 compatible = "nxp,imx8mm-vpu-g1"; 1474 reg = <0x38300000 0x10000>; 1475 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1476 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 1477 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 1478 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 1479 assigned-clock-rates = <600000000>; 1480 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 1481 }; 1482 1483 vpu_g2: video-codec@38310000 { 1484 compatible = "nxp,imx8mq-vpu-g2"; 1485 reg = <0x38310000 0x10000>; 1486 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1487 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 1488 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; 1489 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1490 assigned-clock-rates = <500000000>; 1491 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 1492 }; 1493 1494 vpumix_blk_ctrl: blk-ctrl@38330000 { 1495 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 1496 reg = <0x38330000 0x100>; 1497 #power-domain-cells = <1>; 1498 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1499 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 1500 power-domain-names = "bus", "g1", "g2", "vc8000e"; 1501 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 1502 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 1503 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 1504 clock-names = "g1", "g2", "vc8000e"; 1505 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; 1506 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 1507 assigned-clock-rates = <600000000>, <600000000>; 1508 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 1509 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 1510 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 1511 interconnect-names = "g1", "g2", "vc8000e"; 1512 }; 1513 1514 gic: interrupt-controller@38800000 { 1515 compatible = "arm,gic-v3"; 1516 reg = <0x38800000 0x10000>, 1517 <0x38880000 0xc0000>; 1518 #interrupt-cells = <3>; 1519 interrupt-controller; 1520 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1521 interrupt-parent = <&gic>; 1522 }; 1523 1524 edacmc: memory-controller@3d400000 { 1525 compatible = "snps,ddrc-3.80a"; 1526 reg = <0x3d400000 0x400000>; 1527 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1528 }; 1529 1530 ddr-pmu@3d800000 { 1531 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1532 reg = <0x3d800000 0x400000>; 1533 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1534 }; 1535 1536 usb3_phy0: usb-phy@381f0040 { 1537 compatible = "fsl,imx8mp-usb-phy"; 1538 reg = <0x381f0040 0x40>; 1539 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1540 clock-names = "phy"; 1541 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1542 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1543 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 1544 #phy-cells = <0>; 1545 status = "disabled"; 1546 }; 1547 1548 usb3_0: usb@32f10100 { 1549 compatible = "fsl,imx8mp-dwc3"; 1550 reg = <0x32f10100 0x8>, 1551 <0x381f0000 0x20>; 1552 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1553 <&clk IMX8MP_CLK_USB_SUSP>; 1554 clock-names = "hsio", "suspend"; 1555 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1556 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 1557 #address-cells = <1>; 1558 #size-cells = <1>; 1559 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 1560 ranges; 1561 status = "disabled"; 1562 1563 usb_dwc3_0: usb@38100000 { 1564 compatible = "snps,dwc3"; 1565 reg = <0x38100000 0x10000>; 1566 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1567 <&clk IMX8MP_CLK_USB_CORE_REF>, 1568 <&clk IMX8MP_CLK_USB_SUSP>; 1569 clock-names = "bus_early", "ref", "suspend"; 1570 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1571 phys = <&usb3_phy0>, <&usb3_phy0>; 1572 phy-names = "usb2-phy", "usb3-phy"; 1573 snps,gfladj-refclk-lpm-sel-quirk; 1574 }; 1575 1576 }; 1577 1578 usb3_phy1: usb-phy@382f0040 { 1579 compatible = "fsl,imx8mp-usb-phy"; 1580 reg = <0x382f0040 0x40>; 1581 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1582 clock-names = "phy"; 1583 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1584 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1585 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 1586 #phy-cells = <0>; 1587 status = "disabled"; 1588 }; 1589 1590 usb3_1: usb@32f10108 { 1591 compatible = "fsl,imx8mp-dwc3"; 1592 reg = <0x32f10108 0x8>, 1593 <0x382f0000 0x20>; 1594 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1595 <&clk IMX8MP_CLK_USB_SUSP>; 1596 clock-names = "hsio", "suspend"; 1597 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1598 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 1599 #address-cells = <1>; 1600 #size-cells = <1>; 1601 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 1602 ranges; 1603 status = "disabled"; 1604 1605 usb_dwc3_1: usb@38200000 { 1606 compatible = "snps,dwc3"; 1607 reg = <0x38200000 0x10000>; 1608 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1609 <&clk IMX8MP_CLK_USB_CORE_REF>, 1610 <&clk IMX8MP_CLK_USB_SUSP>; 1611 clock-names = "bus_early", "ref", "suspend"; 1612 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1613 phys = <&usb3_phy1>, <&usb3_phy1>; 1614 phy-names = "usb2-phy", "usb3-phy"; 1615 snps,gfladj-refclk-lpm-sel-quirk; 1616 }; 1617 }; 1618 1619 dsp: dsp@3b6e8000 { 1620 compatible = "fsl,imx8mp-dsp"; 1621 reg = <0x3b6e8000 0x88000>; 1622 mbox-names = "txdb0", "txdb1", 1623 "rxdb0", "rxdb1"; 1624 mboxes = <&mu2 2 0>, <&mu2 2 1>, 1625 <&mu2 3 0>, <&mu2 3 1>; 1626 memory-region = <&dsp_reserved>; 1627 status = "disabled"; 1628 }; 1629 }; 1630}; 1631