1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mp-clock.h>
7#include <dt-bindings/power/imx8mp-power.h>
8#include <dt-bindings/reset/imx8mp-reset.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/interconnect/fsl,imx8mp.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/thermal/thermal.h>
14
15#include "imx8mp-pinfunc.h"
16
17/ {
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		ethernet0 = &fec;
24		ethernet1 = &eqos;
25		gpio0 = &gpio1;
26		gpio1 = &gpio2;
27		gpio2 = &gpio3;
28		gpio3 = &gpio4;
29		gpio4 = &gpio5;
30		i2c0 = &i2c1;
31		i2c1 = &i2c2;
32		i2c2 = &i2c3;
33		i2c3 = &i2c4;
34		i2c4 = &i2c5;
35		i2c5 = &i2c6;
36		mmc0 = &usdhc1;
37		mmc1 = &usdhc2;
38		mmc2 = &usdhc3;
39		serial0 = &uart1;
40		serial1 = &uart2;
41		serial2 = &uart3;
42		serial3 = &uart4;
43		spi0 = &flexspi;
44	};
45
46	cpus {
47		#address-cells = <1>;
48		#size-cells = <0>;
49
50		A53_0: cpu@0 {
51			device_type = "cpu";
52			compatible = "arm,cortex-a53";
53			reg = <0x0>;
54			clock-latency = <61036>;
55			clocks = <&clk IMX8MP_CLK_ARM>;
56			enable-method = "psci";
57			i-cache-size = <0x8000>;
58			i-cache-line-size = <64>;
59			i-cache-sets = <256>;
60			d-cache-size = <0x8000>;
61			d-cache-line-size = <64>;
62			d-cache-sets = <128>;
63			next-level-cache = <&A53_L2>;
64			nvmem-cells = <&cpu_speed_grade>;
65			nvmem-cell-names = "speed_grade";
66			operating-points-v2 = <&a53_opp_table>;
67			#cooling-cells = <2>;
68		};
69
70		A53_1: cpu@1 {
71			device_type = "cpu";
72			compatible = "arm,cortex-a53";
73			reg = <0x1>;
74			clock-latency = <61036>;
75			clocks = <&clk IMX8MP_CLK_ARM>;
76			enable-method = "psci";
77			i-cache-size = <0x8000>;
78			i-cache-line-size = <64>;
79			i-cache-sets = <256>;
80			d-cache-size = <0x8000>;
81			d-cache-line-size = <64>;
82			d-cache-sets = <128>;
83			next-level-cache = <&A53_L2>;
84			operating-points-v2 = <&a53_opp_table>;
85			#cooling-cells = <2>;
86		};
87
88		A53_2: cpu@2 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a53";
91			reg = <0x2>;
92			clock-latency = <61036>;
93			clocks = <&clk IMX8MP_CLK_ARM>;
94			enable-method = "psci";
95			i-cache-size = <0x8000>;
96			i-cache-line-size = <64>;
97			i-cache-sets = <256>;
98			d-cache-size = <0x8000>;
99			d-cache-line-size = <64>;
100			d-cache-sets = <128>;
101			next-level-cache = <&A53_L2>;
102			operating-points-v2 = <&a53_opp_table>;
103			#cooling-cells = <2>;
104		};
105
106		A53_3: cpu@3 {
107			device_type = "cpu";
108			compatible = "arm,cortex-a53";
109			reg = <0x3>;
110			clock-latency = <61036>;
111			clocks = <&clk IMX8MP_CLK_ARM>;
112			enable-method = "psci";
113			i-cache-size = <0x8000>;
114			i-cache-line-size = <64>;
115			i-cache-sets = <256>;
116			d-cache-size = <0x8000>;
117			d-cache-line-size = <64>;
118			d-cache-sets = <128>;
119			next-level-cache = <&A53_L2>;
120			operating-points-v2 = <&a53_opp_table>;
121			#cooling-cells = <2>;
122		};
123
124		A53_L2: l2-cache0 {
125			compatible = "cache";
126			cache-level = <2>;
127			cache-size = <0x80000>;
128			cache-line-size = <64>;
129			cache-sets = <512>;
130		};
131	};
132
133	a53_opp_table: opp-table {
134		compatible = "operating-points-v2";
135		opp-shared;
136
137		opp-1200000000 {
138			opp-hz = /bits/ 64 <1200000000>;
139			opp-microvolt = <850000>;
140			opp-supported-hw = <0x8a0>, <0x7>;
141			clock-latency-ns = <150000>;
142			opp-suspend;
143		};
144
145		opp-1600000000 {
146			opp-hz = /bits/ 64 <1600000000>;
147			opp-microvolt = <950000>;
148			opp-supported-hw = <0xa0>, <0x7>;
149			clock-latency-ns = <150000>;
150			opp-suspend;
151		};
152
153		opp-1800000000 {
154			opp-hz = /bits/ 64 <1800000000>;
155			opp-microvolt = <1000000>;
156			opp-supported-hw = <0x20>, <0x3>;
157			clock-latency-ns = <150000>;
158			opp-suspend;
159		};
160	};
161
162	osc_32k: clock-osc-32k {
163		compatible = "fixed-clock";
164		#clock-cells = <0>;
165		clock-frequency = <32768>;
166		clock-output-names = "osc_32k";
167	};
168
169	osc_24m: clock-osc-24m {
170		compatible = "fixed-clock";
171		#clock-cells = <0>;
172		clock-frequency = <24000000>;
173		clock-output-names = "osc_24m";
174	};
175
176	clk_ext1: clock-ext1 {
177		compatible = "fixed-clock";
178		#clock-cells = <0>;
179		clock-frequency = <133000000>;
180		clock-output-names = "clk_ext1";
181	};
182
183	clk_ext2: clock-ext2 {
184		compatible = "fixed-clock";
185		#clock-cells = <0>;
186		clock-frequency = <133000000>;
187		clock-output-names = "clk_ext2";
188	};
189
190	clk_ext3: clock-ext3 {
191		compatible = "fixed-clock";
192		#clock-cells = <0>;
193		clock-frequency = <133000000>;
194		clock-output-names = "clk_ext3";
195	};
196
197	clk_ext4: clock-ext4 {
198		compatible = "fixed-clock";
199		#clock-cells = <0>;
200		clock-frequency = <133000000>;
201		clock-output-names = "clk_ext4";
202	};
203
204	reserved-memory {
205		#address-cells = <2>;
206		#size-cells = <2>;
207		ranges;
208
209		dsp_reserved: dsp@92400000 {
210			reg = <0 0x92400000 0 0x2000000>;
211			no-map;
212		};
213	};
214
215	pmu {
216		compatible = "arm,cortex-a53-pmu";
217		interrupts = <GIC_PPI 7
218			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
219	};
220
221	psci {
222		compatible = "arm,psci-1.0";
223		method = "smc";
224	};
225
226	thermal-zones {
227		cpu-thermal {
228			polling-delay-passive = <250>;
229			polling-delay = <2000>;
230			thermal-sensors = <&tmu 0>;
231			trips {
232				cpu_alert0: trip0 {
233					temperature = <85000>;
234					hysteresis = <2000>;
235					type = "passive";
236				};
237
238				cpu_crit0: trip1 {
239					temperature = <95000>;
240					hysteresis = <2000>;
241					type = "critical";
242				};
243			};
244
245			cooling-maps {
246				map0 {
247					trip = <&cpu_alert0>;
248					cooling-device =
249						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
250						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
251						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
253				};
254			};
255		};
256
257		soc-thermal {
258			polling-delay-passive = <250>;
259			polling-delay = <2000>;
260			thermal-sensors = <&tmu 1>;
261			trips {
262				soc_alert0: trip0 {
263					temperature = <85000>;
264					hysteresis = <2000>;
265					type = "passive";
266				};
267
268				soc_crit0: trip1 {
269					temperature = <95000>;
270					hysteresis = <2000>;
271					type = "critical";
272				};
273			};
274
275			cooling-maps {
276				map0 {
277					trip = <&soc_alert0>;
278					cooling-device =
279						<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
280						<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
281						<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
282						<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
283				};
284			};
285		};
286	};
287
288	timer {
289		compatible = "arm,armv8-timer";
290		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
291			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
292			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
293			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
294		clock-frequency = <8000000>;
295		arm,no-tick-in-suspend;
296	};
297
298	soc: soc@0 {
299		compatible = "fsl,imx8mp-soc", "simple-bus";
300		#address-cells = <1>;
301		#size-cells = <1>;
302		ranges = <0x0 0x0 0x0 0x3e000000>;
303		nvmem-cells = <&imx8mp_uid>;
304		nvmem-cell-names = "soc_unique_id";
305
306		aips1: bus@30000000 {
307			compatible = "fsl,aips-bus", "simple-bus";
308			reg = <0x30000000 0x400000>;
309			#address-cells = <1>;
310			#size-cells = <1>;
311			ranges;
312
313			gpio1: gpio@30200000 {
314				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
315				reg = <0x30200000 0x10000>;
316				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
317					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
318				clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
319				gpio-controller;
320				#gpio-cells = <2>;
321				interrupt-controller;
322				#interrupt-cells = <2>;
323				gpio-ranges = <&iomuxc 0 5 30>;
324			};
325
326			gpio2: gpio@30210000 {
327				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
328				reg = <0x30210000 0x10000>;
329				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
330					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
331				clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
332				gpio-controller;
333				#gpio-cells = <2>;
334				interrupt-controller;
335				#interrupt-cells = <2>;
336				gpio-ranges = <&iomuxc 0 35 21>;
337			};
338
339			gpio3: gpio@30220000 {
340				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
341				reg = <0x30220000 0x10000>;
342				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
343					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
344				clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
345				gpio-controller;
346				#gpio-cells = <2>;
347				interrupt-controller;
348				#interrupt-cells = <2>;
349				gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
350			};
351
352			gpio4: gpio@30230000 {
353				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
354				reg = <0x30230000 0x10000>;
355				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
356					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
357				clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
358				gpio-controller;
359				#gpio-cells = <2>;
360				interrupt-controller;
361				#interrupt-cells = <2>;
362				gpio-ranges = <&iomuxc 0 82 32>;
363			};
364
365			gpio5: gpio@30240000 {
366				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
367				reg = <0x30240000 0x10000>;
368				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
369					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
370				clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
371				gpio-controller;
372				#gpio-cells = <2>;
373				interrupt-controller;
374				#interrupt-cells = <2>;
375				gpio-ranges = <&iomuxc 0 114 30>;
376			};
377
378			tmu: tmu@30260000 {
379				compatible = "fsl,imx8mp-tmu";
380				reg = <0x30260000 0x10000>;
381				clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
382				#thermal-sensor-cells = <1>;
383			};
384
385			wdog1: watchdog@30280000 {
386				compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
387				reg = <0x30280000 0x10000>;
388				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
389				clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
390				status = "disabled";
391			};
392
393			wdog2: watchdog@30290000 {
394				compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
395				reg = <0x30290000 0x10000>;
396				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
397				clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
398				status = "disabled";
399			};
400
401			wdog3: watchdog@302a0000 {
402				compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
403				reg = <0x302a0000 0x10000>;
404				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
405				clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
406				status = "disabled";
407			};
408
409			iomuxc: pinctrl@30330000 {
410				compatible = "fsl,imx8mp-iomuxc";
411				reg = <0x30330000 0x10000>;
412			};
413
414			gpr: iomuxc-gpr@30340000 {
415				compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
416				reg = <0x30340000 0x10000>;
417			};
418
419			ocotp: efuse@30350000 {
420				compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
421				reg = <0x30350000 0x10000>;
422				clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
423				/* For nvmem subnodes */
424				#address-cells = <1>;
425				#size-cells = <1>;
426
427				imx8mp_uid: unique-id@420 {
428					reg = <0x8 0x8>;
429				};
430
431				cpu_speed_grade: speed-grade@10 {
432					reg = <0x10 4>;
433				};
434
435				eth_mac1: mac-address@90 {
436					reg = <0x90 6>;
437				};
438
439				eth_mac2: mac-address@96 {
440					reg = <0x96 6>;
441				};
442			};
443
444			anatop: anatop@30360000 {
445				compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
446					     "syscon";
447				reg = <0x30360000 0x10000>;
448			};
449
450			snvs: snvs@30370000 {
451				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
452				reg = <0x30370000 0x10000>;
453
454				snvs_rtc: snvs-rtc-lp {
455					compatible = "fsl,sec-v4.0-mon-rtc-lp";
456					regmap =<&snvs>;
457					offset = <0x34>;
458					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
459						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
460					clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
461					clock-names = "snvs-rtc";
462				};
463
464				snvs_pwrkey: snvs-powerkey {
465					compatible = "fsl,sec-v4.0-pwrkey";
466					regmap = <&snvs>;
467					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
468					clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
469					clock-names = "snvs-pwrkey";
470					linux,keycode = <KEY_POWER>;
471					wakeup-source;
472					status = "disabled";
473				};
474
475				snvs_lpgpr: snvs-lpgpr {
476					compatible = "fsl,imx8mp-snvs-lpgpr",
477						     "fsl,imx7d-snvs-lpgpr";
478				};
479			};
480
481			clk: clock-controller@30380000 {
482				compatible = "fsl,imx8mp-ccm";
483				reg = <0x30380000 0x10000>;
484				#clock-cells = <1>;
485				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
486					 <&clk_ext3>, <&clk_ext4>;
487				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
488					      "clk_ext3", "clk_ext4";
489				assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
490						  <&clk IMX8MP_CLK_A53_CORE>,
491						  <&clk IMX8MP_CLK_NOC>,
492						  <&clk IMX8MP_CLK_NOC_IO>,
493						  <&clk IMX8MP_CLK_GIC>,
494						  <&clk IMX8MP_CLK_AUDIO_AHB>,
495						  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
496						  <&clk IMX8MP_AUDIO_PLL1>,
497						  <&clk IMX8MP_AUDIO_PLL2>;
498				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
499							 <&clk IMX8MP_ARM_PLL_OUT>,
500							 <&clk IMX8MP_SYS_PLL2_1000M>,
501							 <&clk IMX8MP_SYS_PLL1_800M>,
502							 <&clk IMX8MP_SYS_PLL2_500M>,
503							 <&clk IMX8MP_SYS_PLL1_800M>,
504							 <&clk IMX8MP_SYS_PLL1_800M>;
505				assigned-clock-rates = <0>, <0>,
506						       <1000000000>,
507						       <800000000>,
508						       <500000000>,
509						       <400000000>,
510						       <800000000>,
511						       <393216000>,
512						       <361267200>;
513			};
514
515			src: reset-controller@30390000 {
516				compatible = "fsl,imx8mp-src", "syscon";
517				reg = <0x30390000 0x10000>;
518				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
519				#reset-cells = <1>;
520			};
521
522			gpc: gpc@303a0000 {
523				compatible = "fsl,imx8mp-gpc";
524				reg = <0x303a0000 0x1000>;
525				interrupt-parent = <&gic>;
526				interrupt-controller;
527				#interrupt-cells = <3>;
528
529				pgc {
530					#address-cells = <1>;
531					#size-cells = <0>;
532
533					pgc_mipi_phy1: power-domain@0 {
534						#power-domain-cells = <0>;
535						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
536					};
537
538					pgc_pcie_phy: power-domain@1 {
539						#power-domain-cells = <0>;
540						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
541					};
542
543					pgc_usb1_phy: power-domain@2 {
544						#power-domain-cells = <0>;
545						reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
546					};
547
548					pgc_usb2_phy: power-domain@3 {
549						#power-domain-cells = <0>;
550						reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
551					};
552
553					pgc_gpu2d: power-domain@6 {
554						#power-domain-cells = <0>;
555						reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
556						clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
557						power-domains = <&pgc_gpumix>;
558					};
559
560					pgc_gpumix: power-domain@7 {
561						#power-domain-cells = <0>;
562						reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
563						clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
564							 <&clk IMX8MP_CLK_GPU_AHB>;
565						assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
566								  <&clk IMX8MP_CLK_GPU_AHB>;
567						assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
568									 <&clk IMX8MP_SYS_PLL1_800M>;
569						assigned-clock-rates = <800000000>, <400000000>;
570					};
571
572					pgc_gpu3d: power-domain@9 {
573						#power-domain-cells = <0>;
574						reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
575						clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
576							 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
577						power-domains = <&pgc_gpumix>;
578					};
579
580					pgc_mediamix: power-domain@10 {
581						#power-domain-cells = <0>;
582						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
583						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
584							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
585					};
586
587					pgc_mipi_phy2: power-domain@16 {
588						#power-domain-cells = <0>;
589						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
590					};
591
592					pgc_hsiomix: power-domains@17 {
593						#power-domain-cells = <0>;
594						reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
595						clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
596							 <&clk IMX8MP_CLK_HSIO_ROOT>;
597						assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
598						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
599						assigned-clock-rates = <500000000>;
600					};
601
602					pgc_ispdwp: power-domain@18 {
603						#power-domain-cells = <0>;
604						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
605						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
606					};
607
608					pgc_vpumix: power-domain@19 {
609						#power-domain-cells = <0>;
610						reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
611						clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
612					};
613
614					pgc_vpu_g1: power-domain@20 {
615						#power-domain-cells = <0>;
616						power-domains = <&pgc_vpumix>;
617						reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
618						clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
619					};
620
621					pgc_vpu_g2: power-domain@21 {
622						#power-domain-cells = <0>;
623						power-domains = <&pgc_vpumix>;
624						reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
625						clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
626					};
627
628					pgc_vpu_vc8000e: power-domain@22 {
629						#power-domain-cells = <0>;
630						power-domains = <&pgc_vpumix>;
631						reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
632						clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
633					};
634				};
635			};
636		};
637
638		aips2: bus@30400000 {
639			compatible = "fsl,aips-bus", "simple-bus";
640			reg = <0x30400000 0x400000>;
641			#address-cells = <1>;
642			#size-cells = <1>;
643			ranges;
644
645			pwm1: pwm@30660000 {
646				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
647				reg = <0x30660000 0x10000>;
648				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
649				clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
650					 <&clk IMX8MP_CLK_PWM1_ROOT>;
651				clock-names = "ipg", "per";
652				#pwm-cells = <3>;
653				status = "disabled";
654			};
655
656			pwm2: pwm@30670000 {
657				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
658				reg = <0x30670000 0x10000>;
659				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
660				clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
661					 <&clk IMX8MP_CLK_PWM2_ROOT>;
662				clock-names = "ipg", "per";
663				#pwm-cells = <3>;
664				status = "disabled";
665			};
666
667			pwm3: pwm@30680000 {
668				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
669				reg = <0x30680000 0x10000>;
670				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
671				clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
672					 <&clk IMX8MP_CLK_PWM3_ROOT>;
673				clock-names = "ipg", "per";
674				#pwm-cells = <3>;
675				status = "disabled";
676			};
677
678			pwm4: pwm@30690000 {
679				compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
680				reg = <0x30690000 0x10000>;
681				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
682				clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
683					 <&clk IMX8MP_CLK_PWM4_ROOT>;
684				clock-names = "ipg", "per";
685				#pwm-cells = <3>;
686				status = "disabled";
687			};
688
689			system_counter: timer@306a0000 {
690				compatible = "nxp,sysctr-timer";
691				reg = <0x306a0000 0x20000>;
692				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
693				clocks = <&osc_24m>;
694				clock-names = "per";
695			};
696		};
697
698		aips3: bus@30800000 {
699			compatible = "fsl,aips-bus", "simple-bus";
700			reg = <0x30800000 0x400000>;
701			#address-cells = <1>;
702			#size-cells = <1>;
703			ranges;
704
705			ecspi1: spi@30820000 {
706				#address-cells = <1>;
707				#size-cells = <0>;
708				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
709				reg = <0x30820000 0x10000>;
710				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
711				clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
712					 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
713				clock-names = "ipg", "per";
714				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
715				dma-names = "rx", "tx";
716				status = "disabled";
717			};
718
719			ecspi2: spi@30830000 {
720				#address-cells = <1>;
721				#size-cells = <0>;
722				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
723				reg = <0x30830000 0x10000>;
724				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
725				clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
726					 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
727				clock-names = "ipg", "per";
728				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
729				dma-names = "rx", "tx";
730				status = "disabled";
731			};
732
733			ecspi3: spi@30840000 {
734				#address-cells = <1>;
735				#size-cells = <0>;
736				compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
737				reg = <0x30840000 0x10000>;
738				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
739				clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
740					 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
741				clock-names = "ipg", "per";
742				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
743				dma-names = "rx", "tx";
744				status = "disabled";
745			};
746
747			uart1: serial@30860000 {
748				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
749				reg = <0x30860000 0x10000>;
750				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
751				clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
752					 <&clk IMX8MP_CLK_UART1_ROOT>;
753				clock-names = "ipg", "per";
754				dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
755				dma-names = "rx", "tx";
756				status = "disabled";
757			};
758
759			uart3: serial@30880000 {
760				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
761				reg = <0x30880000 0x10000>;
762				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
763				clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
764					 <&clk IMX8MP_CLK_UART3_ROOT>;
765				clock-names = "ipg", "per";
766				dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
767				dma-names = "rx", "tx";
768				status = "disabled";
769			};
770
771			uart2: serial@30890000 {
772				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
773				reg = <0x30890000 0x10000>;
774				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
775				clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
776					 <&clk IMX8MP_CLK_UART2_ROOT>;
777				clock-names = "ipg", "per";
778				dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
779				dma-names = "rx", "tx";
780				status = "disabled";
781			};
782
783			flexcan1: can@308c0000 {
784				compatible = "fsl,imx8mp-flexcan";
785				reg = <0x308c0000 0x10000>;
786				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
787				clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
788					 <&clk IMX8MP_CLK_CAN1_ROOT>;
789				clock-names = "ipg", "per";
790				assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
791				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
792				assigned-clock-rates = <40000000>;
793				fsl,clk-source = /bits/ 8 <0>;
794				fsl,stop-mode = <&gpr 0x10 4>;
795				status = "disabled";
796			};
797
798			flexcan2: can@308d0000 {
799				compatible = "fsl,imx8mp-flexcan";
800				reg = <0x308d0000 0x10000>;
801				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
802				clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
803					 <&clk IMX8MP_CLK_CAN2_ROOT>;
804				clock-names = "ipg", "per";
805				assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
806				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
807				assigned-clock-rates = <40000000>;
808				fsl,clk-source = /bits/ 8 <0>;
809				fsl,stop-mode = <&gpr 0x10 5>;
810				status = "disabled";
811			};
812
813			crypto: crypto@30900000 {
814				compatible = "fsl,sec-v4.0";
815				#address-cells = <1>;
816				#size-cells = <1>;
817				reg = <0x30900000 0x40000>;
818				ranges = <0 0x30900000 0x40000>;
819				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
820				clocks = <&clk IMX8MP_CLK_AHB>,
821					 <&clk IMX8MP_CLK_IPG_ROOT>;
822				clock-names = "aclk", "ipg";
823
824				sec_jr0: jr@1000 {
825					compatible = "fsl,sec-v4.0-job-ring";
826					reg = <0x1000 0x1000>;
827					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
828					status = "disabled";
829				};
830
831				sec_jr1: jr@2000 {
832					compatible = "fsl,sec-v4.0-job-ring";
833					reg = <0x2000 0x1000>;
834					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
835				};
836
837				sec_jr2: jr@3000 {
838					compatible = "fsl,sec-v4.0-job-ring";
839					reg = <0x3000 0x1000>;
840					interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
841				};
842			};
843
844			i2c1: i2c@30a20000 {
845				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
846				#address-cells = <1>;
847				#size-cells = <0>;
848				reg = <0x30a20000 0x10000>;
849				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
850				clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
851				status = "disabled";
852			};
853
854			i2c2: i2c@30a30000 {
855				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
856				#address-cells = <1>;
857				#size-cells = <0>;
858				reg = <0x30a30000 0x10000>;
859				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
860				clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
861				status = "disabled";
862			};
863
864			i2c3: i2c@30a40000 {
865				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
866				#address-cells = <1>;
867				#size-cells = <0>;
868				reg = <0x30a40000 0x10000>;
869				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
870				clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
871				status = "disabled";
872			};
873
874			i2c4: i2c@30a50000 {
875				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
876				#address-cells = <1>;
877				#size-cells = <0>;
878				reg = <0x30a50000 0x10000>;
879				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
880				clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
881				status = "disabled";
882			};
883
884			uart4: serial@30a60000 {
885				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
886				reg = <0x30a60000 0x10000>;
887				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
888				clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
889					 <&clk IMX8MP_CLK_UART4_ROOT>;
890				clock-names = "ipg", "per";
891				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
892				dma-names = "rx", "tx";
893				status = "disabled";
894			};
895
896			mu: mailbox@30aa0000 {
897				compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
898				reg = <0x30aa0000 0x10000>;
899				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
900				clocks = <&clk IMX8MP_CLK_MU_ROOT>;
901				#mbox-cells = <2>;
902			};
903
904			mu2: mailbox@30e60000 {
905				compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
906				reg = <0x30e60000 0x10000>;
907				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
908				#mbox-cells = <2>;
909				status = "disabled";
910			};
911
912			i2c5: i2c@30ad0000 {
913				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
914				#address-cells = <1>;
915				#size-cells = <0>;
916				reg = <0x30ad0000 0x10000>;
917				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
918				clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
919				status = "disabled";
920			};
921
922			i2c6: i2c@30ae0000 {
923				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
924				#address-cells = <1>;
925				#size-cells = <0>;
926				reg = <0x30ae0000 0x10000>;
927				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
928				clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
929				status = "disabled";
930			};
931
932			usdhc1: mmc@30b40000 {
933				compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
934				reg = <0x30b40000 0x10000>;
935				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
936				clocks = <&clk IMX8MP_CLK_DUMMY>,
937					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
938					 <&clk IMX8MP_CLK_USDHC1_ROOT>;
939				clock-names = "ipg", "ahb", "per";
940				fsl,tuning-start-tap = <20>;
941				fsl,tuning-step = <2>;
942				bus-width = <4>;
943				status = "disabled";
944			};
945
946			usdhc2: mmc@30b50000 {
947				compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
948				reg = <0x30b50000 0x10000>;
949				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
950				clocks = <&clk IMX8MP_CLK_DUMMY>,
951					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
952					 <&clk IMX8MP_CLK_USDHC2_ROOT>;
953				clock-names = "ipg", "ahb", "per";
954				fsl,tuning-start-tap = <20>;
955				fsl,tuning-step = <2>;
956				bus-width = <4>;
957				status = "disabled";
958			};
959
960			usdhc3: mmc@30b60000 {
961				compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
962				reg = <0x30b60000 0x10000>;
963				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
964				clocks = <&clk IMX8MP_CLK_DUMMY>,
965					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
966					 <&clk IMX8MP_CLK_USDHC3_ROOT>;
967				clock-names = "ipg", "ahb", "per";
968				fsl,tuning-start-tap = <20>;
969				fsl,tuning-step = <2>;
970				bus-width = <4>;
971				status = "disabled";
972			};
973
974			flexspi: spi@30bb0000 {
975				compatible = "nxp,imx8mp-fspi";
976				reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
977				reg-names = "fspi_base", "fspi_mmap";
978				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
979				clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
980					 <&clk IMX8MP_CLK_QSPI_ROOT>;
981				clock-names = "fspi_en", "fspi";
982				assigned-clock-rates = <80000000>;
983				assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
984				#address-cells = <1>;
985				#size-cells = <0>;
986				status = "disabled";
987			};
988
989			sdma1: dma-controller@30bd0000 {
990				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
991				reg = <0x30bd0000 0x10000>;
992				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
993				clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
994					 <&clk IMX8MP_CLK_AHB>;
995				clock-names = "ipg", "ahb";
996				#dma-cells = <3>;
997				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
998			};
999
1000			fec: ethernet@30be0000 {
1001				compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1002				reg = <0x30be0000 0x10000>;
1003				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1004					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1005					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1006					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1007				clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1008					 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1009					 <&clk IMX8MP_CLK_ENET_TIMER>,
1010					 <&clk IMX8MP_CLK_ENET_REF>,
1011					 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1012				clock-names = "ipg", "ahb", "ptp",
1013					      "enet_clk_ref", "enet_out";
1014				assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1015						  <&clk IMX8MP_CLK_ENET_TIMER>,
1016						  <&clk IMX8MP_CLK_ENET_REF>,
1017						  <&clk IMX8MP_CLK_ENET_PHY_REF>;
1018				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1019							 <&clk IMX8MP_SYS_PLL2_100M>,
1020							 <&clk IMX8MP_SYS_PLL2_125M>,
1021							 <&clk IMX8MP_SYS_PLL2_50M>;
1022				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1023				fsl,num-tx-queues = <3>;
1024				fsl,num-rx-queues = <3>;
1025				nvmem-cells = <&eth_mac1>;
1026				nvmem-cell-names = "mac-address";
1027				fsl,stop-mode = <&gpr 0x10 3>;
1028				status = "disabled";
1029			};
1030
1031			eqos: ethernet@30bf0000 {
1032				compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1033				reg = <0x30bf0000 0x10000>;
1034				interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1035					     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1036				interrupt-names = "macirq", "eth_wake_irq";
1037				clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1038					 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1039					 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1040					 <&clk IMX8MP_CLK_ENET_QOS>;
1041				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1042				assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1043						  <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1044						  <&clk IMX8MP_CLK_ENET_QOS>;
1045				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1046							 <&clk IMX8MP_SYS_PLL2_100M>,
1047							 <&clk IMX8MP_SYS_PLL2_125M>;
1048				assigned-clock-rates = <0>, <100000000>, <125000000>;
1049				nvmem-cells = <&eth_mac2>;
1050				nvmem-cell-names = "mac-address";
1051				intf_mode = <&gpr 0x4>;
1052				status = "disabled";
1053			};
1054		};
1055
1056		noc: interconnect@32700000 {
1057			compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1058			reg = <0x32700000 0x100000>;
1059			clocks = <&clk IMX8MP_CLK_NOC>;
1060			#interconnect-cells = <1>;
1061			operating-points-v2 = <&noc_opp_table>;
1062
1063			noc_opp_table: opp-table {
1064				compatible = "operating-points-v2";
1065
1066				opp-200M {
1067					opp-hz = /bits/ 64 <200000000>;
1068				};
1069
1070				opp-1000M {
1071					opp-hz = /bits/ 64 <1000000000>;
1072				};
1073			};
1074		};
1075
1076		aips4: bus@32c00000 {
1077			compatible = "fsl,aips-bus", "simple-bus";
1078			reg = <0x32c00000 0x400000>;
1079			#address-cells = <1>;
1080			#size-cells = <1>;
1081			ranges;
1082
1083			media_blk_ctrl: blk-ctrl@32ec0000 {
1084				compatible = "fsl,imx8mp-media-blk-ctrl",
1085					     "syscon";
1086				reg = <0x32ec0000 0x10000>;
1087				power-domains = <&pgc_mediamix>,
1088						<&pgc_mipi_phy1>,
1089						<&pgc_mipi_phy1>,
1090						<&pgc_mediamix>,
1091						<&pgc_mediamix>,
1092						<&pgc_mipi_phy2>,
1093						<&pgc_mediamix>,
1094						<&pgc_ispdwp>,
1095						<&pgc_ispdwp>,
1096						<&pgc_mipi_phy2>;
1097				power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1098						     "lcdif1", "isi", "mipi-csi2",
1099						     "lcdif2", "isp", "dwe",
1100						     "mipi-dsi2";
1101				interconnects =
1102					<&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
1103					<&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
1104					<&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
1105					<&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
1106					<&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
1107					<&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
1108					<&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
1109					<&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
1110				interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1111						     "isi1", "isi2", "isp0", "isp1",
1112						     "dwe";
1113				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1114					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1115					 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1116					 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1117					 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1118					 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1119					 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1120					 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1121				clock-names = "apb", "axi", "cam1", "cam2",
1122					      "disp1", "disp2", "isp", "phy";
1123
1124				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1125						  <&clk IMX8MP_CLK_MEDIA_APB>;
1126				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1127							 <&clk IMX8MP_SYS_PLL1_800M>;
1128				assigned-clock-rates = <500000000>, <200000000>;
1129
1130				#power-domain-cells = <1>;
1131			};
1132
1133			pcie_phy: pcie-phy@32f00000 {
1134				compatible = "fsl,imx8mp-pcie-phy";
1135				reg = <0x32f00000 0x10000>;
1136				resets = <&src IMX8MP_RESET_PCIEPHY>,
1137					 <&src IMX8MP_RESET_PCIEPHY_PERST>;
1138				reset-names = "pciephy", "perst";
1139				power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1140				#phy-cells = <0>;
1141				status = "disabled";
1142			};
1143
1144			hsio_blk_ctrl: blk-ctrl@32f10000 {
1145				compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1146				reg = <0x32f10000 0x24>;
1147				clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1148					 <&clk IMX8MP_CLK_PCIE_ROOT>;
1149				clock-names = "usb", "pcie";
1150				power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1151						<&pgc_usb1_phy>, <&pgc_usb2_phy>,
1152						<&pgc_hsiomix>, <&pgc_pcie_phy>;
1153				power-domain-names = "bus", "usb", "usb-phy1",
1154						     "usb-phy2", "pcie", "pcie-phy";
1155				interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
1156						<&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
1157						<&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
1158						<&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
1159				interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
1160				#power-domain-cells = <1>;
1161			};
1162		};
1163
1164		pcie: pcie@33800000 {
1165			compatible = "fsl,imx8mp-pcie";
1166			reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1167			reg-names = "dbi", "config";
1168			#address-cells = <3>;
1169			#size-cells = <2>;
1170			device_type = "pci";
1171			bus-range = <0x00 0xff>;
1172			ranges =  <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1173				  <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1174			num-lanes = <1>;
1175			num-viewport = <4>;
1176			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1177			interrupt-names = "msi";
1178			#interrupt-cells = <1>;
1179			interrupt-map-mask = <0 0 0 0x7>;
1180			interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1181					<0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1182					<0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1183					<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1184			fsl,max-link-speed = <3>;
1185			linux,pci-domain = <0>;
1186			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1187			resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
1188				 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
1189			reset-names = "apps", "turnoff";
1190			phys = <&pcie_phy>;
1191			phy-names = "pcie-phy";
1192			status = "disabled";
1193		};
1194
1195		gpu3d: gpu@38000000 {
1196			compatible = "vivante,gc";
1197			reg = <0x38000000 0x8000>;
1198			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1199			clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1200				 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1201				 <&clk IMX8MP_CLK_GPU_ROOT>,
1202				 <&clk IMX8MP_CLK_GPU_AHB>;
1203			clock-names = "core", "shader", "bus", "reg";
1204			assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1205					  <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1206			assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1207						 <&clk IMX8MP_SYS_PLL1_800M>;
1208			assigned-clock-rates = <800000000>, <800000000>;
1209			power-domains = <&pgc_gpu3d>;
1210		};
1211
1212		gpu2d: gpu@38008000 {
1213			compatible = "vivante,gc";
1214			reg = <0x38008000 0x8000>;
1215			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1216			clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1217				 <&clk IMX8MP_CLK_GPU_ROOT>,
1218				 <&clk IMX8MP_CLK_GPU_AHB>;
1219			clock-names = "core", "bus", "reg";
1220			assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1221			assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1222			assigned-clock-rates = <800000000>;
1223			power-domains = <&pgc_gpu2d>;
1224		};
1225
1226		vpumix_blk_ctrl: blk-ctrl@38330000 {
1227			compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
1228			reg = <0x38330000 0x100>;
1229			#power-domain-cells = <1>;
1230			power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1231					<&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
1232			power-domain-names = "bus", "g1", "g2", "vc8000e";
1233			clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
1234				 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
1235				 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
1236			clock-names = "g1", "g2", "vc8000e";
1237			interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
1238					<&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
1239					<&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
1240			interconnect-names = "g1", "g2", "vc8000e";
1241		};
1242
1243		gic: interrupt-controller@38800000 {
1244			compatible = "arm,gic-v3";
1245			reg = <0x38800000 0x10000>,
1246			      <0x38880000 0xc0000>;
1247			#interrupt-cells = <3>;
1248			interrupt-controller;
1249			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1250			interrupt-parent = <&gic>;
1251		};
1252
1253		edacmc: memory-controller@3d400000 {
1254			compatible = "snps,ddrc-3.80a";
1255			reg = <0x3d400000 0x400000>;
1256			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1257		};
1258
1259		ddr-pmu@3d800000 {
1260			compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1261			reg = <0x3d800000 0x400000>;
1262			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1263		};
1264
1265		usb3_phy0: usb-phy@381f0040 {
1266			compatible = "fsl,imx8mp-usb-phy";
1267			reg = <0x381f0040 0x40>;
1268			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1269			clock-names = "phy";
1270			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1271			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1272			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
1273			#phy-cells = <0>;
1274			status = "disabled";
1275		};
1276
1277		usb3_0: usb@32f10100 {
1278			compatible = "fsl,imx8mp-dwc3";
1279			reg = <0x32f10100 0x8>,
1280			      <0x381f0000 0x20>;
1281			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1282				 <&clk IMX8MP_CLK_USB_ROOT>;
1283			clock-names = "hsio", "suspend";
1284			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1285			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
1286			#address-cells = <1>;
1287			#size-cells = <1>;
1288			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1289			ranges;
1290			status = "disabled";
1291
1292			usb_dwc3_0: usb@38100000 {
1293				compatible = "snps,dwc3";
1294				reg = <0x38100000 0x10000>;
1295				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1296					 <&clk IMX8MP_CLK_USB_CORE_REF>,
1297					 <&clk IMX8MP_CLK_USB_ROOT>;
1298				clock-names = "bus_early", "ref", "suspend";
1299				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1300				phys = <&usb3_phy0>, <&usb3_phy0>;
1301				phy-names = "usb2-phy", "usb3-phy";
1302				snps,gfladj-refclk-lpm-sel-quirk;
1303			};
1304
1305		};
1306
1307		usb3_phy1: usb-phy@382f0040 {
1308			compatible = "fsl,imx8mp-usb-phy";
1309			reg = <0x382f0040 0x40>;
1310			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1311			clock-names = "phy";
1312			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1313			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1314			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
1315			#phy-cells = <0>;
1316			status = "disabled";
1317		};
1318
1319		usb3_1: usb@32f10108 {
1320			compatible = "fsl,imx8mp-dwc3";
1321			reg = <0x32f10108 0x8>,
1322			      <0x382f0000 0x20>;
1323			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1324				 <&clk IMX8MP_CLK_USB_ROOT>;
1325			clock-names = "hsio", "suspend";
1326			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1327			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
1328			#address-cells = <1>;
1329			#size-cells = <1>;
1330			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1331			ranges;
1332			status = "disabled";
1333
1334			usb_dwc3_1: usb@38200000 {
1335				compatible = "snps,dwc3";
1336				reg = <0x38200000 0x10000>;
1337				clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
1338					 <&clk IMX8MP_CLK_USB_CORE_REF>,
1339					 <&clk IMX8MP_CLK_USB_ROOT>;
1340				clock-names = "bus_early", "ref", "suspend";
1341				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1342				phys = <&usb3_phy1>, <&usb3_phy1>;
1343				phy-names = "usb2-phy", "usb3-phy";
1344				snps,gfladj-refclk-lpm-sel-quirk;
1345			};
1346		};
1347
1348		dsp: dsp@3b6e8000 {
1349			compatible = "fsl,imx8mp-dsp";
1350			reg = <0x3b6e8000 0x88000>;
1351			mbox-names = "txdb0", "txdb1",
1352				"rxdb0", "rxdb1";
1353			mboxes = <&mu2 2 0>, <&mu2 2 1>,
1354				<&mu2 3 0>, <&mu2 3 1>;
1355			memory-region = <&dsp_reserved>;
1356			status = "disabled";
1357		};
1358	};
1359};
1360