1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 A53_0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&A53_L2>; 64 nvmem-cells = <&cpu_speed_grade>; 65 nvmem-cell-names = "speed_grade"; 66 operating-points-v2 = <&a53_opp_table>; 67 #cooling-cells = <2>; 68 }; 69 70 A53_1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x1>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MP_CLK_ARM>; 76 enable-method = "psci"; 77 i-cache-size = <0x8000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <128>; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A53_2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x2>; 92 clock-latency = <61036>; 93 clocks = <&clk IMX8MP_CLK_ARM>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 }; 105 106 A53_3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x3>; 110 clock-latency = <61036>; 111 clocks = <&clk IMX8MP_CLK_ARM>; 112 enable-method = "psci"; 113 i-cache-size = <0x8000>; 114 i-cache-line-size = <64>; 115 i-cache-sets = <256>; 116 d-cache-size = <0x8000>; 117 d-cache-line-size = <64>; 118 d-cache-sets = <128>; 119 next-level-cache = <&A53_L2>; 120 operating-points-v2 = <&a53_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A53_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-unified; 127 cache-level = <2>; 128 cache-size = <0x80000>; 129 cache-line-size = <64>; 130 cache-sets = <512>; 131 }; 132 }; 133 134 a53_opp_table: opp-table { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-1200000000 { 139 opp-hz = /bits/ 64 <1200000000>; 140 opp-microvolt = <850000>; 141 opp-supported-hw = <0x8a0>, <0x7>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 146 opp-1600000000 { 147 opp-hz = /bits/ 64 <1600000000>; 148 opp-microvolt = <950000>; 149 opp-supported-hw = <0xa0>, <0x7>; 150 clock-latency-ns = <150000>; 151 opp-suspend; 152 }; 153 154 opp-1800000000 { 155 opp-hz = /bits/ 64 <1800000000>; 156 opp-microvolt = <1000000>; 157 opp-supported-hw = <0x20>, <0x3>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 }; 162 163 osc_32k: clock-osc-32k { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <32768>; 167 clock-output-names = "osc_32k"; 168 }; 169 170 osc_24m: clock-osc-24m { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <24000000>; 174 clock-output-names = "osc_24m"; 175 }; 176 177 clk_ext1: clock-ext1 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext1"; 182 }; 183 184 clk_ext2: clock-ext2 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <133000000>; 188 clock-output-names = "clk_ext2"; 189 }; 190 191 clk_ext3: clock-ext3 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext3"; 196 }; 197 198 clk_ext4: clock-ext4 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext4"; 203 }; 204 205 reserved-memory { 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges; 209 210 dsp_reserved: dsp@92400000 { 211 reg = <0 0x92400000 0 0x2000000>; 212 no-map; 213 }; 214 }; 215 216 pmu { 217 compatible = "arm,cortex-a53-pmu"; 218 interrupts = <GIC_PPI 7 219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0"; 224 method = "smc"; 225 }; 226 227 thermal-zones { 228 cpu-thermal { 229 polling-delay-passive = <250>; 230 polling-delay = <2000>; 231 thermal-sensors = <&tmu 0>; 232 trips { 233 cpu_alert0: trip0 { 234 temperature = <85000>; 235 hysteresis = <2000>; 236 type = "passive"; 237 }; 238 239 cpu_crit0: trip1 { 240 temperature = <95000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 }; 245 246 cooling-maps { 247 map0 { 248 trip = <&cpu_alert0>; 249 cooling-device = 250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 254 }; 255 }; 256 }; 257 258 soc-thermal { 259 polling-delay-passive = <250>; 260 polling-delay = <2000>; 261 thermal-sensors = <&tmu 1>; 262 trips { 263 soc_alert0: trip0 { 264 temperature = <85000>; 265 hysteresis = <2000>; 266 type = "passive"; 267 }; 268 269 soc_crit0: trip1 { 270 temperature = <95000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 276 cooling-maps { 277 map0 { 278 trip = <&soc_alert0>; 279 cooling-device = 280 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 281 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 282 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 283 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 284 }; 285 }; 286 }; 287 }; 288 289 timer { 290 compatible = "arm,armv8-timer"; 291 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 293 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 294 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 295 clock-frequency = <8000000>; 296 arm,no-tick-in-suspend; 297 }; 298 299 soc: soc@0 { 300 compatible = "fsl,imx8mp-soc", "simple-bus"; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0x0 0x0 0x0 0x3e000000>; 304 nvmem-cells = <&imx8mp_uid>; 305 nvmem-cell-names = "soc_unique_id"; 306 307 aips1: bus@30000000 { 308 compatible = "fsl,aips-bus", "simple-bus"; 309 reg = <0x30000000 0x400000>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges; 313 314 gpio1: gpio@30200000 { 315 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 316 reg = <0x30200000 0x10000>; 317 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 gpio-ranges = <&iomuxc 0 5 30>; 325 }; 326 327 gpio2: gpio@30210000 { 328 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 329 reg = <0x30210000 0x10000>; 330 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 gpio-ranges = <&iomuxc 0 35 21>; 338 }; 339 340 gpio3: gpio@30220000 { 341 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 342 reg = <0x30220000 0x10000>; 343 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 351 }; 352 353 gpio4: gpio@30230000 { 354 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 355 reg = <0x30230000 0x10000>; 356 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 gpio-ranges = <&iomuxc 0 82 32>; 364 }; 365 366 gpio5: gpio@30240000 { 367 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 368 reg = <0x30240000 0x10000>; 369 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 gpio-ranges = <&iomuxc 0 114 30>; 377 }; 378 379 tmu: tmu@30260000 { 380 compatible = "fsl,imx8mp-tmu"; 381 reg = <0x30260000 0x10000>; 382 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 383 #thermal-sensor-cells = <1>; 384 }; 385 386 wdog1: watchdog@30280000 { 387 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 388 reg = <0x30280000 0x10000>; 389 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 391 status = "disabled"; 392 }; 393 394 wdog2: watchdog@30290000 { 395 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 396 reg = <0x30290000 0x10000>; 397 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 399 status = "disabled"; 400 }; 401 402 wdog3: watchdog@302a0000 { 403 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 404 reg = <0x302a0000 0x10000>; 405 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 407 status = "disabled"; 408 }; 409 410 iomuxc: pinctrl@30330000 { 411 compatible = "fsl,imx8mp-iomuxc"; 412 reg = <0x30330000 0x10000>; 413 }; 414 415 gpr: iomuxc-gpr@30340000 { 416 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 417 reg = <0x30340000 0x10000>; 418 }; 419 420 ocotp: efuse@30350000 { 421 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 422 reg = <0x30350000 0x10000>; 423 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 424 /* For nvmem subnodes */ 425 #address-cells = <1>; 426 #size-cells = <1>; 427 428 imx8mp_uid: unique-id@420 { 429 reg = <0x8 0x8>; 430 }; 431 432 cpu_speed_grade: speed-grade@10 { 433 reg = <0x10 4>; 434 }; 435 436 eth_mac1: mac-address@90 { 437 reg = <0x90 6>; 438 }; 439 440 eth_mac2: mac-address@96 { 441 reg = <0x96 6>; 442 }; 443 }; 444 445 anatop: clock-controller@30360000 { 446 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 447 reg = <0x30360000 0x10000>; 448 #clock-cells = <1>; 449 }; 450 451 snvs: snvs@30370000 { 452 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 453 reg = <0x30370000 0x10000>; 454 455 snvs_rtc: snvs-rtc-lp { 456 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 457 regmap =<&snvs>; 458 offset = <0x34>; 459 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 462 clock-names = "snvs-rtc"; 463 }; 464 465 snvs_pwrkey: snvs-powerkey { 466 compatible = "fsl,sec-v4.0-pwrkey"; 467 regmap = <&snvs>; 468 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 470 clock-names = "snvs-pwrkey"; 471 linux,keycode = <KEY_POWER>; 472 wakeup-source; 473 status = "disabled"; 474 }; 475 476 snvs_lpgpr: snvs-lpgpr { 477 compatible = "fsl,imx8mp-snvs-lpgpr", 478 "fsl,imx7d-snvs-lpgpr"; 479 }; 480 }; 481 482 clk: clock-controller@30380000 { 483 compatible = "fsl,imx8mp-ccm"; 484 reg = <0x30380000 0x10000>; 485 #clock-cells = <1>; 486 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 487 <&clk_ext3>, <&clk_ext4>; 488 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 489 "clk_ext3", "clk_ext4"; 490 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 491 <&clk IMX8MP_CLK_A53_CORE>, 492 <&clk IMX8MP_CLK_NOC>, 493 <&clk IMX8MP_CLK_NOC_IO>, 494 <&clk IMX8MP_CLK_GIC>, 495 <&clk IMX8MP_CLK_AUDIO_AHB>, 496 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, 497 <&clk IMX8MP_AUDIO_PLL1>, 498 <&clk IMX8MP_AUDIO_PLL2>; 499 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 500 <&clk IMX8MP_ARM_PLL_OUT>, 501 <&clk IMX8MP_SYS_PLL2_1000M>, 502 <&clk IMX8MP_SYS_PLL1_800M>, 503 <&clk IMX8MP_SYS_PLL2_500M>, 504 <&clk IMX8MP_SYS_PLL1_800M>, 505 <&clk IMX8MP_SYS_PLL1_800M>; 506 assigned-clock-rates = <0>, <0>, 507 <1000000000>, 508 <800000000>, 509 <500000000>, 510 <400000000>, 511 <800000000>, 512 <393216000>, 513 <361267200>; 514 }; 515 516 src: reset-controller@30390000 { 517 compatible = "fsl,imx8mp-src", "syscon"; 518 reg = <0x30390000 0x10000>; 519 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 520 #reset-cells = <1>; 521 }; 522 523 gpc: gpc@303a0000 { 524 compatible = "fsl,imx8mp-gpc"; 525 reg = <0x303a0000 0x1000>; 526 interrupt-parent = <&gic>; 527 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 528 interrupt-controller; 529 #interrupt-cells = <3>; 530 531 pgc { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 535 pgc_mipi_phy1: power-domain@0 { 536 #power-domain-cells = <0>; 537 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 538 }; 539 540 pgc_pcie_phy: power-domain@1 { 541 #power-domain-cells = <0>; 542 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 543 }; 544 545 pgc_usb1_phy: power-domain@2 { 546 #power-domain-cells = <0>; 547 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 548 }; 549 550 pgc_usb2_phy: power-domain@3 { 551 #power-domain-cells = <0>; 552 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 553 }; 554 555 pgc_gpu2d: power-domain@6 { 556 #power-domain-cells = <0>; 557 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 558 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 559 power-domains = <&pgc_gpumix>; 560 }; 561 562 pgc_gpumix: power-domain@7 { 563 #power-domain-cells = <0>; 564 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 565 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 566 <&clk IMX8MP_CLK_GPU_AHB>; 567 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 568 <&clk IMX8MP_CLK_GPU_AHB>; 569 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 570 <&clk IMX8MP_SYS_PLL1_800M>; 571 assigned-clock-rates = <800000000>, <400000000>; 572 }; 573 574 pgc_gpu3d: power-domain@9 { 575 #power-domain-cells = <0>; 576 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 577 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 578 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 579 power-domains = <&pgc_gpumix>; 580 }; 581 582 pgc_mediamix: power-domain@10 { 583 #power-domain-cells = <0>; 584 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 585 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 586 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 587 }; 588 589 pgc_mipi_phy2: power-domain@16 { 590 #power-domain-cells = <0>; 591 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 592 }; 593 594 pgc_hsiomix: power-domain@17 { 595 #power-domain-cells = <0>; 596 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 597 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 598 <&clk IMX8MP_CLK_HSIO_ROOT>; 599 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 600 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 601 assigned-clock-rates = <500000000>; 602 }; 603 604 pgc_ispdwp: power-domain@18 { 605 #power-domain-cells = <0>; 606 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 607 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 608 }; 609 610 pgc_vpumix: power-domain@19 { 611 #power-domain-cells = <0>; 612 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 613 clocks =<&clk IMX8MP_CLK_VPU_ROOT>; 614 }; 615 616 pgc_vpu_g1: power-domain@20 { 617 #power-domain-cells = <0>; 618 power-domains = <&pgc_vpumix>; 619 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 620 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 621 }; 622 623 pgc_vpu_g2: power-domain@21 { 624 #power-domain-cells = <0>; 625 power-domains = <&pgc_vpumix>; 626 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 627 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 628 }; 629 630 pgc_vpu_vc8000e: power-domain@22 { 631 #power-domain-cells = <0>; 632 power-domains = <&pgc_vpumix>; 633 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 634 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 635 }; 636 637 pgc_mlmix: power-domain@24 { 638 #power-domain-cells = <0>; 639 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 640 clocks = <&clk IMX8MP_CLK_ML_AXI>, 641 <&clk IMX8MP_CLK_ML_AHB>, 642 <&clk IMX8MP_CLK_NPU_ROOT>; 643 }; 644 }; 645 }; 646 }; 647 648 aips2: bus@30400000 { 649 compatible = "fsl,aips-bus", "simple-bus"; 650 reg = <0x30400000 0x400000>; 651 #address-cells = <1>; 652 #size-cells = <1>; 653 ranges; 654 655 pwm1: pwm@30660000 { 656 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 657 reg = <0x30660000 0x10000>; 658 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 660 <&clk IMX8MP_CLK_PWM1_ROOT>; 661 clock-names = "ipg", "per"; 662 #pwm-cells = <3>; 663 status = "disabled"; 664 }; 665 666 pwm2: pwm@30670000 { 667 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 668 reg = <0x30670000 0x10000>; 669 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 671 <&clk IMX8MP_CLK_PWM2_ROOT>; 672 clock-names = "ipg", "per"; 673 #pwm-cells = <3>; 674 status = "disabled"; 675 }; 676 677 pwm3: pwm@30680000 { 678 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 679 reg = <0x30680000 0x10000>; 680 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 682 <&clk IMX8MP_CLK_PWM3_ROOT>; 683 clock-names = "ipg", "per"; 684 #pwm-cells = <3>; 685 status = "disabled"; 686 }; 687 688 pwm4: pwm@30690000 { 689 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 690 reg = <0x30690000 0x10000>; 691 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 693 <&clk IMX8MP_CLK_PWM4_ROOT>; 694 clock-names = "ipg", "per"; 695 #pwm-cells = <3>; 696 status = "disabled"; 697 }; 698 699 system_counter: timer@306a0000 { 700 compatible = "nxp,sysctr-timer"; 701 reg = <0x306a0000 0x20000>; 702 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&osc_24m>; 704 clock-names = "per"; 705 }; 706 }; 707 708 aips3: bus@30800000 { 709 compatible = "fsl,aips-bus", "simple-bus"; 710 reg = <0x30800000 0x400000>; 711 #address-cells = <1>; 712 #size-cells = <1>; 713 ranges; 714 715 ecspi1: spi@30820000 { 716 #address-cells = <1>; 717 #size-cells = <0>; 718 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 719 reg = <0x30820000 0x10000>; 720 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 722 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 723 clock-names = "ipg", "per"; 724 assigned-clock-rates = <80000000>; 725 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 726 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 727 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 728 dma-names = "rx", "tx"; 729 status = "disabled"; 730 }; 731 732 ecspi2: spi@30830000 { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 736 reg = <0x30830000 0x10000>; 737 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 739 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 740 clock-names = "ipg", "per"; 741 assigned-clock-rates = <80000000>; 742 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 743 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 744 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 745 dma-names = "rx", "tx"; 746 status = "disabled"; 747 }; 748 749 ecspi3: spi@30840000 { 750 #address-cells = <1>; 751 #size-cells = <0>; 752 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 753 reg = <0x30840000 0x10000>; 754 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 756 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 757 clock-names = "ipg", "per"; 758 assigned-clock-rates = <80000000>; 759 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 760 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 761 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 762 dma-names = "rx", "tx"; 763 status = "disabled"; 764 }; 765 766 uart1: serial@30860000 { 767 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 768 reg = <0x30860000 0x10000>; 769 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 771 <&clk IMX8MP_CLK_UART1_ROOT>; 772 clock-names = "ipg", "per"; 773 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 774 dma-names = "rx", "tx"; 775 status = "disabled"; 776 }; 777 778 uart3: serial@30880000 { 779 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 780 reg = <0x30880000 0x10000>; 781 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 783 <&clk IMX8MP_CLK_UART3_ROOT>; 784 clock-names = "ipg", "per"; 785 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 786 dma-names = "rx", "tx"; 787 status = "disabled"; 788 }; 789 790 uart2: serial@30890000 { 791 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 792 reg = <0x30890000 0x10000>; 793 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 795 <&clk IMX8MP_CLK_UART2_ROOT>; 796 clock-names = "ipg", "per"; 797 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 798 dma-names = "rx", "tx"; 799 status = "disabled"; 800 }; 801 802 flexcan1: can@308c0000 { 803 compatible = "fsl,imx8mp-flexcan"; 804 reg = <0x308c0000 0x10000>; 805 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 807 <&clk IMX8MP_CLK_CAN1_ROOT>; 808 clock-names = "ipg", "per"; 809 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 810 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 811 assigned-clock-rates = <40000000>; 812 fsl,clk-source = /bits/ 8 <0>; 813 fsl,stop-mode = <&gpr 0x10 4>; 814 status = "disabled"; 815 }; 816 817 flexcan2: can@308d0000 { 818 compatible = "fsl,imx8mp-flexcan"; 819 reg = <0x308d0000 0x10000>; 820 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 822 <&clk IMX8MP_CLK_CAN2_ROOT>; 823 clock-names = "ipg", "per"; 824 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 825 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 826 assigned-clock-rates = <40000000>; 827 fsl,clk-source = /bits/ 8 <0>; 828 fsl,stop-mode = <&gpr 0x10 5>; 829 status = "disabled"; 830 }; 831 832 crypto: crypto@30900000 { 833 compatible = "fsl,sec-v4.0"; 834 #address-cells = <1>; 835 #size-cells = <1>; 836 reg = <0x30900000 0x40000>; 837 ranges = <0 0x30900000 0x40000>; 838 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&clk IMX8MP_CLK_AHB>, 840 <&clk IMX8MP_CLK_IPG_ROOT>; 841 clock-names = "aclk", "ipg"; 842 843 sec_jr0: jr@1000 { 844 compatible = "fsl,sec-v4.0-job-ring"; 845 reg = <0x1000 0x1000>; 846 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 847 status = "disabled"; 848 }; 849 850 sec_jr1: jr@2000 { 851 compatible = "fsl,sec-v4.0-job-ring"; 852 reg = <0x2000 0x1000>; 853 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 854 }; 855 856 sec_jr2: jr@3000 { 857 compatible = "fsl,sec-v4.0-job-ring"; 858 reg = <0x3000 0x1000>; 859 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 860 }; 861 }; 862 863 i2c1: i2c@30a20000 { 864 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 reg = <0x30a20000 0x10000>; 868 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 870 status = "disabled"; 871 }; 872 873 i2c2: i2c@30a30000 { 874 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 reg = <0x30a30000 0x10000>; 878 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 880 status = "disabled"; 881 }; 882 883 i2c3: i2c@30a40000 { 884 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 reg = <0x30a40000 0x10000>; 888 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 890 status = "disabled"; 891 }; 892 893 i2c4: i2c@30a50000 { 894 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 reg = <0x30a50000 0x10000>; 898 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 900 status = "disabled"; 901 }; 902 903 uart4: serial@30a60000 { 904 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 905 reg = <0x30a60000 0x10000>; 906 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 908 <&clk IMX8MP_CLK_UART4_ROOT>; 909 clock-names = "ipg", "per"; 910 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 911 dma-names = "rx", "tx"; 912 status = "disabled"; 913 }; 914 915 mu: mailbox@30aa0000 { 916 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 917 reg = <0x30aa0000 0x10000>; 918 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 920 #mbox-cells = <2>; 921 }; 922 923 mu2: mailbox@30e60000 { 924 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 925 reg = <0x30e60000 0x10000>; 926 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 927 #mbox-cells = <2>; 928 status = "disabled"; 929 }; 930 931 i2c5: i2c@30ad0000 { 932 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 reg = <0x30ad0000 0x10000>; 936 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 938 status = "disabled"; 939 }; 940 941 i2c6: i2c@30ae0000 { 942 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 reg = <0x30ae0000 0x10000>; 946 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 948 status = "disabled"; 949 }; 950 951 usdhc1: mmc@30b40000 { 952 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 953 reg = <0x30b40000 0x10000>; 954 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&clk IMX8MP_CLK_DUMMY>, 956 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 957 <&clk IMX8MP_CLK_USDHC1_ROOT>; 958 clock-names = "ipg", "ahb", "per"; 959 fsl,tuning-start-tap = <20>; 960 fsl,tuning-step = <2>; 961 bus-width = <4>; 962 status = "disabled"; 963 }; 964 965 usdhc2: mmc@30b50000 { 966 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 967 reg = <0x30b50000 0x10000>; 968 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&clk IMX8MP_CLK_DUMMY>, 970 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 971 <&clk IMX8MP_CLK_USDHC2_ROOT>; 972 clock-names = "ipg", "ahb", "per"; 973 fsl,tuning-start-tap = <20>; 974 fsl,tuning-step = <2>; 975 bus-width = <4>; 976 status = "disabled"; 977 }; 978 979 usdhc3: mmc@30b60000 { 980 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 981 reg = <0x30b60000 0x10000>; 982 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&clk IMX8MP_CLK_DUMMY>, 984 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 985 <&clk IMX8MP_CLK_USDHC3_ROOT>; 986 clock-names = "ipg", "ahb", "per"; 987 fsl,tuning-start-tap = <20>; 988 fsl,tuning-step = <2>; 989 bus-width = <4>; 990 status = "disabled"; 991 }; 992 993 flexspi: spi@30bb0000 { 994 compatible = "nxp,imx8mp-fspi"; 995 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 996 reg-names = "fspi_base", "fspi_mmap"; 997 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 999 <&clk IMX8MP_CLK_QSPI_ROOT>; 1000 clock-names = "fspi_en", "fspi"; 1001 assigned-clock-rates = <80000000>; 1002 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 status = "disabled"; 1006 }; 1007 1008 sdma1: dma-controller@30bd0000 { 1009 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1010 reg = <0x30bd0000 0x10000>; 1011 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1013 <&clk IMX8MP_CLK_AHB>; 1014 clock-names = "ipg", "ahb"; 1015 #dma-cells = <3>; 1016 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1017 }; 1018 1019 fec: ethernet@30be0000 { 1020 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1021 reg = <0x30be0000 0x10000>; 1022 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1027 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1028 <&clk IMX8MP_CLK_ENET_TIMER>, 1029 <&clk IMX8MP_CLK_ENET_REF>, 1030 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1031 clock-names = "ipg", "ahb", "ptp", 1032 "enet_clk_ref", "enet_out"; 1033 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1034 <&clk IMX8MP_CLK_ENET_TIMER>, 1035 <&clk IMX8MP_CLK_ENET_REF>, 1036 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1037 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1038 <&clk IMX8MP_SYS_PLL2_100M>, 1039 <&clk IMX8MP_SYS_PLL2_125M>, 1040 <&clk IMX8MP_SYS_PLL2_50M>; 1041 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1042 fsl,num-tx-queues = <3>; 1043 fsl,num-rx-queues = <3>; 1044 nvmem-cells = <ð_mac1>; 1045 nvmem-cell-names = "mac-address"; 1046 fsl,stop-mode = <&gpr 0x10 3>; 1047 status = "disabled"; 1048 }; 1049 1050 eqos: ethernet@30bf0000 { 1051 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1052 reg = <0x30bf0000 0x10000>; 1053 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1055 interrupt-names = "macirq", "eth_wake_irq"; 1056 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1057 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1058 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1059 <&clk IMX8MP_CLK_ENET_QOS>; 1060 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1061 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1062 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1063 <&clk IMX8MP_CLK_ENET_QOS>; 1064 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1065 <&clk IMX8MP_SYS_PLL2_100M>, 1066 <&clk IMX8MP_SYS_PLL2_125M>; 1067 assigned-clock-rates = <0>, <100000000>, <125000000>; 1068 nvmem-cells = <ð_mac2>; 1069 nvmem-cell-names = "mac-address"; 1070 intf_mode = <&gpr 0x4>; 1071 status = "disabled"; 1072 }; 1073 }; 1074 1075 noc: interconnect@32700000 { 1076 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1077 reg = <0x32700000 0x100000>; 1078 clocks = <&clk IMX8MP_CLK_NOC>; 1079 #interconnect-cells = <1>; 1080 operating-points-v2 = <&noc_opp_table>; 1081 1082 noc_opp_table: opp-table { 1083 compatible = "operating-points-v2"; 1084 1085 opp-200000000 { 1086 opp-hz = /bits/ 64 <200000000>; 1087 }; 1088 1089 opp-1000000000 { 1090 opp-hz = /bits/ 64 <1000000000>; 1091 }; 1092 }; 1093 }; 1094 1095 aips4: bus@32c00000 { 1096 compatible = "fsl,aips-bus", "simple-bus"; 1097 reg = <0x32c00000 0x400000>; 1098 #address-cells = <1>; 1099 #size-cells = <1>; 1100 ranges; 1101 1102 media_blk_ctrl: blk-ctrl@32ec0000 { 1103 compatible = "fsl,imx8mp-media-blk-ctrl", 1104 "syscon"; 1105 reg = <0x32ec0000 0x10000>; 1106 power-domains = <&pgc_mediamix>, 1107 <&pgc_mipi_phy1>, 1108 <&pgc_mipi_phy1>, 1109 <&pgc_mediamix>, 1110 <&pgc_mediamix>, 1111 <&pgc_mipi_phy2>, 1112 <&pgc_mediamix>, 1113 <&pgc_ispdwp>, 1114 <&pgc_ispdwp>, 1115 <&pgc_mipi_phy2>; 1116 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1117 "lcdif1", "isi", "mipi-csi2", 1118 "lcdif2", "isp", "dwe", 1119 "mipi-dsi2"; 1120 interconnects = 1121 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1122 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1123 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1124 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1125 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1126 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1127 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1128 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1129 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1130 "isi1", "isi2", "isp0", "isp1", 1131 "dwe"; 1132 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1133 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1134 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1135 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1136 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1137 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1138 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1139 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1140 clock-names = "apb", "axi", "cam1", "cam2", 1141 "disp1", "disp2", "isp", "phy"; 1142 1143 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1144 <&clk IMX8MP_CLK_MEDIA_APB>; 1145 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1146 <&clk IMX8MP_SYS_PLL1_800M>; 1147 assigned-clock-rates = <500000000>, <200000000>; 1148 1149 #power-domain-cells = <1>; 1150 }; 1151 1152 pcie_phy: pcie-phy@32f00000 { 1153 compatible = "fsl,imx8mp-pcie-phy"; 1154 reg = <0x32f00000 0x10000>; 1155 resets = <&src IMX8MP_RESET_PCIEPHY>, 1156 <&src IMX8MP_RESET_PCIEPHY_PERST>; 1157 reset-names = "pciephy", "perst"; 1158 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 1159 #phy-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 hsio_blk_ctrl: blk-ctrl@32f10000 { 1164 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 1165 reg = <0x32f10000 0x24>; 1166 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1167 <&clk IMX8MP_CLK_PCIE_ROOT>; 1168 clock-names = "usb", "pcie"; 1169 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 1170 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 1171 <&pgc_hsiomix>, <&pgc_pcie_phy>; 1172 power-domain-names = "bus", "usb", "usb-phy1", 1173 "usb-phy2", "pcie", "pcie-phy"; 1174 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 1175 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 1176 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 1177 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 1178 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 1179 #power-domain-cells = <1>; 1180 }; 1181 }; 1182 1183 pcie: pcie@33800000 { 1184 compatible = "fsl,imx8mp-pcie"; 1185 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1186 reg-names = "dbi", "config"; 1187 #address-cells = <3>; 1188 #size-cells = <2>; 1189 device_type = "pci"; 1190 bus-range = <0x00 0xff>; 1191 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1192 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1193 num-lanes = <1>; 1194 num-viewport = <4>; 1195 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1196 interrupt-names = "msi"; 1197 #interrupt-cells = <1>; 1198 interrupt-map-mask = <0 0 0 0x7>; 1199 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1200 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1201 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1202 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1203 fsl,max-link-speed = <3>; 1204 linux,pci-domain = <0>; 1205 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1206 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1207 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1208 reset-names = "apps", "turnoff"; 1209 phys = <&pcie_phy>; 1210 phy-names = "pcie-phy"; 1211 status = "disabled"; 1212 }; 1213 1214 gpu3d: gpu@38000000 { 1215 compatible = "vivante,gc"; 1216 reg = <0x38000000 0x8000>; 1217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 1219 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 1220 <&clk IMX8MP_CLK_GPU_ROOT>, 1221 <&clk IMX8MP_CLK_GPU_AHB>; 1222 clock-names = "core", "shader", "bus", "reg"; 1223 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 1224 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 1225 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1226 <&clk IMX8MP_SYS_PLL1_800M>; 1227 assigned-clock-rates = <800000000>, <800000000>; 1228 power-domains = <&pgc_gpu3d>; 1229 }; 1230 1231 gpu2d: gpu@38008000 { 1232 compatible = "vivante,gc"; 1233 reg = <0x38008000 0x8000>; 1234 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 1236 <&clk IMX8MP_CLK_GPU_ROOT>, 1237 <&clk IMX8MP_CLK_GPU_AHB>; 1238 clock-names = "core", "bus", "reg"; 1239 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 1240 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1241 assigned-clock-rates = <800000000>; 1242 power-domains = <&pgc_gpu2d>; 1243 }; 1244 1245 vpumix_blk_ctrl: blk-ctrl@38330000 { 1246 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 1247 reg = <0x38330000 0x100>; 1248 #power-domain-cells = <1>; 1249 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1250 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 1251 power-domain-names = "bus", "g1", "g2", "vc8000e"; 1252 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 1253 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 1254 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 1255 clock-names = "g1", "g2", "vc8000e"; 1256 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 1257 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 1258 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 1259 interconnect-names = "g1", "g2", "vc8000e"; 1260 }; 1261 1262 gic: interrupt-controller@38800000 { 1263 compatible = "arm,gic-v3"; 1264 reg = <0x38800000 0x10000>, 1265 <0x38880000 0xc0000>; 1266 #interrupt-cells = <3>; 1267 interrupt-controller; 1268 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1269 interrupt-parent = <&gic>; 1270 }; 1271 1272 edacmc: memory-controller@3d400000 { 1273 compatible = "snps,ddrc-3.80a"; 1274 reg = <0x3d400000 0x400000>; 1275 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1276 }; 1277 1278 ddr-pmu@3d800000 { 1279 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1280 reg = <0x3d800000 0x400000>; 1281 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1282 }; 1283 1284 usb3_phy0: usb-phy@381f0040 { 1285 compatible = "fsl,imx8mp-usb-phy"; 1286 reg = <0x381f0040 0x40>; 1287 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1288 clock-names = "phy"; 1289 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1290 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1291 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 1292 #phy-cells = <0>; 1293 status = "disabled"; 1294 }; 1295 1296 usb3_0: usb@32f10100 { 1297 compatible = "fsl,imx8mp-dwc3"; 1298 reg = <0x32f10100 0x8>, 1299 <0x381f0000 0x20>; 1300 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1301 <&clk IMX8MP_CLK_USB_SUSP>; 1302 clock-names = "hsio", "suspend"; 1303 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1304 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 1305 #address-cells = <1>; 1306 #size-cells = <1>; 1307 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 1308 ranges; 1309 status = "disabled"; 1310 1311 usb_dwc3_0: usb@38100000 { 1312 compatible = "snps,dwc3"; 1313 reg = <0x38100000 0x10000>; 1314 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1315 <&clk IMX8MP_CLK_USB_CORE_REF>, 1316 <&clk IMX8MP_CLK_USB_SUSP>; 1317 clock-names = "bus_early", "ref", "suspend"; 1318 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1319 phys = <&usb3_phy0>, <&usb3_phy0>; 1320 phy-names = "usb2-phy", "usb3-phy"; 1321 snps,gfladj-refclk-lpm-sel-quirk; 1322 }; 1323 1324 }; 1325 1326 usb3_phy1: usb-phy@382f0040 { 1327 compatible = "fsl,imx8mp-usb-phy"; 1328 reg = <0x382f0040 0x40>; 1329 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1330 clock-names = "phy"; 1331 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1332 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1333 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 1334 #phy-cells = <0>; 1335 status = "disabled"; 1336 }; 1337 1338 usb3_1: usb@32f10108 { 1339 compatible = "fsl,imx8mp-dwc3"; 1340 reg = <0x32f10108 0x8>, 1341 <0x382f0000 0x20>; 1342 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1343 <&clk IMX8MP_CLK_USB_SUSP>; 1344 clock-names = "hsio", "suspend"; 1345 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1346 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 1347 #address-cells = <1>; 1348 #size-cells = <1>; 1349 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 1350 ranges; 1351 status = "disabled"; 1352 1353 usb_dwc3_1: usb@38200000 { 1354 compatible = "snps,dwc3"; 1355 reg = <0x38200000 0x10000>; 1356 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1357 <&clk IMX8MP_CLK_USB_CORE_REF>, 1358 <&clk IMX8MP_CLK_USB_SUSP>; 1359 clock-names = "bus_early", "ref", "suspend"; 1360 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1361 phys = <&usb3_phy1>, <&usb3_phy1>; 1362 phy-names = "usb2-phy", "usb3-phy"; 1363 snps,gfladj-refclk-lpm-sel-quirk; 1364 }; 1365 }; 1366 1367 dsp: dsp@3b6e8000 { 1368 compatible = "fsl,imx8mp-dsp"; 1369 reg = <0x3b6e8000 0x88000>; 1370 mbox-names = "txdb0", "txdb1", 1371 "rxdb0", "rxdb1"; 1372 mboxes = <&mu2 2 0>, <&mu2 2 1>, 1373 <&mu2 3 0>, <&mu2 3 1>; 1374 memory-region = <&dsp_reserved>; 1375 status = "disabled"; 1376 }; 1377 }; 1378}; 1379