1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 A53_0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&A53_L2>; 64 nvmem-cells = <&cpu_speed_grade>; 65 nvmem-cell-names = "speed_grade"; 66 operating-points-v2 = <&a53_opp_table>; 67 #cooling-cells = <2>; 68 }; 69 70 A53_1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x1>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MP_CLK_ARM>; 76 enable-method = "psci"; 77 i-cache-size = <0x8000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <128>; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A53_2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x2>; 92 clock-latency = <61036>; 93 clocks = <&clk IMX8MP_CLK_ARM>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 }; 105 106 A53_3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x3>; 110 clock-latency = <61036>; 111 clocks = <&clk IMX8MP_CLK_ARM>; 112 enable-method = "psci"; 113 i-cache-size = <0x8000>; 114 i-cache-line-size = <64>; 115 i-cache-sets = <256>; 116 d-cache-size = <0x8000>; 117 d-cache-line-size = <64>; 118 d-cache-sets = <128>; 119 next-level-cache = <&A53_L2>; 120 operating-points-v2 = <&a53_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A53_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-unified; 127 cache-level = <2>; 128 cache-size = <0x80000>; 129 cache-line-size = <64>; 130 cache-sets = <512>; 131 }; 132 }; 133 134 a53_opp_table: opp-table { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-1200000000 { 139 opp-hz = /bits/ 64 <1200000000>; 140 opp-microvolt = <850000>; 141 opp-supported-hw = <0x8a0>, <0x7>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 146 opp-1600000000 { 147 opp-hz = /bits/ 64 <1600000000>; 148 opp-microvolt = <950000>; 149 opp-supported-hw = <0xa0>, <0x7>; 150 clock-latency-ns = <150000>; 151 opp-suspend; 152 }; 153 154 opp-1800000000 { 155 opp-hz = /bits/ 64 <1800000000>; 156 opp-microvolt = <1000000>; 157 opp-supported-hw = <0x20>, <0x3>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 }; 162 163 osc_32k: clock-osc-32k { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <32768>; 167 clock-output-names = "osc_32k"; 168 }; 169 170 osc_24m: clock-osc-24m { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <24000000>; 174 clock-output-names = "osc_24m"; 175 }; 176 177 clk_ext1: clock-ext1 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext1"; 182 }; 183 184 clk_ext2: clock-ext2 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <133000000>; 188 clock-output-names = "clk_ext2"; 189 }; 190 191 clk_ext3: clock-ext3 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext3"; 196 }; 197 198 clk_ext4: clock-ext4 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext4"; 203 }; 204 205 reserved-memory { 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges; 209 210 dsp_reserved: dsp@92400000 { 211 reg = <0 0x92400000 0 0x2000000>; 212 no-map; 213 }; 214 }; 215 216 pmu { 217 compatible = "arm,cortex-a53-pmu"; 218 interrupts = <GIC_PPI 7 219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0"; 224 method = "smc"; 225 }; 226 227 thermal-zones { 228 cpu-thermal { 229 polling-delay-passive = <250>; 230 polling-delay = <2000>; 231 thermal-sensors = <&tmu 0>; 232 trips { 233 cpu_alert0: trip0 { 234 temperature = <85000>; 235 hysteresis = <2000>; 236 type = "passive"; 237 }; 238 239 cpu_crit0: trip1 { 240 temperature = <95000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 }; 245 246 cooling-maps { 247 map0 { 248 trip = <&cpu_alert0>; 249 cooling-device = 250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 254 }; 255 }; 256 }; 257 258 soc-thermal { 259 polling-delay-passive = <250>; 260 polling-delay = <2000>; 261 thermal-sensors = <&tmu 1>; 262 trips { 263 soc_alert0: trip0 { 264 temperature = <85000>; 265 hysteresis = <2000>; 266 type = "passive"; 267 }; 268 269 soc_crit0: trip1 { 270 temperature = <95000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 276 cooling-maps { 277 map0 { 278 trip = <&soc_alert0>; 279 cooling-device = 280 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 281 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 282 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 283 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 284 }; 285 }; 286 }; 287 }; 288 289 timer { 290 compatible = "arm,armv8-timer"; 291 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 293 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 294 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 295 clock-frequency = <8000000>; 296 arm,no-tick-in-suspend; 297 }; 298 299 soc: soc@0 { 300 compatible = "fsl,imx8mp-soc", "simple-bus"; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0x0 0x0 0x0 0x3e000000>; 304 nvmem-cells = <&imx8mp_uid>; 305 nvmem-cell-names = "soc_unique_id"; 306 307 aips1: bus@30000000 { 308 compatible = "fsl,aips-bus", "simple-bus"; 309 reg = <0x30000000 0x400000>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges; 313 314 gpio1: gpio@30200000 { 315 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 316 reg = <0x30200000 0x10000>; 317 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 gpio-ranges = <&iomuxc 0 5 30>; 325 }; 326 327 gpio2: gpio@30210000 { 328 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 329 reg = <0x30210000 0x10000>; 330 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 gpio-ranges = <&iomuxc 0 35 21>; 338 }; 339 340 gpio3: gpio@30220000 { 341 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 342 reg = <0x30220000 0x10000>; 343 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 351 }; 352 353 gpio4: gpio@30230000 { 354 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 355 reg = <0x30230000 0x10000>; 356 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 gpio-ranges = <&iomuxc 0 82 32>; 364 }; 365 366 gpio5: gpio@30240000 { 367 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 368 reg = <0x30240000 0x10000>; 369 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 gpio-ranges = <&iomuxc 0 114 30>; 377 }; 378 379 tmu: tmu@30260000 { 380 compatible = "fsl,imx8mp-tmu"; 381 reg = <0x30260000 0x10000>; 382 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 383 nvmem-cells = <&tmu_calib>; 384 nvmem-cell-names = "calib"; 385 #thermal-sensor-cells = <1>; 386 }; 387 388 wdog1: watchdog@30280000 { 389 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 390 reg = <0x30280000 0x10000>; 391 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 393 status = "disabled"; 394 }; 395 396 wdog2: watchdog@30290000 { 397 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 398 reg = <0x30290000 0x10000>; 399 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 401 status = "disabled"; 402 }; 403 404 wdog3: watchdog@302a0000 { 405 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 406 reg = <0x302a0000 0x10000>; 407 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 409 status = "disabled"; 410 }; 411 412 iomuxc: pinctrl@30330000 { 413 compatible = "fsl,imx8mp-iomuxc"; 414 reg = <0x30330000 0x10000>; 415 }; 416 417 gpr: syscon@30340000 { 418 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 419 reg = <0x30340000 0x10000>; 420 }; 421 422 ocotp: efuse@30350000 { 423 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 424 reg = <0x30350000 0x10000>; 425 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 426 /* For nvmem subnodes */ 427 #address-cells = <1>; 428 #size-cells = <1>; 429 430 /* 431 * The register address below maps to the MX8M 432 * Fusemap Description Table entries this way. 433 * Assuming 434 * reg = <ADDR SIZE>; 435 * then 436 * Fuse Address = (ADDR * 4) + 0x400 437 * Note that if SIZE is greater than 4, then 438 * each subsequent fuse is located at offset 439 * +0x10 in Fusemap Description Table (e.g. 440 * reg = <0x8 0x8> describes fuses 0x420 and 441 * 0x430). 442 */ 443 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 444 reg = <0x8 0x8>; 445 }; 446 447 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 448 reg = <0x10 4>; 449 }; 450 451 eth_mac1: mac-address@90 { /* 0x640 */ 452 reg = <0x90 6>; 453 }; 454 455 eth_mac2: mac-address@96 { /* 0x658 */ 456 reg = <0x96 6>; 457 }; 458 459 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 460 reg = <0x264 0x10>; 461 }; 462 }; 463 464 anatop: clock-controller@30360000 { 465 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 466 reg = <0x30360000 0x10000>; 467 #clock-cells = <1>; 468 }; 469 470 snvs: snvs@30370000 { 471 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 472 reg = <0x30370000 0x10000>; 473 474 snvs_rtc: snvs-rtc-lp { 475 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 476 regmap =<&snvs>; 477 offset = <0x34>; 478 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 481 clock-names = "snvs-rtc"; 482 }; 483 484 snvs_pwrkey: snvs-powerkey { 485 compatible = "fsl,sec-v4.0-pwrkey"; 486 regmap = <&snvs>; 487 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 489 clock-names = "snvs-pwrkey"; 490 linux,keycode = <KEY_POWER>; 491 wakeup-source; 492 status = "disabled"; 493 }; 494 495 snvs_lpgpr: snvs-lpgpr { 496 compatible = "fsl,imx8mp-snvs-lpgpr", 497 "fsl,imx7d-snvs-lpgpr"; 498 }; 499 }; 500 501 clk: clock-controller@30380000 { 502 compatible = "fsl,imx8mp-ccm"; 503 reg = <0x30380000 0x10000>; 504 #clock-cells = <1>; 505 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 506 <&clk_ext3>, <&clk_ext4>; 507 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 508 "clk_ext3", "clk_ext4"; 509 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 510 <&clk IMX8MP_CLK_A53_CORE>, 511 <&clk IMX8MP_CLK_NOC>, 512 <&clk IMX8MP_CLK_NOC_IO>, 513 <&clk IMX8MP_CLK_GIC>, 514 <&clk IMX8MP_CLK_AUDIO_AHB>, 515 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, 516 <&clk IMX8MP_AUDIO_PLL1>, 517 <&clk IMX8MP_AUDIO_PLL2>; 518 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 519 <&clk IMX8MP_ARM_PLL_OUT>, 520 <&clk IMX8MP_SYS_PLL2_1000M>, 521 <&clk IMX8MP_SYS_PLL1_800M>, 522 <&clk IMX8MP_SYS_PLL2_500M>, 523 <&clk IMX8MP_SYS_PLL1_800M>, 524 <&clk IMX8MP_SYS_PLL1_800M>; 525 assigned-clock-rates = <0>, <0>, 526 <1000000000>, 527 <800000000>, 528 <500000000>, 529 <400000000>, 530 <800000000>, 531 <393216000>, 532 <361267200>; 533 }; 534 535 src: reset-controller@30390000 { 536 compatible = "fsl,imx8mp-src", "syscon"; 537 reg = <0x30390000 0x10000>; 538 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 539 #reset-cells = <1>; 540 }; 541 542 gpc: gpc@303a0000 { 543 compatible = "fsl,imx8mp-gpc"; 544 reg = <0x303a0000 0x1000>; 545 interrupt-parent = <&gic>; 546 interrupt-controller; 547 #interrupt-cells = <3>; 548 549 pgc { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 553 pgc_mipi_phy1: power-domain@0 { 554 #power-domain-cells = <0>; 555 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 556 }; 557 558 pgc_pcie_phy: power-domain@1 { 559 #power-domain-cells = <0>; 560 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 561 }; 562 563 pgc_usb1_phy: power-domain@2 { 564 #power-domain-cells = <0>; 565 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 566 }; 567 568 pgc_usb2_phy: power-domain@3 { 569 #power-domain-cells = <0>; 570 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 571 }; 572 573 pgc_gpu2d: power-domain@6 { 574 #power-domain-cells = <0>; 575 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 576 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 577 power-domains = <&pgc_gpumix>; 578 }; 579 580 pgc_gpumix: power-domain@7 { 581 #power-domain-cells = <0>; 582 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 583 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 584 <&clk IMX8MP_CLK_GPU_AHB>; 585 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 586 <&clk IMX8MP_CLK_GPU_AHB>; 587 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 588 <&clk IMX8MP_SYS_PLL1_800M>; 589 assigned-clock-rates = <800000000>, <400000000>; 590 }; 591 592 pgc_gpu3d: power-domain@9 { 593 #power-domain-cells = <0>; 594 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 595 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 596 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 597 power-domains = <&pgc_gpumix>; 598 }; 599 600 pgc_mediamix: power-domain@10 { 601 #power-domain-cells = <0>; 602 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 603 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 604 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 605 }; 606 607 pgc_mipi_phy2: power-domain@16 { 608 #power-domain-cells = <0>; 609 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 610 }; 611 612 pgc_hsiomix: power-domains@17 { 613 #power-domain-cells = <0>; 614 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 615 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 616 <&clk IMX8MP_CLK_HSIO_ROOT>; 617 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 618 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 619 assigned-clock-rates = <500000000>; 620 }; 621 622 pgc_ispdwp: power-domain@18 { 623 #power-domain-cells = <0>; 624 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 625 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 626 }; 627 628 pgc_vpumix: power-domain@19 { 629 #power-domain-cells = <0>; 630 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 631 clocks =<&clk IMX8MP_CLK_VPU_ROOT>; 632 }; 633 634 pgc_vpu_g1: power-domain@20 { 635 #power-domain-cells = <0>; 636 power-domains = <&pgc_vpumix>; 637 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 638 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 639 }; 640 641 pgc_vpu_g2: power-domain@21 { 642 #power-domain-cells = <0>; 643 power-domains = <&pgc_vpumix>; 644 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 645 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 646 }; 647 648 pgc_vpu_vc8000e: power-domain@22 { 649 #power-domain-cells = <0>; 650 power-domains = <&pgc_vpumix>; 651 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 652 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 653 }; 654 655 pgc_mlmix: power-domain@24 { 656 #power-domain-cells = <0>; 657 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 658 clocks = <&clk IMX8MP_CLK_ML_AXI>, 659 <&clk IMX8MP_CLK_ML_AHB>, 660 <&clk IMX8MP_CLK_NPU_ROOT>; 661 }; 662 }; 663 }; 664 }; 665 666 aips2: bus@30400000 { 667 compatible = "fsl,aips-bus", "simple-bus"; 668 reg = <0x30400000 0x400000>; 669 #address-cells = <1>; 670 #size-cells = <1>; 671 ranges; 672 673 pwm1: pwm@30660000 { 674 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 675 reg = <0x30660000 0x10000>; 676 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 678 <&clk IMX8MP_CLK_PWM1_ROOT>; 679 clock-names = "ipg", "per"; 680 #pwm-cells = <3>; 681 status = "disabled"; 682 }; 683 684 pwm2: pwm@30670000 { 685 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 686 reg = <0x30670000 0x10000>; 687 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 689 <&clk IMX8MP_CLK_PWM2_ROOT>; 690 clock-names = "ipg", "per"; 691 #pwm-cells = <3>; 692 status = "disabled"; 693 }; 694 695 pwm3: pwm@30680000 { 696 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 697 reg = <0x30680000 0x10000>; 698 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 700 <&clk IMX8MP_CLK_PWM3_ROOT>; 701 clock-names = "ipg", "per"; 702 #pwm-cells = <3>; 703 status = "disabled"; 704 }; 705 706 pwm4: pwm@30690000 { 707 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 708 reg = <0x30690000 0x10000>; 709 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 711 <&clk IMX8MP_CLK_PWM4_ROOT>; 712 clock-names = "ipg", "per"; 713 #pwm-cells = <3>; 714 status = "disabled"; 715 }; 716 717 system_counter: timer@306a0000 { 718 compatible = "nxp,sysctr-timer"; 719 reg = <0x306a0000 0x20000>; 720 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&osc_24m>; 722 clock-names = "per"; 723 }; 724 }; 725 726 aips3: bus@30800000 { 727 compatible = "fsl,aips-bus", "simple-bus"; 728 reg = <0x30800000 0x400000>; 729 #address-cells = <1>; 730 #size-cells = <1>; 731 ranges; 732 733 spba-bus@30800000 { 734 compatible = "fsl,spba-bus", "simple-bus"; 735 reg = <0x30800000 0x100000>; 736 #address-cells = <1>; 737 #size-cells = <1>; 738 ranges; 739 740 ecspi1: spi@30820000 { 741 #address-cells = <1>; 742 #size-cells = <0>; 743 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 744 reg = <0x30820000 0x10000>; 745 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 747 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 748 clock-names = "ipg", "per"; 749 assigned-clock-rates = <80000000>; 750 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 751 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 752 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 753 dma-names = "rx", "tx"; 754 status = "disabled"; 755 }; 756 757 ecspi2: spi@30830000 { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 761 reg = <0x30830000 0x10000>; 762 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 764 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 765 clock-names = "ipg", "per"; 766 assigned-clock-rates = <80000000>; 767 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 768 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 769 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 770 dma-names = "rx", "tx"; 771 status = "disabled"; 772 }; 773 774 ecspi3: spi@30840000 { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 778 reg = <0x30840000 0x10000>; 779 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 781 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 782 clock-names = "ipg", "per"; 783 assigned-clock-rates = <80000000>; 784 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 785 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 786 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 787 dma-names = "rx", "tx"; 788 status = "disabled"; 789 }; 790 791 uart1: serial@30860000 { 792 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 793 reg = <0x30860000 0x10000>; 794 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 796 <&clk IMX8MP_CLK_UART1_ROOT>; 797 clock-names = "ipg", "per"; 798 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 799 dma-names = "rx", "tx"; 800 status = "disabled"; 801 }; 802 803 uart3: serial@30880000 { 804 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 805 reg = <0x30880000 0x10000>; 806 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 808 <&clk IMX8MP_CLK_UART3_ROOT>; 809 clock-names = "ipg", "per"; 810 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 811 dma-names = "rx", "tx"; 812 status = "disabled"; 813 }; 814 815 uart2: serial@30890000 { 816 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 817 reg = <0x30890000 0x10000>; 818 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 820 <&clk IMX8MP_CLK_UART2_ROOT>; 821 clock-names = "ipg", "per"; 822 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 823 dma-names = "rx", "tx"; 824 status = "disabled"; 825 }; 826 827 flexcan1: can@308c0000 { 828 compatible = "fsl,imx8mp-flexcan"; 829 reg = <0x308c0000 0x10000>; 830 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 832 <&clk IMX8MP_CLK_CAN1_ROOT>; 833 clock-names = "ipg", "per"; 834 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 835 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 836 assigned-clock-rates = <40000000>; 837 fsl,clk-source = /bits/ 8 <0>; 838 fsl,stop-mode = <&gpr 0x10 4>; 839 status = "disabled"; 840 }; 841 842 flexcan2: can@308d0000 { 843 compatible = "fsl,imx8mp-flexcan"; 844 reg = <0x308d0000 0x10000>; 845 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 847 <&clk IMX8MP_CLK_CAN2_ROOT>; 848 clock-names = "ipg", "per"; 849 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 850 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 851 assigned-clock-rates = <40000000>; 852 fsl,clk-source = /bits/ 8 <0>; 853 fsl,stop-mode = <&gpr 0x10 5>; 854 status = "disabled"; 855 }; 856 }; 857 858 crypto: crypto@30900000 { 859 compatible = "fsl,sec-v4.0"; 860 #address-cells = <1>; 861 #size-cells = <1>; 862 reg = <0x30900000 0x40000>; 863 ranges = <0 0x30900000 0x40000>; 864 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&clk IMX8MP_CLK_AHB>, 866 <&clk IMX8MP_CLK_IPG_ROOT>; 867 clock-names = "aclk", "ipg"; 868 869 sec_jr0: jr@1000 { 870 compatible = "fsl,sec-v4.0-job-ring"; 871 reg = <0x1000 0x1000>; 872 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 873 status = "disabled"; 874 }; 875 876 sec_jr1: jr@2000 { 877 compatible = "fsl,sec-v4.0-job-ring"; 878 reg = <0x2000 0x1000>; 879 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 880 }; 881 882 sec_jr2: jr@3000 { 883 compatible = "fsl,sec-v4.0-job-ring"; 884 reg = <0x3000 0x1000>; 885 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 886 }; 887 }; 888 889 i2c1: i2c@30a20000 { 890 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 reg = <0x30a20000 0x10000>; 894 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 896 status = "disabled"; 897 }; 898 899 i2c2: i2c@30a30000 { 900 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 reg = <0x30a30000 0x10000>; 904 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 906 status = "disabled"; 907 }; 908 909 i2c3: i2c@30a40000 { 910 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 reg = <0x30a40000 0x10000>; 914 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 916 status = "disabled"; 917 }; 918 919 i2c4: i2c@30a50000 { 920 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 921 #address-cells = <1>; 922 #size-cells = <0>; 923 reg = <0x30a50000 0x10000>; 924 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 926 status = "disabled"; 927 }; 928 929 uart4: serial@30a60000 { 930 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 931 reg = <0x30a60000 0x10000>; 932 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 934 <&clk IMX8MP_CLK_UART4_ROOT>; 935 clock-names = "ipg", "per"; 936 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 937 dma-names = "rx", "tx"; 938 status = "disabled"; 939 }; 940 941 mu: mailbox@30aa0000 { 942 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 943 reg = <0x30aa0000 0x10000>; 944 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 946 #mbox-cells = <2>; 947 }; 948 949 mu2: mailbox@30e60000 { 950 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 951 reg = <0x30e60000 0x10000>; 952 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 953 #mbox-cells = <2>; 954 status = "disabled"; 955 }; 956 957 i2c5: i2c@30ad0000 { 958 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 reg = <0x30ad0000 0x10000>; 962 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 964 status = "disabled"; 965 }; 966 967 i2c6: i2c@30ae0000 { 968 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 reg = <0x30ae0000 0x10000>; 972 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 974 status = "disabled"; 975 }; 976 977 usdhc1: mmc@30b40000 { 978 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 979 reg = <0x30b40000 0x10000>; 980 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&clk IMX8MP_CLK_DUMMY>, 982 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 983 <&clk IMX8MP_CLK_USDHC1_ROOT>; 984 clock-names = "ipg", "ahb", "per"; 985 fsl,tuning-start-tap = <20>; 986 fsl,tuning-step = <2>; 987 bus-width = <4>; 988 status = "disabled"; 989 }; 990 991 usdhc2: mmc@30b50000 { 992 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 993 reg = <0x30b50000 0x10000>; 994 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&clk IMX8MP_CLK_DUMMY>, 996 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 997 <&clk IMX8MP_CLK_USDHC2_ROOT>; 998 clock-names = "ipg", "ahb", "per"; 999 fsl,tuning-start-tap = <20>; 1000 fsl,tuning-step = <2>; 1001 bus-width = <4>; 1002 status = "disabled"; 1003 }; 1004 1005 usdhc3: mmc@30b60000 { 1006 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1007 reg = <0x30b60000 0x10000>; 1008 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&clk IMX8MP_CLK_DUMMY>, 1010 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1011 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1012 clock-names = "ipg", "ahb", "per"; 1013 fsl,tuning-start-tap = <20>; 1014 fsl,tuning-step = <2>; 1015 bus-width = <4>; 1016 status = "disabled"; 1017 }; 1018 1019 flexspi: spi@30bb0000 { 1020 compatible = "nxp,imx8mp-fspi"; 1021 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1022 reg-names = "fspi_base", "fspi_mmap"; 1023 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1025 <&clk IMX8MP_CLK_QSPI_ROOT>; 1026 clock-names = "fspi_en", "fspi"; 1027 assigned-clock-rates = <80000000>; 1028 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 status = "disabled"; 1032 }; 1033 1034 sdma1: dma-controller@30bd0000 { 1035 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1036 reg = <0x30bd0000 0x10000>; 1037 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1039 <&clk IMX8MP_CLK_AHB>; 1040 clock-names = "ipg", "ahb"; 1041 #dma-cells = <3>; 1042 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1043 }; 1044 1045 fec: ethernet@30be0000 { 1046 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1047 reg = <0x30be0000 0x10000>; 1048 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1053 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1054 <&clk IMX8MP_CLK_ENET_TIMER>, 1055 <&clk IMX8MP_CLK_ENET_REF>, 1056 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1057 clock-names = "ipg", "ahb", "ptp", 1058 "enet_clk_ref", "enet_out"; 1059 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1060 <&clk IMX8MP_CLK_ENET_TIMER>, 1061 <&clk IMX8MP_CLK_ENET_REF>, 1062 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1063 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1064 <&clk IMX8MP_SYS_PLL2_100M>, 1065 <&clk IMX8MP_SYS_PLL2_125M>, 1066 <&clk IMX8MP_SYS_PLL2_50M>; 1067 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1068 fsl,num-tx-queues = <3>; 1069 fsl,num-rx-queues = <3>; 1070 nvmem-cells = <ð_mac1>; 1071 nvmem-cell-names = "mac-address"; 1072 fsl,stop-mode = <&gpr 0x10 3>; 1073 status = "disabled"; 1074 }; 1075 1076 eqos: ethernet@30bf0000 { 1077 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1078 reg = <0x30bf0000 0x10000>; 1079 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1081 interrupt-names = "macirq", "eth_wake_irq"; 1082 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1083 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1084 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1085 <&clk IMX8MP_CLK_ENET_QOS>; 1086 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1087 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1088 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1089 <&clk IMX8MP_CLK_ENET_QOS>; 1090 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1091 <&clk IMX8MP_SYS_PLL2_100M>, 1092 <&clk IMX8MP_SYS_PLL2_125M>; 1093 assigned-clock-rates = <0>, <100000000>, <125000000>; 1094 nvmem-cells = <ð_mac2>; 1095 nvmem-cell-names = "mac-address"; 1096 intf_mode = <&gpr 0x4>; 1097 status = "disabled"; 1098 }; 1099 }; 1100 1101 noc: interconnect@32700000 { 1102 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1103 reg = <0x32700000 0x100000>; 1104 clocks = <&clk IMX8MP_CLK_NOC>; 1105 #interconnect-cells = <1>; 1106 operating-points-v2 = <&noc_opp_table>; 1107 1108 noc_opp_table: opp-table { 1109 compatible = "operating-points-v2"; 1110 1111 opp-200000000 { 1112 opp-hz = /bits/ 64 <200000000>; 1113 }; 1114 1115 opp-1000000000 { 1116 opp-hz = /bits/ 64 <1000000000>; 1117 }; 1118 }; 1119 }; 1120 1121 aips4: bus@32c00000 { 1122 compatible = "fsl,aips-bus", "simple-bus"; 1123 reg = <0x32c00000 0x400000>; 1124 #address-cells = <1>; 1125 #size-cells = <1>; 1126 ranges; 1127 1128 lcdif2: display-controller@32e90000 { 1129 compatible = "fsl,imx8mp-lcdif"; 1130 reg = <0x32e90000 0x238>; 1131 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1133 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1134 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1135 clock-names = "pix", "axi", "disp_axi"; 1136 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1137 <&clk IMX8MP_VIDEO_PLL1>; 1138 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, 1139 <&clk IMX8MP_VIDEO_PLL1_REF_SEL>; 1140 assigned-clock-rates = <0>, <1039500000>; 1141 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1142 status = "disabled"; 1143 1144 port { 1145 lcdif2_to_ldb: endpoint { 1146 remote-endpoint = <&ldb_from_lcdif2>; 1147 }; 1148 }; 1149 }; 1150 1151 media_blk_ctrl: blk-ctrl@32ec0000 { 1152 compatible = "fsl,imx8mp-media-blk-ctrl", 1153 "simple-bus", "syscon"; 1154 reg = <0x32ec0000 0x10000>; 1155 #address-cells = <1>; 1156 #size-cells = <1>; 1157 power-domains = <&pgc_mediamix>, 1158 <&pgc_mipi_phy1>, 1159 <&pgc_mipi_phy1>, 1160 <&pgc_mediamix>, 1161 <&pgc_mediamix>, 1162 <&pgc_mipi_phy2>, 1163 <&pgc_mediamix>, 1164 <&pgc_ispdwp>, 1165 <&pgc_ispdwp>, 1166 <&pgc_mipi_phy2>; 1167 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1168 "lcdif1", "isi", "mipi-csi2", 1169 "lcdif2", "isp", "dwe", 1170 "mipi-dsi2"; 1171 interconnects = 1172 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1173 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1174 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1175 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1176 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1177 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1178 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1179 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1180 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1181 "isi1", "isi2", "isp0", "isp1", 1182 "dwe"; 1183 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1184 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1185 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1186 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1187 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1188 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1189 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1190 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1191 clock-names = "apb", "axi", "cam1", "cam2", 1192 "disp1", "disp2", "isp", "phy"; 1193 1194 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1195 <&clk IMX8MP_CLK_MEDIA_APB>; 1196 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1197 <&clk IMX8MP_SYS_PLL1_800M>; 1198 assigned-clock-rates = <500000000>, <200000000>; 1199 1200 #power-domain-cells = <1>; 1201 1202 lvds_bridge: bridge@5c { 1203 compatible = "fsl,imx8mp-ldb"; 1204 clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1205 clock-names = "ldb"; 1206 reg = <0x5c 0x4>, <0x128 0x4>; 1207 reg-names = "ldb", "lvds"; 1208 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1209 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1210 status = "disabled"; 1211 1212 ports { 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 1216 port@0 { 1217 reg = <0>; 1218 1219 ldb_from_lcdif2: endpoint { 1220 remote-endpoint = <&lcdif2_to_ldb>; 1221 }; 1222 }; 1223 1224 port@1 { 1225 reg = <1>; 1226 1227 ldb_lvds_ch0: endpoint { 1228 }; 1229 }; 1230 1231 port@2 { 1232 reg = <2>; 1233 1234 ldb_lvds_ch1: endpoint { 1235 }; 1236 }; 1237 }; 1238 }; 1239 }; 1240 1241 pcie_phy: pcie-phy@32f00000 { 1242 compatible = "fsl,imx8mp-pcie-phy"; 1243 reg = <0x32f00000 0x10000>; 1244 resets = <&src IMX8MP_RESET_PCIEPHY>, 1245 <&src IMX8MP_RESET_PCIEPHY_PERST>; 1246 reset-names = "pciephy", "perst"; 1247 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 1248 #phy-cells = <0>; 1249 status = "disabled"; 1250 }; 1251 1252 hsio_blk_ctrl: blk-ctrl@32f10000 { 1253 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 1254 reg = <0x32f10000 0x24>; 1255 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1256 <&clk IMX8MP_CLK_PCIE_ROOT>; 1257 clock-names = "usb", "pcie"; 1258 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 1259 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 1260 <&pgc_hsiomix>, <&pgc_pcie_phy>; 1261 power-domain-names = "bus", "usb", "usb-phy1", 1262 "usb-phy2", "pcie", "pcie-phy"; 1263 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 1264 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 1265 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 1266 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 1267 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 1268 #power-domain-cells = <1>; 1269 #clock-cells = <0>; 1270 }; 1271 }; 1272 1273 pcie: pcie@33800000 { 1274 compatible = "fsl,imx8mp-pcie"; 1275 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1276 reg-names = "dbi", "config"; 1277 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1278 <&clk IMX8MP_CLK_HSIO_AXI>, 1279 <&clk IMX8MP_CLK_PCIE_ROOT>; 1280 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1281 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 1282 assigned-clock-rates = <10000000>; 1283 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 1284 #address-cells = <3>; 1285 #size-cells = <2>; 1286 device_type = "pci"; 1287 bus-range = <0x00 0xff>; 1288 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1289 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1290 num-lanes = <1>; 1291 num-viewport = <4>; 1292 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1293 interrupt-names = "msi"; 1294 #interrupt-cells = <1>; 1295 interrupt-map-mask = <0 0 0 0x7>; 1296 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1297 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1298 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1299 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1300 fsl,max-link-speed = <3>; 1301 linux,pci-domain = <0>; 1302 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1303 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1304 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1305 reset-names = "apps", "turnoff"; 1306 phys = <&pcie_phy>; 1307 phy-names = "pcie-phy"; 1308 status = "disabled"; 1309 }; 1310 1311 gpu3d: gpu@38000000 { 1312 compatible = "vivante,gc"; 1313 reg = <0x38000000 0x8000>; 1314 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1315 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 1316 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 1317 <&clk IMX8MP_CLK_GPU_ROOT>, 1318 <&clk IMX8MP_CLK_GPU_AHB>; 1319 clock-names = "core", "shader", "bus", "reg"; 1320 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 1321 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 1322 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1323 <&clk IMX8MP_SYS_PLL1_800M>; 1324 assigned-clock-rates = <800000000>, <800000000>; 1325 power-domains = <&pgc_gpu3d>; 1326 }; 1327 1328 gpu2d: gpu@38008000 { 1329 compatible = "vivante,gc"; 1330 reg = <0x38008000 0x8000>; 1331 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 1333 <&clk IMX8MP_CLK_GPU_ROOT>, 1334 <&clk IMX8MP_CLK_GPU_AHB>; 1335 clock-names = "core", "bus", "reg"; 1336 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 1337 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1338 assigned-clock-rates = <800000000>; 1339 power-domains = <&pgc_gpu2d>; 1340 }; 1341 1342 vpu_g1: video-codec@38300000 { 1343 compatible = "nxp,imx8mm-vpu-g1"; 1344 reg = <0x38300000 0x10000>; 1345 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1346 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 1347 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 1348 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 1349 assigned-clock-rates = <600000000>; 1350 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 1351 }; 1352 1353 vpu_g2: video-codec@38310000 { 1354 compatible = "nxp,imx8mq-vpu-g2"; 1355 reg = <0x38310000 0x10000>; 1356 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 1358 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; 1359 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1360 assigned-clock-rates = <500000000>; 1361 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 1362 }; 1363 1364 vpumix_blk_ctrl: blk-ctrl@38330000 { 1365 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 1366 reg = <0x38330000 0x100>; 1367 #power-domain-cells = <1>; 1368 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1369 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 1370 power-domain-names = "bus", "g1", "g2", "vc8000e"; 1371 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 1372 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 1373 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 1374 clock-names = "g1", "g2", "vc8000e"; 1375 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; 1376 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 1377 assigned-clock-rates = <600000000>, <600000000>; 1378 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 1379 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 1380 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 1381 interconnect-names = "g1", "g2", "vc8000e"; 1382 }; 1383 1384 gic: interrupt-controller@38800000 { 1385 compatible = "arm,gic-v3"; 1386 reg = <0x38800000 0x10000>, 1387 <0x38880000 0xc0000>; 1388 #interrupt-cells = <3>; 1389 interrupt-controller; 1390 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1391 interrupt-parent = <&gic>; 1392 }; 1393 1394 edacmc: memory-controller@3d400000 { 1395 compatible = "snps,ddrc-3.80a"; 1396 reg = <0x3d400000 0x400000>; 1397 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1398 }; 1399 1400 ddr-pmu@3d800000 { 1401 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1402 reg = <0x3d800000 0x400000>; 1403 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1404 }; 1405 1406 usb3_phy0: usb-phy@381f0040 { 1407 compatible = "fsl,imx8mp-usb-phy"; 1408 reg = <0x381f0040 0x40>; 1409 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1410 clock-names = "phy"; 1411 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1412 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1413 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 1414 #phy-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 usb3_0: usb@32f10100 { 1419 compatible = "fsl,imx8mp-dwc3"; 1420 reg = <0x32f10100 0x8>, 1421 <0x381f0000 0x20>; 1422 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1423 <&clk IMX8MP_CLK_USB_ROOT>; 1424 clock-names = "hsio", "suspend"; 1425 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1426 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 1427 #address-cells = <1>; 1428 #size-cells = <1>; 1429 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 1430 ranges; 1431 status = "disabled"; 1432 1433 usb_dwc3_0: usb@38100000 { 1434 compatible = "snps,dwc3"; 1435 reg = <0x38100000 0x10000>; 1436 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 1437 <&clk IMX8MP_CLK_USB_CORE_REF>, 1438 <&clk IMX8MP_CLK_USB_ROOT>; 1439 clock-names = "bus_early", "ref", "suspend"; 1440 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1441 phys = <&usb3_phy0>, <&usb3_phy0>; 1442 phy-names = "usb2-phy", "usb3-phy"; 1443 snps,gfladj-refclk-lpm-sel-quirk; 1444 }; 1445 1446 }; 1447 1448 usb3_phy1: usb-phy@382f0040 { 1449 compatible = "fsl,imx8mp-usb-phy"; 1450 reg = <0x382f0040 0x40>; 1451 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1452 clock-names = "phy"; 1453 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1454 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1455 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 1456 #phy-cells = <0>; 1457 status = "disabled"; 1458 }; 1459 1460 usb3_1: usb@32f10108 { 1461 compatible = "fsl,imx8mp-dwc3"; 1462 reg = <0x32f10108 0x8>, 1463 <0x382f0000 0x20>; 1464 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1465 <&clk IMX8MP_CLK_USB_ROOT>; 1466 clock-names = "hsio", "suspend"; 1467 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1468 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 1469 #address-cells = <1>; 1470 #size-cells = <1>; 1471 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 1472 ranges; 1473 status = "disabled"; 1474 1475 usb_dwc3_1: usb@38200000 { 1476 compatible = "snps,dwc3"; 1477 reg = <0x38200000 0x10000>; 1478 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 1479 <&clk IMX8MP_CLK_USB_CORE_REF>, 1480 <&clk IMX8MP_CLK_USB_ROOT>; 1481 clock-names = "bus_early", "ref", "suspend"; 1482 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1483 phys = <&usb3_phy1>, <&usb3_phy1>; 1484 phy-names = "usb2-phy", "usb3-phy"; 1485 snps,gfladj-refclk-lpm-sel-quirk; 1486 }; 1487 }; 1488 1489 dsp: dsp@3b6e8000 { 1490 compatible = "fsl,imx8mp-dsp"; 1491 reg = <0x3b6e8000 0x88000>; 1492 mbox-names = "txdb0", "txdb1", 1493 "rxdb0", "rxdb1"; 1494 mboxes = <&mu2 2 0>, <&mu2 2 1>, 1495 <&mu2 3 0>, <&mu2 3 1>; 1496 memory-region = <&dsp_reserved>; 1497 status = "disabled"; 1498 }; 1499 }; 1500}; 1501