1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 A53_0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&A53_L2>; 64 nvmem-cells = <&cpu_speed_grade>; 65 nvmem-cell-names = "speed_grade"; 66 operating-points-v2 = <&a53_opp_table>; 67 #cooling-cells = <2>; 68 }; 69 70 A53_1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x1>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MP_CLK_ARM>; 76 enable-method = "psci"; 77 i-cache-size = <0x8000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <128>; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A53_2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x2>; 92 clock-latency = <61036>; 93 clocks = <&clk IMX8MP_CLK_ARM>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 }; 105 106 A53_3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x3>; 110 clock-latency = <61036>; 111 clocks = <&clk IMX8MP_CLK_ARM>; 112 enable-method = "psci"; 113 i-cache-size = <0x8000>; 114 i-cache-line-size = <64>; 115 i-cache-sets = <256>; 116 d-cache-size = <0x8000>; 117 d-cache-line-size = <64>; 118 d-cache-sets = <128>; 119 next-level-cache = <&A53_L2>; 120 operating-points-v2 = <&a53_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A53_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-unified; 127 cache-level = <2>; 128 cache-size = <0x80000>; 129 cache-line-size = <64>; 130 cache-sets = <512>; 131 }; 132 }; 133 134 a53_opp_table: opp-table { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-1200000000 { 139 opp-hz = /bits/ 64 <1200000000>; 140 opp-microvolt = <850000>; 141 opp-supported-hw = <0x8a0>, <0x7>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 146 opp-1600000000 { 147 opp-hz = /bits/ 64 <1600000000>; 148 opp-microvolt = <950000>; 149 opp-supported-hw = <0xa0>, <0x7>; 150 clock-latency-ns = <150000>; 151 opp-suspend; 152 }; 153 154 opp-1800000000 { 155 opp-hz = /bits/ 64 <1800000000>; 156 opp-microvolt = <1000000>; 157 opp-supported-hw = <0x20>, <0x3>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 }; 162 163 osc_32k: clock-osc-32k { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <32768>; 167 clock-output-names = "osc_32k"; 168 }; 169 170 osc_24m: clock-osc-24m { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <24000000>; 174 clock-output-names = "osc_24m"; 175 }; 176 177 clk_ext1: clock-ext1 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext1"; 182 }; 183 184 clk_ext2: clock-ext2 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <133000000>; 188 clock-output-names = "clk_ext2"; 189 }; 190 191 clk_ext3: clock-ext3 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext3"; 196 }; 197 198 clk_ext4: clock-ext4 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext4"; 203 }; 204 205 reserved-memory { 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges; 209 210 dsp_reserved: dsp@92400000 { 211 reg = <0 0x92400000 0 0x2000000>; 212 no-map; 213 }; 214 }; 215 216 pmu { 217 compatible = "arm,cortex-a53-pmu"; 218 interrupts = <GIC_PPI 7 219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0"; 224 method = "smc"; 225 }; 226 227 thermal-zones { 228 cpu-thermal { 229 polling-delay-passive = <250>; 230 polling-delay = <2000>; 231 thermal-sensors = <&tmu 0>; 232 trips { 233 cpu_alert0: trip0 { 234 temperature = <85000>; 235 hysteresis = <2000>; 236 type = "passive"; 237 }; 238 239 cpu_crit0: trip1 { 240 temperature = <95000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 }; 245 246 cooling-maps { 247 map0 { 248 trip = <&cpu_alert0>; 249 cooling-device = 250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 254 }; 255 }; 256 }; 257 258 soc-thermal { 259 polling-delay-passive = <250>; 260 polling-delay = <2000>; 261 thermal-sensors = <&tmu 1>; 262 trips { 263 soc_alert0: trip0 { 264 temperature = <85000>; 265 hysteresis = <2000>; 266 type = "passive"; 267 }; 268 269 soc_crit0: trip1 { 270 temperature = <95000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 276 cooling-maps { 277 map0 { 278 trip = <&soc_alert0>; 279 cooling-device = 280 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 281 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 282 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 283 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 284 }; 285 }; 286 }; 287 }; 288 289 timer { 290 compatible = "arm,armv8-timer"; 291 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 293 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 294 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 295 clock-frequency = <8000000>; 296 arm,no-tick-in-suspend; 297 }; 298 299 soc: soc@0 { 300 compatible = "fsl,imx8mp-soc", "simple-bus"; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0x0 0x0 0x0 0x3e000000>; 304 nvmem-cells = <&imx8mp_uid>; 305 nvmem-cell-names = "soc_unique_id"; 306 307 aips1: bus@30000000 { 308 compatible = "fsl,aips-bus", "simple-bus"; 309 reg = <0x30000000 0x400000>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges; 313 314 gpio1: gpio@30200000 { 315 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 316 reg = <0x30200000 0x10000>; 317 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 gpio-ranges = <&iomuxc 0 5 30>; 325 }; 326 327 gpio2: gpio@30210000 { 328 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 329 reg = <0x30210000 0x10000>; 330 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 gpio-ranges = <&iomuxc 0 35 21>; 338 }; 339 340 gpio3: gpio@30220000 { 341 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 342 reg = <0x30220000 0x10000>; 343 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 351 }; 352 353 gpio4: gpio@30230000 { 354 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 355 reg = <0x30230000 0x10000>; 356 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 gpio-ranges = <&iomuxc 0 82 32>; 364 }; 365 366 gpio5: gpio@30240000 { 367 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 368 reg = <0x30240000 0x10000>; 369 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 gpio-ranges = <&iomuxc 0 114 30>; 377 }; 378 379 tmu: tmu@30260000 { 380 compatible = "fsl,imx8mp-tmu"; 381 reg = <0x30260000 0x10000>; 382 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 383 #thermal-sensor-cells = <1>; 384 }; 385 386 wdog1: watchdog@30280000 { 387 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 388 reg = <0x30280000 0x10000>; 389 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 391 status = "disabled"; 392 }; 393 394 wdog2: watchdog@30290000 { 395 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 396 reg = <0x30290000 0x10000>; 397 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 399 status = "disabled"; 400 }; 401 402 wdog3: watchdog@302a0000 { 403 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 404 reg = <0x302a0000 0x10000>; 405 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 407 status = "disabled"; 408 }; 409 410 iomuxc: pinctrl@30330000 { 411 compatible = "fsl,imx8mp-iomuxc"; 412 reg = <0x30330000 0x10000>; 413 }; 414 415 gpr: iomuxc-gpr@30340000 { 416 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 417 reg = <0x30340000 0x10000>; 418 }; 419 420 ocotp: efuse@30350000 { 421 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 422 reg = <0x30350000 0x10000>; 423 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 424 /* For nvmem subnodes */ 425 #address-cells = <1>; 426 #size-cells = <1>; 427 428 imx8mp_uid: unique-id@420 { 429 reg = <0x8 0x8>; 430 }; 431 432 cpu_speed_grade: speed-grade@10 { 433 reg = <0x10 4>; 434 }; 435 436 eth_mac1: mac-address@90 { 437 reg = <0x90 6>; 438 }; 439 440 eth_mac2: mac-address@96 { 441 reg = <0x96 6>; 442 }; 443 }; 444 445 anatop: clock-controller@30360000 { 446 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 447 reg = <0x30360000 0x10000>; 448 #clock-cells = <1>; 449 }; 450 451 snvs: snvs@30370000 { 452 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 453 reg = <0x30370000 0x10000>; 454 455 snvs_rtc: snvs-rtc-lp { 456 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 457 regmap =<&snvs>; 458 offset = <0x34>; 459 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 462 clock-names = "snvs-rtc"; 463 }; 464 465 snvs_pwrkey: snvs-powerkey { 466 compatible = "fsl,sec-v4.0-pwrkey"; 467 regmap = <&snvs>; 468 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 470 clock-names = "snvs-pwrkey"; 471 linux,keycode = <KEY_POWER>; 472 wakeup-source; 473 status = "disabled"; 474 }; 475 476 snvs_lpgpr: snvs-lpgpr { 477 compatible = "fsl,imx8mp-snvs-lpgpr", 478 "fsl,imx7d-snvs-lpgpr"; 479 }; 480 }; 481 482 clk: clock-controller@30380000 { 483 compatible = "fsl,imx8mp-ccm"; 484 reg = <0x30380000 0x10000>; 485 #clock-cells = <1>; 486 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 487 <&clk_ext3>, <&clk_ext4>; 488 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 489 "clk_ext3", "clk_ext4"; 490 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 491 <&clk IMX8MP_CLK_A53_CORE>, 492 <&clk IMX8MP_CLK_NOC>, 493 <&clk IMX8MP_CLK_NOC_IO>, 494 <&clk IMX8MP_CLK_GIC>, 495 <&clk IMX8MP_CLK_AUDIO_AHB>, 496 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, 497 <&clk IMX8MP_AUDIO_PLL1>, 498 <&clk IMX8MP_AUDIO_PLL2>; 499 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 500 <&clk IMX8MP_ARM_PLL_OUT>, 501 <&clk IMX8MP_SYS_PLL2_1000M>, 502 <&clk IMX8MP_SYS_PLL1_800M>, 503 <&clk IMX8MP_SYS_PLL2_500M>, 504 <&clk IMX8MP_SYS_PLL1_800M>, 505 <&clk IMX8MP_SYS_PLL1_800M>; 506 assigned-clock-rates = <0>, <0>, 507 <1000000000>, 508 <800000000>, 509 <500000000>, 510 <400000000>, 511 <800000000>, 512 <393216000>, 513 <361267200>; 514 }; 515 516 src: reset-controller@30390000 { 517 compatible = "fsl,imx8mp-src", "syscon"; 518 reg = <0x30390000 0x10000>; 519 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 520 #reset-cells = <1>; 521 }; 522 523 gpc: gpc@303a0000 { 524 compatible = "fsl,imx8mp-gpc"; 525 reg = <0x303a0000 0x1000>; 526 interrupt-parent = <&gic>; 527 interrupt-controller; 528 #interrupt-cells = <3>; 529 530 pgc { 531 #address-cells = <1>; 532 #size-cells = <0>; 533 534 pgc_mipi_phy1: power-domain@0 { 535 #power-domain-cells = <0>; 536 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 537 }; 538 539 pgc_pcie_phy: power-domain@1 { 540 #power-domain-cells = <0>; 541 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 542 }; 543 544 pgc_usb1_phy: power-domain@2 { 545 #power-domain-cells = <0>; 546 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 547 }; 548 549 pgc_usb2_phy: power-domain@3 { 550 #power-domain-cells = <0>; 551 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 552 }; 553 554 pgc_gpu2d: power-domain@6 { 555 #power-domain-cells = <0>; 556 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 557 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 558 power-domains = <&pgc_gpumix>; 559 }; 560 561 pgc_gpumix: power-domain@7 { 562 #power-domain-cells = <0>; 563 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 564 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 565 <&clk IMX8MP_CLK_GPU_AHB>; 566 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 567 <&clk IMX8MP_CLK_GPU_AHB>; 568 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 569 <&clk IMX8MP_SYS_PLL1_800M>; 570 assigned-clock-rates = <800000000>, <400000000>; 571 }; 572 573 pgc_gpu3d: power-domain@9 { 574 #power-domain-cells = <0>; 575 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 576 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 577 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 578 power-domains = <&pgc_gpumix>; 579 }; 580 581 pgc_mediamix: power-domain@10 { 582 #power-domain-cells = <0>; 583 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 584 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 585 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 586 }; 587 588 pgc_mipi_phy2: power-domain@16 { 589 #power-domain-cells = <0>; 590 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 591 }; 592 593 pgc_hsiomix: power-domains@17 { 594 #power-domain-cells = <0>; 595 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 596 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 597 <&clk IMX8MP_CLK_HSIO_ROOT>; 598 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 599 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 600 assigned-clock-rates = <500000000>; 601 }; 602 603 pgc_ispdwp: power-domain@18 { 604 #power-domain-cells = <0>; 605 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 606 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 607 }; 608 609 pgc_vpumix: power-domain@19 { 610 #power-domain-cells = <0>; 611 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 612 clocks =<&clk IMX8MP_CLK_VPU_ROOT>; 613 }; 614 615 pgc_vpu_g1: power-domain@20 { 616 #power-domain-cells = <0>; 617 power-domains = <&pgc_vpumix>; 618 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 619 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 620 }; 621 622 pgc_vpu_g2: power-domain@21 { 623 #power-domain-cells = <0>; 624 power-domains = <&pgc_vpumix>; 625 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 626 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 627 }; 628 629 pgc_vpu_vc8000e: power-domain@22 { 630 #power-domain-cells = <0>; 631 power-domains = <&pgc_vpumix>; 632 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 633 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 634 }; 635 636 pgc_mlmix: power-domain@24 { 637 #power-domain-cells = <0>; 638 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 639 clocks = <&clk IMX8MP_CLK_ML_AXI>, 640 <&clk IMX8MP_CLK_ML_AHB>, 641 <&clk IMX8MP_CLK_NPU_ROOT>; 642 }; 643 }; 644 }; 645 }; 646 647 aips2: bus@30400000 { 648 compatible = "fsl,aips-bus", "simple-bus"; 649 reg = <0x30400000 0x400000>; 650 #address-cells = <1>; 651 #size-cells = <1>; 652 ranges; 653 654 pwm1: pwm@30660000 { 655 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 656 reg = <0x30660000 0x10000>; 657 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 659 <&clk IMX8MP_CLK_PWM1_ROOT>; 660 clock-names = "ipg", "per"; 661 #pwm-cells = <3>; 662 status = "disabled"; 663 }; 664 665 pwm2: pwm@30670000 { 666 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 667 reg = <0x30670000 0x10000>; 668 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 670 <&clk IMX8MP_CLK_PWM2_ROOT>; 671 clock-names = "ipg", "per"; 672 #pwm-cells = <3>; 673 status = "disabled"; 674 }; 675 676 pwm3: pwm@30680000 { 677 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 678 reg = <0x30680000 0x10000>; 679 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 681 <&clk IMX8MP_CLK_PWM3_ROOT>; 682 clock-names = "ipg", "per"; 683 #pwm-cells = <3>; 684 status = "disabled"; 685 }; 686 687 pwm4: pwm@30690000 { 688 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 689 reg = <0x30690000 0x10000>; 690 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 692 <&clk IMX8MP_CLK_PWM4_ROOT>; 693 clock-names = "ipg", "per"; 694 #pwm-cells = <3>; 695 status = "disabled"; 696 }; 697 698 system_counter: timer@306a0000 { 699 compatible = "nxp,sysctr-timer"; 700 reg = <0x306a0000 0x20000>; 701 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&osc_24m>; 703 clock-names = "per"; 704 }; 705 }; 706 707 aips3: bus@30800000 { 708 compatible = "fsl,aips-bus", "simple-bus"; 709 reg = <0x30800000 0x400000>; 710 #address-cells = <1>; 711 #size-cells = <1>; 712 ranges; 713 714 ecspi1: spi@30820000 { 715 #address-cells = <1>; 716 #size-cells = <0>; 717 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 718 reg = <0x30820000 0x10000>; 719 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 721 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 722 clock-names = "ipg", "per"; 723 assigned-clock-rates = <80000000>; 724 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 725 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 726 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 727 dma-names = "rx", "tx"; 728 status = "disabled"; 729 }; 730 731 ecspi2: spi@30830000 { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 735 reg = <0x30830000 0x10000>; 736 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 738 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 739 clock-names = "ipg", "per"; 740 assigned-clock-rates = <80000000>; 741 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 743 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 744 dma-names = "rx", "tx"; 745 status = "disabled"; 746 }; 747 748 ecspi3: spi@30840000 { 749 #address-cells = <1>; 750 #size-cells = <0>; 751 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 752 reg = <0x30840000 0x10000>; 753 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 755 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 756 clock-names = "ipg", "per"; 757 assigned-clock-rates = <80000000>; 758 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 759 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 760 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 761 dma-names = "rx", "tx"; 762 status = "disabled"; 763 }; 764 765 uart1: serial@30860000 { 766 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 767 reg = <0x30860000 0x10000>; 768 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 770 <&clk IMX8MP_CLK_UART1_ROOT>; 771 clock-names = "ipg", "per"; 772 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 773 dma-names = "rx", "tx"; 774 status = "disabled"; 775 }; 776 777 uart3: serial@30880000 { 778 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 779 reg = <0x30880000 0x10000>; 780 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 782 <&clk IMX8MP_CLK_UART3_ROOT>; 783 clock-names = "ipg", "per"; 784 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 785 dma-names = "rx", "tx"; 786 status = "disabled"; 787 }; 788 789 uart2: serial@30890000 { 790 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 791 reg = <0x30890000 0x10000>; 792 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 794 <&clk IMX8MP_CLK_UART2_ROOT>; 795 clock-names = "ipg", "per"; 796 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 797 dma-names = "rx", "tx"; 798 status = "disabled"; 799 }; 800 801 flexcan1: can@308c0000 { 802 compatible = "fsl,imx8mp-flexcan"; 803 reg = <0x308c0000 0x10000>; 804 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 806 <&clk IMX8MP_CLK_CAN1_ROOT>; 807 clock-names = "ipg", "per"; 808 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 809 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 810 assigned-clock-rates = <40000000>; 811 fsl,clk-source = /bits/ 8 <0>; 812 fsl,stop-mode = <&gpr 0x10 4>; 813 status = "disabled"; 814 }; 815 816 flexcan2: can@308d0000 { 817 compatible = "fsl,imx8mp-flexcan"; 818 reg = <0x308d0000 0x10000>; 819 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 821 <&clk IMX8MP_CLK_CAN2_ROOT>; 822 clock-names = "ipg", "per"; 823 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 824 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 825 assigned-clock-rates = <40000000>; 826 fsl,clk-source = /bits/ 8 <0>; 827 fsl,stop-mode = <&gpr 0x10 5>; 828 status = "disabled"; 829 }; 830 831 crypto: crypto@30900000 { 832 compatible = "fsl,sec-v4.0"; 833 #address-cells = <1>; 834 #size-cells = <1>; 835 reg = <0x30900000 0x40000>; 836 ranges = <0 0x30900000 0x40000>; 837 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&clk IMX8MP_CLK_AHB>, 839 <&clk IMX8MP_CLK_IPG_ROOT>; 840 clock-names = "aclk", "ipg"; 841 842 sec_jr0: jr@1000 { 843 compatible = "fsl,sec-v4.0-job-ring"; 844 reg = <0x1000 0x1000>; 845 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 846 status = "disabled"; 847 }; 848 849 sec_jr1: jr@2000 { 850 compatible = "fsl,sec-v4.0-job-ring"; 851 reg = <0x2000 0x1000>; 852 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 853 }; 854 855 sec_jr2: jr@3000 { 856 compatible = "fsl,sec-v4.0-job-ring"; 857 reg = <0x3000 0x1000>; 858 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 859 }; 860 }; 861 862 i2c1: i2c@30a20000 { 863 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 reg = <0x30a20000 0x10000>; 867 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 869 status = "disabled"; 870 }; 871 872 i2c2: i2c@30a30000 { 873 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 reg = <0x30a30000 0x10000>; 877 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 879 status = "disabled"; 880 }; 881 882 i2c3: i2c@30a40000 { 883 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 reg = <0x30a40000 0x10000>; 887 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 889 status = "disabled"; 890 }; 891 892 i2c4: i2c@30a50000 { 893 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 reg = <0x30a50000 0x10000>; 897 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 899 status = "disabled"; 900 }; 901 902 uart4: serial@30a60000 { 903 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 904 reg = <0x30a60000 0x10000>; 905 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 907 <&clk IMX8MP_CLK_UART4_ROOT>; 908 clock-names = "ipg", "per"; 909 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 910 dma-names = "rx", "tx"; 911 status = "disabled"; 912 }; 913 914 mu: mailbox@30aa0000 { 915 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 916 reg = <0x30aa0000 0x10000>; 917 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 919 #mbox-cells = <2>; 920 }; 921 922 mu2: mailbox@30e60000 { 923 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 924 reg = <0x30e60000 0x10000>; 925 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 926 #mbox-cells = <2>; 927 status = "disabled"; 928 }; 929 930 i2c5: i2c@30ad0000 { 931 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 reg = <0x30ad0000 0x10000>; 935 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 937 status = "disabled"; 938 }; 939 940 i2c6: i2c@30ae0000 { 941 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 reg = <0x30ae0000 0x10000>; 945 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 947 status = "disabled"; 948 }; 949 950 usdhc1: mmc@30b40000 { 951 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 952 reg = <0x30b40000 0x10000>; 953 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 954 clocks = <&clk IMX8MP_CLK_DUMMY>, 955 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 956 <&clk IMX8MP_CLK_USDHC1_ROOT>; 957 clock-names = "ipg", "ahb", "per"; 958 fsl,tuning-start-tap = <20>; 959 fsl,tuning-step = <2>; 960 bus-width = <4>; 961 status = "disabled"; 962 }; 963 964 usdhc2: mmc@30b50000 { 965 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 966 reg = <0x30b50000 0x10000>; 967 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&clk IMX8MP_CLK_DUMMY>, 969 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 970 <&clk IMX8MP_CLK_USDHC2_ROOT>; 971 clock-names = "ipg", "ahb", "per"; 972 fsl,tuning-start-tap = <20>; 973 fsl,tuning-step = <2>; 974 bus-width = <4>; 975 status = "disabled"; 976 }; 977 978 usdhc3: mmc@30b60000 { 979 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 980 reg = <0x30b60000 0x10000>; 981 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clk IMX8MP_CLK_DUMMY>, 983 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 984 <&clk IMX8MP_CLK_USDHC3_ROOT>; 985 clock-names = "ipg", "ahb", "per"; 986 fsl,tuning-start-tap = <20>; 987 fsl,tuning-step = <2>; 988 bus-width = <4>; 989 status = "disabled"; 990 }; 991 992 flexspi: spi@30bb0000 { 993 compatible = "nxp,imx8mp-fspi"; 994 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 995 reg-names = "fspi_base", "fspi_mmap"; 996 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 998 <&clk IMX8MP_CLK_QSPI_ROOT>; 999 clock-names = "fspi_en", "fspi"; 1000 assigned-clock-rates = <80000000>; 1001 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 status = "disabled"; 1005 }; 1006 1007 sdma1: dma-controller@30bd0000 { 1008 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1009 reg = <0x30bd0000 0x10000>; 1010 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1012 <&clk IMX8MP_CLK_AHB>; 1013 clock-names = "ipg", "ahb"; 1014 #dma-cells = <3>; 1015 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1016 }; 1017 1018 fec: ethernet@30be0000 { 1019 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1020 reg = <0x30be0000 0x10000>; 1021 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1026 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1027 <&clk IMX8MP_CLK_ENET_TIMER>, 1028 <&clk IMX8MP_CLK_ENET_REF>, 1029 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1030 clock-names = "ipg", "ahb", "ptp", 1031 "enet_clk_ref", "enet_out"; 1032 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1033 <&clk IMX8MP_CLK_ENET_TIMER>, 1034 <&clk IMX8MP_CLK_ENET_REF>, 1035 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1036 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1037 <&clk IMX8MP_SYS_PLL2_100M>, 1038 <&clk IMX8MP_SYS_PLL2_125M>, 1039 <&clk IMX8MP_SYS_PLL2_50M>; 1040 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1041 fsl,num-tx-queues = <3>; 1042 fsl,num-rx-queues = <3>; 1043 nvmem-cells = <ð_mac1>; 1044 nvmem-cell-names = "mac-address"; 1045 fsl,stop-mode = <&gpr 0x10 3>; 1046 status = "disabled"; 1047 }; 1048 1049 eqos: ethernet@30bf0000 { 1050 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1051 reg = <0x30bf0000 0x10000>; 1052 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1054 interrupt-names = "macirq", "eth_wake_irq"; 1055 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1056 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1057 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1058 <&clk IMX8MP_CLK_ENET_QOS>; 1059 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1060 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1061 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1062 <&clk IMX8MP_CLK_ENET_QOS>; 1063 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1064 <&clk IMX8MP_SYS_PLL2_100M>, 1065 <&clk IMX8MP_SYS_PLL2_125M>; 1066 assigned-clock-rates = <0>, <100000000>, <125000000>; 1067 nvmem-cells = <ð_mac2>; 1068 nvmem-cell-names = "mac-address"; 1069 intf_mode = <&gpr 0x4>; 1070 status = "disabled"; 1071 }; 1072 }; 1073 1074 noc: interconnect@32700000 { 1075 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1076 reg = <0x32700000 0x100000>; 1077 clocks = <&clk IMX8MP_CLK_NOC>; 1078 #interconnect-cells = <1>; 1079 operating-points-v2 = <&noc_opp_table>; 1080 1081 noc_opp_table: opp-table { 1082 compatible = "operating-points-v2"; 1083 1084 opp-200000000 { 1085 opp-hz = /bits/ 64 <200000000>; 1086 }; 1087 1088 opp-1000000000 { 1089 opp-hz = /bits/ 64 <1000000000>; 1090 }; 1091 }; 1092 }; 1093 1094 aips4: bus@32c00000 { 1095 compatible = "fsl,aips-bus", "simple-bus"; 1096 reg = <0x32c00000 0x400000>; 1097 #address-cells = <1>; 1098 #size-cells = <1>; 1099 ranges; 1100 1101 media_blk_ctrl: blk-ctrl@32ec0000 { 1102 compatible = "fsl,imx8mp-media-blk-ctrl", 1103 "syscon"; 1104 reg = <0x32ec0000 0x10000>; 1105 power-domains = <&pgc_mediamix>, 1106 <&pgc_mipi_phy1>, 1107 <&pgc_mipi_phy1>, 1108 <&pgc_mediamix>, 1109 <&pgc_mediamix>, 1110 <&pgc_mipi_phy2>, 1111 <&pgc_mediamix>, 1112 <&pgc_ispdwp>, 1113 <&pgc_ispdwp>, 1114 <&pgc_mipi_phy2>; 1115 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1116 "lcdif1", "isi", "mipi-csi2", 1117 "lcdif2", "isp", "dwe", 1118 "mipi-dsi2"; 1119 interconnects = 1120 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1121 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1122 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1123 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1124 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1125 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1126 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1127 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1128 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1129 "isi1", "isi2", "isp0", "isp1", 1130 "dwe"; 1131 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1132 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1133 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1134 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1135 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1136 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1137 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1138 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1139 clock-names = "apb", "axi", "cam1", "cam2", 1140 "disp1", "disp2", "isp", "phy"; 1141 1142 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1143 <&clk IMX8MP_CLK_MEDIA_APB>; 1144 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1145 <&clk IMX8MP_SYS_PLL1_800M>; 1146 assigned-clock-rates = <500000000>, <200000000>; 1147 1148 #power-domain-cells = <1>; 1149 }; 1150 1151 pcie_phy: pcie-phy@32f00000 { 1152 compatible = "fsl,imx8mp-pcie-phy"; 1153 reg = <0x32f00000 0x10000>; 1154 resets = <&src IMX8MP_RESET_PCIEPHY>, 1155 <&src IMX8MP_RESET_PCIEPHY_PERST>; 1156 reset-names = "pciephy", "perst"; 1157 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 1158 #phy-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 hsio_blk_ctrl: blk-ctrl@32f10000 { 1163 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 1164 reg = <0x32f10000 0x24>; 1165 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1166 <&clk IMX8MP_CLK_PCIE_ROOT>; 1167 clock-names = "usb", "pcie"; 1168 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 1169 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 1170 <&pgc_hsiomix>, <&pgc_pcie_phy>; 1171 power-domain-names = "bus", "usb", "usb-phy1", 1172 "usb-phy2", "pcie", "pcie-phy"; 1173 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 1174 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 1175 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 1176 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 1177 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 1178 #power-domain-cells = <1>; 1179 }; 1180 }; 1181 1182 pcie: pcie@33800000 { 1183 compatible = "fsl,imx8mp-pcie"; 1184 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1185 reg-names = "dbi", "config"; 1186 #address-cells = <3>; 1187 #size-cells = <2>; 1188 device_type = "pci"; 1189 bus-range = <0x00 0xff>; 1190 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1191 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1192 num-lanes = <1>; 1193 num-viewport = <4>; 1194 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1195 interrupt-names = "msi"; 1196 #interrupt-cells = <1>; 1197 interrupt-map-mask = <0 0 0 0x7>; 1198 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1199 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1200 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1201 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1202 fsl,max-link-speed = <3>; 1203 linux,pci-domain = <0>; 1204 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1205 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1206 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1207 reset-names = "apps", "turnoff"; 1208 phys = <&pcie_phy>; 1209 phy-names = "pcie-phy"; 1210 status = "disabled"; 1211 }; 1212 1213 gpu3d: gpu@38000000 { 1214 compatible = "vivante,gc"; 1215 reg = <0x38000000 0x8000>; 1216 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1217 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 1218 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 1219 <&clk IMX8MP_CLK_GPU_ROOT>, 1220 <&clk IMX8MP_CLK_GPU_AHB>; 1221 clock-names = "core", "shader", "bus", "reg"; 1222 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 1223 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 1224 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1225 <&clk IMX8MP_SYS_PLL1_800M>; 1226 assigned-clock-rates = <800000000>, <800000000>; 1227 power-domains = <&pgc_gpu3d>; 1228 }; 1229 1230 gpu2d: gpu@38008000 { 1231 compatible = "vivante,gc"; 1232 reg = <0x38008000 0x8000>; 1233 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 1235 <&clk IMX8MP_CLK_GPU_ROOT>, 1236 <&clk IMX8MP_CLK_GPU_AHB>; 1237 clock-names = "core", "bus", "reg"; 1238 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 1239 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1240 assigned-clock-rates = <800000000>; 1241 power-domains = <&pgc_gpu2d>; 1242 }; 1243 1244 vpumix_blk_ctrl: blk-ctrl@38330000 { 1245 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 1246 reg = <0x38330000 0x100>; 1247 #power-domain-cells = <1>; 1248 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1249 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 1250 power-domain-names = "bus", "g1", "g2", "vc8000e"; 1251 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 1252 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 1253 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 1254 clock-names = "g1", "g2", "vc8000e"; 1255 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 1256 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 1257 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 1258 interconnect-names = "g1", "g2", "vc8000e"; 1259 }; 1260 1261 gic: interrupt-controller@38800000 { 1262 compatible = "arm,gic-v3"; 1263 reg = <0x38800000 0x10000>, 1264 <0x38880000 0xc0000>; 1265 #interrupt-cells = <3>; 1266 interrupt-controller; 1267 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1268 interrupt-parent = <&gic>; 1269 }; 1270 1271 edacmc: memory-controller@3d400000 { 1272 compatible = "snps,ddrc-3.80a"; 1273 reg = <0x3d400000 0x400000>; 1274 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1275 }; 1276 1277 ddr-pmu@3d800000 { 1278 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1279 reg = <0x3d800000 0x400000>; 1280 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1281 }; 1282 1283 usb3_phy0: usb-phy@381f0040 { 1284 compatible = "fsl,imx8mp-usb-phy"; 1285 reg = <0x381f0040 0x40>; 1286 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1287 clock-names = "phy"; 1288 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1289 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1290 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 1291 #phy-cells = <0>; 1292 status = "disabled"; 1293 }; 1294 1295 usb3_0: usb@32f10100 { 1296 compatible = "fsl,imx8mp-dwc3"; 1297 reg = <0x32f10100 0x8>, 1298 <0x381f0000 0x20>; 1299 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1300 <&clk IMX8MP_CLK_USB_ROOT>; 1301 clock-names = "hsio", "suspend"; 1302 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1303 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 1304 #address-cells = <1>; 1305 #size-cells = <1>; 1306 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 1307 ranges; 1308 status = "disabled"; 1309 1310 usb_dwc3_0: usb@38100000 { 1311 compatible = "snps,dwc3"; 1312 reg = <0x38100000 0x10000>; 1313 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 1314 <&clk IMX8MP_CLK_USB_CORE_REF>, 1315 <&clk IMX8MP_CLK_USB_ROOT>; 1316 clock-names = "bus_early", "ref", "suspend"; 1317 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1318 phys = <&usb3_phy0>, <&usb3_phy0>; 1319 phy-names = "usb2-phy", "usb3-phy"; 1320 snps,gfladj-refclk-lpm-sel-quirk; 1321 }; 1322 1323 }; 1324 1325 usb3_phy1: usb-phy@382f0040 { 1326 compatible = "fsl,imx8mp-usb-phy"; 1327 reg = <0x382f0040 0x40>; 1328 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1329 clock-names = "phy"; 1330 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1331 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1332 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 1333 #phy-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 usb3_1: usb@32f10108 { 1338 compatible = "fsl,imx8mp-dwc3"; 1339 reg = <0x32f10108 0x8>, 1340 <0x382f0000 0x20>; 1341 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1342 <&clk IMX8MP_CLK_USB_ROOT>; 1343 clock-names = "hsio", "suspend"; 1344 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 1346 #address-cells = <1>; 1347 #size-cells = <1>; 1348 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 1349 ranges; 1350 status = "disabled"; 1351 1352 usb_dwc3_1: usb@38200000 { 1353 compatible = "snps,dwc3"; 1354 reg = <0x38200000 0x10000>; 1355 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 1356 <&clk IMX8MP_CLK_USB_CORE_REF>, 1357 <&clk IMX8MP_CLK_USB_ROOT>; 1358 clock-names = "bus_early", "ref", "suspend"; 1359 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1360 phys = <&usb3_phy1>, <&usb3_phy1>; 1361 phy-names = "usb2-phy", "usb3-phy"; 1362 snps,gfladj-refclk-lpm-sel-quirk; 1363 }; 1364 }; 1365 1366 dsp: dsp@3b6e8000 { 1367 compatible = "fsl,imx8mp-dsp"; 1368 reg = <0x3b6e8000 0x88000>; 1369 mbox-names = "txdb0", "txdb1", 1370 "rxdb0", "rxdb1"; 1371 mboxes = <&mu2 2 0>, <&mu2 2 1>, 1372 <&mu2 3 0>, <&mu2 3 1>; 1373 memory-region = <&dsp_reserved>; 1374 status = "disabled"; 1375 }; 1376 }; 1377}; 1378