1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mp-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 mmc0 = &usdhc1; 27 mmc1 = &usdhc2; 28 mmc2 = &usdhc3; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 A53_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x0>; 43 clock-latency = <61036>; 44 clocks = <&clk IMX8MP_CLK_ARM>; 45 enable-method = "psci"; 46 next-level-cache = <&A53_L2>; 47 #cooling-cells = <2>; 48 }; 49 50 A53_1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x1>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 next-level-cache = <&A53_L2>; 58 #cooling-cells = <2>; 59 }; 60 61 A53_2: cpu@2 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x2>; 65 clock-latency = <61036>; 66 clocks = <&clk IMX8MP_CLK_ARM>; 67 enable-method = "psci"; 68 next-level-cache = <&A53_L2>; 69 #cooling-cells = <2>; 70 }; 71 72 A53_3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x3>; 76 clock-latency = <61036>; 77 clocks = <&clk IMX8MP_CLK_ARM>; 78 enable-method = "psci"; 79 next-level-cache = <&A53_L2>; 80 #cooling-cells = <2>; 81 }; 82 83 A53_L2: l2-cache0 { 84 compatible = "cache"; 85 }; 86 }; 87 88 osc_32k: clock-osc-32k { 89 compatible = "fixed-clock"; 90 #clock-cells = <0>; 91 clock-frequency = <32768>; 92 clock-output-names = "osc_32k"; 93 }; 94 95 osc_24m: clock-osc-24m { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <24000000>; 99 clock-output-names = "osc_24m"; 100 }; 101 102 clk_ext1: clock-ext1 { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <133000000>; 106 clock-output-names = "clk_ext1"; 107 }; 108 109 clk_ext2: clock-ext2 { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <133000000>; 113 clock-output-names = "clk_ext2"; 114 }; 115 116 clk_ext3: clock-ext3 { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-frequency = <133000000>; 120 clock-output-names = "clk_ext3"; 121 }; 122 123 clk_ext4: clock-ext4 { 124 compatible = "fixed-clock"; 125 #clock-cells = <0>; 126 clock-frequency= <133000000>; 127 clock-output-names = "clk_ext4"; 128 }; 129 130 psci { 131 compatible = "arm,psci-1.0"; 132 method = "smc"; 133 }; 134 135 thermal-zones { 136 cpu-thermal { 137 polling-delay-passive = <250>; 138 polling-delay = <2000>; 139 thermal-sensors = <&tmu 0>; 140 trips { 141 cpu_alert0: trip0 { 142 temperature = <85000>; 143 hysteresis = <2000>; 144 type = "passive"; 145 }; 146 147 cpu_crit0: trip1 { 148 temperature = <95000>; 149 hysteresis = <2000>; 150 type = "critical"; 151 }; 152 }; 153 154 cooling-maps { 155 map0 { 156 trip = <&cpu_alert0>; 157 cooling-device = 158 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 159 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 160 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 161 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 162 }; 163 }; 164 }; 165 166 soc-thermal { 167 polling-delay-passive = <250>; 168 polling-delay = <2000>; 169 thermal-sensors = <&tmu 1>; 170 trips { 171 soc_alert0: trip0 { 172 temperature = <85000>; 173 hysteresis = <2000>; 174 type = "passive"; 175 }; 176 177 soc_crit0: trip1 { 178 temperature = <95000>; 179 hysteresis = <2000>; 180 type = "critical"; 181 }; 182 }; 183 184 cooling-maps { 185 map0 { 186 trip = <&soc_alert0>; 187 cooling-device = 188 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 189 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 190 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 191 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 192 }; 193 }; 194 }; 195 }; 196 197 timer { 198 compatible = "arm,armv8-timer"; 199 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 200 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 201 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 202 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 203 clock-frequency = <8000000>; 204 arm,no-tick-in-suspend; 205 }; 206 207 soc@0 { 208 compatible = "simple-bus"; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges = <0x0 0x0 0x0 0x3e000000>; 212 213 aips1: bus@30000000 { 214 compatible = "fsl,aips-bus", "simple-bus"; 215 reg = <0x30000000 0x400000>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 220 gpio1: gpio@30200000 { 221 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 222 reg = <0x30200000 0x10000>; 223 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 226 gpio-controller; 227 #gpio-cells = <2>; 228 interrupt-controller; 229 #interrupt-cells = <2>; 230 gpio-ranges = <&iomuxc 0 5 30>; 231 }; 232 233 gpio2: gpio@30210000 { 234 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 235 reg = <0x30210000 0x10000>; 236 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 239 gpio-controller; 240 #gpio-cells = <2>; 241 interrupt-controller; 242 #interrupt-cells = <2>; 243 gpio-ranges = <&iomuxc 0 35 21>; 244 }; 245 246 gpio3: gpio@30220000 { 247 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 248 reg = <0x30220000 0x10000>; 249 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 252 gpio-controller; 253 #gpio-cells = <2>; 254 interrupt-controller; 255 #interrupt-cells = <2>; 256 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>; 257 }; 258 259 gpio4: gpio@30230000 { 260 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 261 reg = <0x30230000 0x10000>; 262 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 265 gpio-controller; 266 #gpio-cells = <2>; 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 gpio-ranges = <&iomuxc 0 82 32>; 270 }; 271 272 gpio5: gpio@30240000 { 273 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 274 reg = <0x30240000 0x10000>; 275 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 278 gpio-controller; 279 #gpio-cells = <2>; 280 interrupt-controller; 281 #interrupt-cells = <2>; 282 gpio-ranges = <&iomuxc 0 114 30>; 283 }; 284 285 tmu: tmu@30260000 { 286 compatible = "fsl,imx8mp-tmu"; 287 reg = <0x30260000 0x10000>; 288 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 289 #thermal-sensor-cells = <1>; 290 }; 291 292 wdog1: watchdog@30280000 { 293 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 294 reg = <0x30280000 0x10000>; 295 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 297 status = "disabled"; 298 }; 299 300 iomuxc: pinctrl@30330000 { 301 compatible = "fsl,imx8mp-iomuxc"; 302 reg = <0x30330000 0x10000>; 303 }; 304 305 gpr: iomuxc-gpr@30340000 { 306 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 307 reg = <0x30340000 0x10000>; 308 }; 309 310 ocotp: ocotp-ctrl@30350000 { 311 compatible = "fsl,imx8mp-ocotp", "syscon"; 312 reg = <0x30350000 0x10000>; 313 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 314 /* For nvmem subnodes */ 315 #address-cells = <1>; 316 #size-cells = <1>; 317 318 cpu_speed_grade: speed-grade@10 { 319 reg = <0x10 4>; 320 }; 321 }; 322 323 anatop: anatop@30360000 { 324 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", 325 "syscon"; 326 reg = <0x30360000 0x10000>; 327 }; 328 329 snvs: snvs@30370000 { 330 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 331 reg = <0x30370000 0x10000>; 332 333 snvs_rtc: snvs-rtc-lp { 334 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 335 regmap =<&snvs>; 336 offset = <0x34>; 337 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 340 clock-names = "snvs-rtc"; 341 }; 342 343 snvs_pwrkey: snvs-powerkey { 344 compatible = "fsl,sec-v4.0-pwrkey"; 345 regmap = <&snvs>; 346 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 348 clock-names = "snvs-pwrkey"; 349 linux,keycode = <KEY_POWER>; 350 wakeup-source; 351 status = "disabled"; 352 }; 353 }; 354 355 clk: clock-controller@30380000 { 356 compatible = "fsl,imx8mp-ccm"; 357 reg = <0x30380000 0x10000>; 358 #clock-cells = <1>; 359 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 360 <&clk_ext3>, <&clk_ext4>; 361 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 362 "clk_ext3", "clk_ext4"; 363 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 364 <&clk IMX8MP_CLK_A53_CORE>, 365 <&clk IMX8MP_CLK_NOC>, 366 <&clk IMX8MP_CLK_NOC_IO>, 367 <&clk IMX8MP_CLK_GIC>, 368 <&clk IMX8MP_CLK_AUDIO_AHB>, 369 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, 370 <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, 371 <&clk IMX8MP_AUDIO_PLL1>, 372 <&clk IMX8MP_AUDIO_PLL2>; 373 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 374 <&clk IMX8MP_ARM_PLL_OUT>, 375 <&clk IMX8MP_SYS_PLL2_1000M>, 376 <&clk IMX8MP_SYS_PLL1_800M>, 377 <&clk IMX8MP_SYS_PLL2_500M>, 378 <&clk IMX8MP_SYS_PLL1_800M>, 379 <&clk IMX8MP_SYS_PLL1_800M>; 380 assigned-clock-rates = <0>, <0>, 381 <1000000000>, 382 <800000000>, 383 <500000000>, 384 <400000000>, 385 <800000000>, 386 <400000000>, 387 <393216000>, 388 <361267200>; 389 }; 390 391 src: reset-controller@30390000 { 392 compatible = "fsl,imx8mp-src", "syscon"; 393 reg = <0x30390000 0x10000>; 394 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 395 #reset-cells = <1>; 396 }; 397 }; 398 399 aips2: bus@30400000 { 400 compatible = "fsl,aips-bus", "simple-bus"; 401 reg = <0x30400000 0x400000>; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 ranges; 405 406 pwm1: pwm@30660000 { 407 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 408 reg = <0x30660000 0x10000>; 409 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 411 <&clk IMX8MP_CLK_PWM1_ROOT>; 412 clock-names = "ipg", "per"; 413 #pwm-cells = <2>; 414 status = "disabled"; 415 }; 416 417 pwm2: pwm@30670000 { 418 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 419 reg = <0x30670000 0x10000>; 420 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 422 <&clk IMX8MP_CLK_PWM2_ROOT>; 423 clock-names = "ipg", "per"; 424 #pwm-cells = <2>; 425 status = "disabled"; 426 }; 427 428 pwm3: pwm@30680000 { 429 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 430 reg = <0x30680000 0x10000>; 431 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 433 <&clk IMX8MP_CLK_PWM3_ROOT>; 434 clock-names = "ipg", "per"; 435 #pwm-cells = <2>; 436 status = "disabled"; 437 }; 438 439 pwm4: pwm@30690000 { 440 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 441 reg = <0x30690000 0x10000>; 442 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 444 <&clk IMX8MP_CLK_PWM4_ROOT>; 445 clock-names = "ipg", "per"; 446 #pwm-cells = <2>; 447 status = "disabled"; 448 }; 449 450 system_counter: timer@306a0000 { 451 compatible = "nxp,sysctr-timer"; 452 reg = <0x306a0000 0x20000>; 453 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&osc_24m>; 455 clock-names = "per"; 456 }; 457 }; 458 459 aips3: bus@30800000 { 460 compatible = "fsl,aips-bus", "simple-bus"; 461 reg = <0x30800000 0x400000>; 462 #address-cells = <1>; 463 #size-cells = <1>; 464 ranges; 465 466 ecspi1: spi@30820000 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 470 reg = <0x30820000 0x10000>; 471 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 473 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 474 clock-names = "ipg", "per"; 475 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 476 dma-names = "rx", "tx"; 477 status = "disabled"; 478 }; 479 480 ecspi2: spi@30830000 { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 484 reg = <0x30830000 0x10000>; 485 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 487 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 488 clock-names = "ipg", "per"; 489 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 490 dma-names = "rx", "tx"; 491 status = "disabled"; 492 }; 493 494 ecspi3: spi@30840000 { 495 #address-cells = <1>; 496 #size-cells = <0>; 497 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 498 reg = <0x30840000 0x10000>; 499 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 501 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 502 clock-names = "ipg", "per"; 503 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 504 dma-names = "rx", "tx"; 505 status = "disabled"; 506 }; 507 508 uart1: serial@30860000 { 509 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 510 reg = <0x30860000 0x10000>; 511 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 513 <&clk IMX8MP_CLK_UART1_ROOT>; 514 clock-names = "ipg", "per"; 515 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 516 dma-names = "rx", "tx"; 517 status = "disabled"; 518 }; 519 520 uart3: serial@30880000 { 521 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 522 reg = <0x30880000 0x10000>; 523 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 525 <&clk IMX8MP_CLK_UART3_ROOT>; 526 clock-names = "ipg", "per"; 527 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 528 dma-names = "rx", "tx"; 529 status = "disabled"; 530 }; 531 532 uart2: serial@30890000 { 533 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 534 reg = <0x30890000 0x10000>; 535 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 537 <&clk IMX8MP_CLK_UART2_ROOT>; 538 clock-names = "ipg", "per"; 539 status = "disabled"; 540 }; 541 542 crypto: crypto@30900000 { 543 compatible = "fsl,sec-v4.0"; 544 #address-cells = <1>; 545 #size-cells = <1>; 546 reg = <0x30900000 0x40000>; 547 ranges = <0 0x30900000 0x40000>; 548 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clk IMX8MP_CLK_AHB>, 550 <&clk IMX8MP_CLK_IPG_ROOT>; 551 clock-names = "aclk", "ipg"; 552 553 sec_jr0: jr@1000 { 554 compatible = "fsl,sec-v4.0-job-ring"; 555 reg = <0x1000 0x1000>; 556 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 557 }; 558 559 sec_jr1: jr@2000 { 560 compatible = "fsl,sec-v4.0-job-ring"; 561 reg = <0x2000 0x1000>; 562 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 563 }; 564 565 sec_jr2: jr@3000 { 566 compatible = "fsl,sec-v4.0-job-ring"; 567 reg = <0x3000 0x1000>; 568 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 569 }; 570 }; 571 572 i2c1: i2c@30a20000 { 573 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 reg = <0x30a20000 0x10000>; 577 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 579 status = "disabled"; 580 }; 581 582 i2c2: i2c@30a30000 { 583 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 reg = <0x30a30000 0x10000>; 587 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 589 status = "disabled"; 590 }; 591 592 i2c3: i2c@30a40000 { 593 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 reg = <0x30a40000 0x10000>; 597 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 599 status = "disabled"; 600 }; 601 602 i2c4: i2c@30a50000 { 603 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 reg = <0x30a50000 0x10000>; 607 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 609 status = "disabled"; 610 }; 611 612 uart4: serial@30a60000 { 613 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 614 reg = <0x30a60000 0x10000>; 615 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 617 <&clk IMX8MP_CLK_UART4_ROOT>; 618 clock-names = "ipg", "per"; 619 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 620 dma-names = "rx", "tx"; 621 status = "disabled"; 622 }; 623 624 i2c5: i2c@30ad0000 { 625 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 reg = <0x30ad0000 0x10000>; 629 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 631 status = "disabled"; 632 }; 633 634 i2c6: i2c@30ae0000 { 635 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 reg = <0x30ae0000 0x10000>; 639 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 641 status = "disabled"; 642 }; 643 644 usdhc1: mmc@30b40000 { 645 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 646 reg = <0x30b40000 0x10000>; 647 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&clk IMX8MP_CLK_DUMMY>, 649 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 650 <&clk IMX8MP_CLK_USDHC1_ROOT>; 651 clock-names = "ipg", "ahb", "per"; 652 fsl,tuning-start-tap = <20>; 653 fsl,tuning-step= <2>; 654 bus-width = <4>; 655 status = "disabled"; 656 }; 657 658 usdhc2: mmc@30b50000 { 659 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 660 reg = <0x30b50000 0x10000>; 661 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&clk IMX8MP_CLK_DUMMY>, 663 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 664 <&clk IMX8MP_CLK_USDHC2_ROOT>; 665 clock-names = "ipg", "ahb", "per"; 666 fsl,tuning-start-tap = <20>; 667 fsl,tuning-step= <2>; 668 bus-width = <4>; 669 status = "disabled"; 670 }; 671 672 usdhc3: mmc@30b60000 { 673 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 674 reg = <0x30b60000 0x10000>; 675 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&clk IMX8MP_CLK_DUMMY>, 677 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 678 <&clk IMX8MP_CLK_USDHC3_ROOT>; 679 clock-names = "ipg", "ahb", "per"; 680 fsl,tuning-start-tap = <20>; 681 fsl,tuning-step= <2>; 682 bus-width = <4>; 683 status = "disabled"; 684 }; 685 686 sdma1: dma-controller@30bd0000 { 687 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 688 reg = <0x30bd0000 0x10000>; 689 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 691 <&clk IMX8MP_CLK_SDMA1_ROOT>; 692 clock-names = "ipg", "ahb"; 693 #dma-cells = <3>; 694 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 695 }; 696 697 fec: ethernet@30be0000 { 698 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 699 reg = <0x30be0000 0x10000>; 700 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 704 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 705 <&clk IMX8MP_CLK_ENET_TIMER>, 706 <&clk IMX8MP_CLK_ENET_REF>, 707 <&clk IMX8MP_CLK_ENET_PHY_REF>; 708 clock-names = "ipg", "ahb", "ptp", 709 "enet_clk_ref", "enet_out"; 710 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 711 <&clk IMX8MP_CLK_ENET_TIMER>, 712 <&clk IMX8MP_CLK_ENET_REF>, 713 <&clk IMX8MP_CLK_ENET_TIMER>; 714 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 715 <&clk IMX8MP_SYS_PLL2_100M>, 716 <&clk IMX8MP_SYS_PLL2_125M>; 717 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 718 fsl,num-tx-queues = <3>; 719 fsl,num-rx-queues = <3>; 720 status = "disabled"; 721 }; 722 }; 723 724 gic: interrupt-controller@38800000 { 725 compatible = "arm,gic-v3"; 726 reg = <0x38800000 0x10000>, 727 <0x38880000 0xc0000>; 728 #interrupt-cells = <3>; 729 interrupt-controller; 730 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 731 interrupt-parent = <&gic>; 732 }; 733 }; 734}; 735