1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12#include "imx8mp-pinfunc.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec; 21 ethernet1 = &eqos; 22 gpio0 = &gpio1; 23 gpio1 = &gpio2; 24 gpio2 = &gpio3; 25 gpio3 = &gpio4; 26 gpio4 = &gpio5; 27 i2c0 = &i2c1; 28 i2c1 = &i2c2; 29 i2c2 = &i2c3; 30 i2c3 = &i2c4; 31 i2c4 = &i2c5; 32 i2c5 = &i2c6; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 mmc2 = &usdhc3; 36 serial0 = &uart1; 37 serial1 = &uart2; 38 serial2 = &uart3; 39 serial3 = &uart4; 40 spi0 = &flexspi; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 A53_0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 reg = <0x0>; 51 clock-latency = <61036>; 52 clocks = <&clk IMX8MP_CLK_ARM>; 53 enable-method = "psci"; 54 i-cache-size = <0x8000>; 55 i-cache-line-size = <64>; 56 i-cache-sets = <256>; 57 d-cache-size = <0x8000>; 58 d-cache-line-size = <64>; 59 d-cache-sets = <128>; 60 next-level-cache = <&A53_L2>; 61 #cooling-cells = <2>; 62 }; 63 64 A53_1: cpu@1 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x1>; 68 clock-latency = <61036>; 69 clocks = <&clk IMX8MP_CLK_ARM>; 70 enable-method = "psci"; 71 i-cache-size = <0x8000>; 72 i-cache-line-size = <64>; 73 i-cache-sets = <256>; 74 d-cache-size = <0x8000>; 75 d-cache-line-size = <64>; 76 d-cache-sets = <128>; 77 next-level-cache = <&A53_L2>; 78 #cooling-cells = <2>; 79 }; 80 81 A53_2: cpu@2 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x2>; 85 clock-latency = <61036>; 86 clocks = <&clk IMX8MP_CLK_ARM>; 87 enable-method = "psci"; 88 i-cache-size = <0x8000>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <256>; 91 d-cache-size = <0x8000>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&A53_L2>; 95 #cooling-cells = <2>; 96 }; 97 98 A53_3: cpu@3 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x3>; 102 clock-latency = <61036>; 103 clocks = <&clk IMX8MP_CLK_ARM>; 104 enable-method = "psci"; 105 i-cache-size = <0x8000>; 106 i-cache-line-size = <64>; 107 i-cache-sets = <256>; 108 d-cache-size = <0x8000>; 109 d-cache-line-size = <64>; 110 d-cache-sets = <128>; 111 next-level-cache = <&A53_L2>; 112 #cooling-cells = <2>; 113 }; 114 115 A53_L2: l2-cache0 { 116 compatible = "cache"; 117 cache-level = <2>; 118 cache-size = <0x80000>; 119 cache-line-size = <64>; 120 cache-sets = <512>; 121 }; 122 }; 123 124 osc_32k: clock-osc-32k { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <32768>; 128 clock-output-names = "osc_32k"; 129 }; 130 131 osc_24m: clock-osc-24m { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 clock-frequency = <24000000>; 135 clock-output-names = "osc_24m"; 136 }; 137 138 clk_ext1: clock-ext1 { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 clock-frequency = <133000000>; 142 clock-output-names = "clk_ext1"; 143 }; 144 145 clk_ext2: clock-ext2 { 146 compatible = "fixed-clock"; 147 #clock-cells = <0>; 148 clock-frequency = <133000000>; 149 clock-output-names = "clk_ext2"; 150 }; 151 152 clk_ext3: clock-ext3 { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 clock-frequency = <133000000>; 156 clock-output-names = "clk_ext3"; 157 }; 158 159 clk_ext4: clock-ext4 { 160 compatible = "fixed-clock"; 161 #clock-cells = <0>; 162 clock-frequency= <133000000>; 163 clock-output-names = "clk_ext4"; 164 }; 165 166 reserved-memory { 167 #address-cells = <2>; 168 #size-cells = <2>; 169 ranges; 170 171 dsp_reserved: dsp@92400000 { 172 reg = <0 0x92400000 0 0x2000000>; 173 no-map; 174 }; 175 }; 176 177 pmu { 178 compatible = "arm,cortex-a53-pmu"; 179 interrupts = <GIC_PPI 7 180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 181 }; 182 183 psci { 184 compatible = "arm,psci-1.0"; 185 method = "smc"; 186 }; 187 188 thermal-zones { 189 cpu-thermal { 190 polling-delay-passive = <250>; 191 polling-delay = <2000>; 192 thermal-sensors = <&tmu 0>; 193 trips { 194 cpu_alert0: trip0 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 cpu_crit0: trip1 { 201 temperature = <95000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&cpu_alert0>; 210 cooling-device = 211 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 212 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 213 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 214 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 215 }; 216 }; 217 }; 218 219 soc-thermal { 220 polling-delay-passive = <250>; 221 polling-delay = <2000>; 222 thermal-sensors = <&tmu 1>; 223 trips { 224 soc_alert0: trip0 { 225 temperature = <85000>; 226 hysteresis = <2000>; 227 type = "passive"; 228 }; 229 230 soc_crit0: trip1 { 231 temperature = <95000>; 232 hysteresis = <2000>; 233 type = "critical"; 234 }; 235 }; 236 237 cooling-maps { 238 map0 { 239 trip = <&soc_alert0>; 240 cooling-device = 241 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 242 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 243 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 244 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 245 }; 246 }; 247 }; 248 }; 249 250 timer { 251 compatible = "arm,armv8-timer"; 252 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 253 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 254 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 255 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 256 clock-frequency = <8000000>; 257 arm,no-tick-in-suspend; 258 }; 259 260 soc@0 { 261 compatible = "fsl,imx8mp-soc", "simple-bus"; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 ranges = <0x0 0x0 0x0 0x3e000000>; 265 nvmem-cells = <&imx8mp_uid>; 266 nvmem-cell-names = "soc_unique_id"; 267 268 aips1: bus@30000000 { 269 compatible = "fsl,aips-bus", "simple-bus"; 270 reg = <0x30000000 0x400000>; 271 #address-cells = <1>; 272 #size-cells = <1>; 273 ranges; 274 275 gpio1: gpio@30200000 { 276 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 277 reg = <0x30200000 0x10000>; 278 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 281 gpio-controller; 282 #gpio-cells = <2>; 283 interrupt-controller; 284 #interrupt-cells = <2>; 285 gpio-ranges = <&iomuxc 0 5 30>; 286 }; 287 288 gpio2: gpio@30210000 { 289 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 290 reg = <0x30210000 0x10000>; 291 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 294 gpio-controller; 295 #gpio-cells = <2>; 296 interrupt-controller; 297 #interrupt-cells = <2>; 298 gpio-ranges = <&iomuxc 0 35 21>; 299 }; 300 301 gpio3: gpio@30220000 { 302 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 303 reg = <0x30220000 0x10000>; 304 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 307 gpio-controller; 308 #gpio-cells = <2>; 309 interrupt-controller; 310 #interrupt-cells = <2>; 311 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 312 }; 313 314 gpio4: gpio@30230000 { 315 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 316 reg = <0x30230000 0x10000>; 317 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 gpio-ranges = <&iomuxc 0 82 32>; 325 }; 326 327 gpio5: gpio@30240000 { 328 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 329 reg = <0x30240000 0x10000>; 330 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 gpio-ranges = <&iomuxc 0 114 30>; 338 }; 339 340 tmu: tmu@30260000 { 341 compatible = "fsl,imx8mp-tmu"; 342 reg = <0x30260000 0x10000>; 343 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 344 #thermal-sensor-cells = <1>; 345 }; 346 347 wdog1: watchdog@30280000 { 348 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 349 reg = <0x30280000 0x10000>; 350 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 352 status = "disabled"; 353 }; 354 355 wdog2: watchdog@30290000 { 356 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 357 reg = <0x30290000 0x10000>; 358 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 360 status = "disabled"; 361 }; 362 363 wdog3: watchdog@302a0000 { 364 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 365 reg = <0x302a0000 0x10000>; 366 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 368 status = "disabled"; 369 }; 370 371 iomuxc: pinctrl@30330000 { 372 compatible = "fsl,imx8mp-iomuxc"; 373 reg = <0x30330000 0x10000>; 374 }; 375 376 gpr: iomuxc-gpr@30340000 { 377 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 378 reg = <0x30340000 0x10000>; 379 }; 380 381 ocotp: efuse@30350000 { 382 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 383 reg = <0x30350000 0x10000>; 384 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 385 /* For nvmem subnodes */ 386 #address-cells = <1>; 387 #size-cells = <1>; 388 389 imx8mp_uid: unique-id@420 { 390 reg = <0x8 0x8>; 391 }; 392 393 cpu_speed_grade: speed-grade@10 { 394 reg = <0x10 4>; 395 }; 396 397 eth_mac1: mac-address@90 { 398 reg = <0x90 6>; 399 }; 400 401 eth_mac2: mac-address@96 { 402 reg = <0x96 6>; 403 }; 404 }; 405 406 anatop: anatop@30360000 { 407 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", 408 "syscon"; 409 reg = <0x30360000 0x10000>; 410 }; 411 412 snvs: snvs@30370000 { 413 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 414 reg = <0x30370000 0x10000>; 415 416 snvs_rtc: snvs-rtc-lp { 417 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 418 regmap =<&snvs>; 419 offset = <0x34>; 420 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 423 clock-names = "snvs-rtc"; 424 }; 425 426 snvs_pwrkey: snvs-powerkey { 427 compatible = "fsl,sec-v4.0-pwrkey"; 428 regmap = <&snvs>; 429 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 431 clock-names = "snvs-pwrkey"; 432 linux,keycode = <KEY_POWER>; 433 wakeup-source; 434 status = "disabled"; 435 }; 436 }; 437 438 clk: clock-controller@30380000 { 439 compatible = "fsl,imx8mp-ccm"; 440 reg = <0x30380000 0x10000>; 441 #clock-cells = <1>; 442 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 443 <&clk_ext3>, <&clk_ext4>; 444 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 445 "clk_ext3", "clk_ext4"; 446 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 447 <&clk IMX8MP_CLK_A53_CORE>, 448 <&clk IMX8MP_CLK_NOC>, 449 <&clk IMX8MP_CLK_NOC_IO>, 450 <&clk IMX8MP_CLK_GIC>, 451 <&clk IMX8MP_CLK_AUDIO_AHB>, 452 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, 453 <&clk IMX8MP_AUDIO_PLL1>, 454 <&clk IMX8MP_AUDIO_PLL2>; 455 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 456 <&clk IMX8MP_ARM_PLL_OUT>, 457 <&clk IMX8MP_SYS_PLL2_1000M>, 458 <&clk IMX8MP_SYS_PLL1_800M>, 459 <&clk IMX8MP_SYS_PLL2_500M>, 460 <&clk IMX8MP_SYS_PLL1_800M>, 461 <&clk IMX8MP_SYS_PLL1_800M>; 462 assigned-clock-rates = <0>, <0>, 463 <1000000000>, 464 <800000000>, 465 <500000000>, 466 <400000000>, 467 <800000000>, 468 <393216000>, 469 <361267200>; 470 }; 471 472 src: reset-controller@30390000 { 473 compatible = "fsl,imx8mp-src", "syscon"; 474 reg = <0x30390000 0x10000>; 475 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 476 #reset-cells = <1>; 477 }; 478 }; 479 480 aips2: bus@30400000 { 481 compatible = "fsl,aips-bus", "simple-bus"; 482 reg = <0x30400000 0x400000>; 483 #address-cells = <1>; 484 #size-cells = <1>; 485 ranges; 486 487 pwm1: pwm@30660000 { 488 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 489 reg = <0x30660000 0x10000>; 490 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 492 <&clk IMX8MP_CLK_PWM1_ROOT>; 493 clock-names = "ipg", "per"; 494 #pwm-cells = <2>; 495 status = "disabled"; 496 }; 497 498 pwm2: pwm@30670000 { 499 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 500 reg = <0x30670000 0x10000>; 501 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 503 <&clk IMX8MP_CLK_PWM2_ROOT>; 504 clock-names = "ipg", "per"; 505 #pwm-cells = <2>; 506 status = "disabled"; 507 }; 508 509 pwm3: pwm@30680000 { 510 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 511 reg = <0x30680000 0x10000>; 512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 514 <&clk IMX8MP_CLK_PWM3_ROOT>; 515 clock-names = "ipg", "per"; 516 #pwm-cells = <2>; 517 status = "disabled"; 518 }; 519 520 pwm4: pwm@30690000 { 521 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 522 reg = <0x30690000 0x10000>; 523 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 525 <&clk IMX8MP_CLK_PWM4_ROOT>; 526 clock-names = "ipg", "per"; 527 #pwm-cells = <2>; 528 status = "disabled"; 529 }; 530 531 system_counter: timer@306a0000 { 532 compatible = "nxp,sysctr-timer"; 533 reg = <0x306a0000 0x20000>; 534 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&osc_24m>; 536 clock-names = "per"; 537 }; 538 }; 539 540 aips3: bus@30800000 { 541 compatible = "fsl,aips-bus", "simple-bus"; 542 reg = <0x30800000 0x400000>; 543 #address-cells = <1>; 544 #size-cells = <1>; 545 ranges; 546 547 ecspi1: spi@30820000 { 548 #address-cells = <1>; 549 #size-cells = <0>; 550 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 551 reg = <0x30820000 0x10000>; 552 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 554 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 555 clock-names = "ipg", "per"; 556 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 557 dma-names = "rx", "tx"; 558 status = "disabled"; 559 }; 560 561 ecspi2: spi@30830000 { 562 #address-cells = <1>; 563 #size-cells = <0>; 564 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 565 reg = <0x30830000 0x10000>; 566 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 568 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 569 clock-names = "ipg", "per"; 570 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 571 dma-names = "rx", "tx"; 572 status = "disabled"; 573 }; 574 575 ecspi3: spi@30840000 { 576 #address-cells = <1>; 577 #size-cells = <0>; 578 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 579 reg = <0x30840000 0x10000>; 580 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 582 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 583 clock-names = "ipg", "per"; 584 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 585 dma-names = "rx", "tx"; 586 status = "disabled"; 587 }; 588 589 uart1: serial@30860000 { 590 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 591 reg = <0x30860000 0x10000>; 592 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 594 <&clk IMX8MP_CLK_UART1_ROOT>; 595 clock-names = "ipg", "per"; 596 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 597 dma-names = "rx", "tx"; 598 status = "disabled"; 599 }; 600 601 uart3: serial@30880000 { 602 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 603 reg = <0x30880000 0x10000>; 604 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 606 <&clk IMX8MP_CLK_UART3_ROOT>; 607 clock-names = "ipg", "per"; 608 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 609 dma-names = "rx", "tx"; 610 status = "disabled"; 611 }; 612 613 uart2: serial@30890000 { 614 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 615 reg = <0x30890000 0x10000>; 616 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 618 <&clk IMX8MP_CLK_UART2_ROOT>; 619 clock-names = "ipg", "per"; 620 status = "disabled"; 621 }; 622 623 flexcan1: can@308c0000 { 624 compatible = "fsl,imx8mp-flexcan"; 625 reg = <0x308c0000 0x10000>; 626 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 628 <&clk IMX8MP_CLK_CAN1_ROOT>; 629 clock-names = "ipg", "per"; 630 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 631 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 632 assigned-clock-rates = <40000000>; 633 fsl,clk-source = /bits/ 8 <0>; 634 fsl,stop-mode = <&gpr 0x10 4>; 635 status = "disabled"; 636 }; 637 638 flexcan2: can@308d0000 { 639 compatible = "fsl,imx8mp-flexcan"; 640 reg = <0x308d0000 0x10000>; 641 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 643 <&clk IMX8MP_CLK_CAN2_ROOT>; 644 clock-names = "ipg", "per"; 645 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 646 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 647 assigned-clock-rates = <40000000>; 648 fsl,clk-source = /bits/ 8 <0>; 649 fsl,stop-mode = <&gpr 0x10 5>; 650 status = "disabled"; 651 }; 652 653 crypto: crypto@30900000 { 654 compatible = "fsl,sec-v4.0"; 655 #address-cells = <1>; 656 #size-cells = <1>; 657 reg = <0x30900000 0x40000>; 658 ranges = <0 0x30900000 0x40000>; 659 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&clk IMX8MP_CLK_AHB>, 661 <&clk IMX8MP_CLK_IPG_ROOT>; 662 clock-names = "aclk", "ipg"; 663 664 sec_jr0: jr@1000 { 665 compatible = "fsl,sec-v4.0-job-ring"; 666 reg = <0x1000 0x1000>; 667 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 668 }; 669 670 sec_jr1: jr@2000 { 671 compatible = "fsl,sec-v4.0-job-ring"; 672 reg = <0x2000 0x1000>; 673 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 674 }; 675 676 sec_jr2: jr@3000 { 677 compatible = "fsl,sec-v4.0-job-ring"; 678 reg = <0x3000 0x1000>; 679 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 680 }; 681 }; 682 683 i2c1: i2c@30a20000 { 684 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 reg = <0x30a20000 0x10000>; 688 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 690 status = "disabled"; 691 }; 692 693 i2c2: i2c@30a30000 { 694 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 reg = <0x30a30000 0x10000>; 698 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 700 status = "disabled"; 701 }; 702 703 i2c3: i2c@30a40000 { 704 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 reg = <0x30a40000 0x10000>; 708 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 710 status = "disabled"; 711 }; 712 713 i2c4: i2c@30a50000 { 714 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 reg = <0x30a50000 0x10000>; 718 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 720 status = "disabled"; 721 }; 722 723 uart4: serial@30a60000 { 724 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 725 reg = <0x30a60000 0x10000>; 726 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 728 <&clk IMX8MP_CLK_UART4_ROOT>; 729 clock-names = "ipg", "per"; 730 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 731 dma-names = "rx", "tx"; 732 status = "disabled"; 733 }; 734 735 mu: mailbox@30aa0000 { 736 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 737 reg = <0x30aa0000 0x10000>; 738 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 740 #mbox-cells = <2>; 741 }; 742 743 mu2: mailbox@30e60000 { 744 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 745 reg = <0x30e60000 0x10000>; 746 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 747 #mbox-cells = <2>; 748 status = "disabled"; 749 }; 750 751 i2c5: i2c@30ad0000 { 752 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 reg = <0x30ad0000 0x10000>; 756 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 758 status = "disabled"; 759 }; 760 761 i2c6: i2c@30ae0000 { 762 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 reg = <0x30ae0000 0x10000>; 766 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 768 status = "disabled"; 769 }; 770 771 usdhc1: mmc@30b40000 { 772 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 773 reg = <0x30b40000 0x10000>; 774 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&clk IMX8MP_CLK_DUMMY>, 776 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 777 <&clk IMX8MP_CLK_USDHC1_ROOT>; 778 clock-names = "ipg", "ahb", "per"; 779 fsl,tuning-start-tap = <20>; 780 fsl,tuning-step= <2>; 781 bus-width = <4>; 782 status = "disabled"; 783 }; 784 785 usdhc2: mmc@30b50000 { 786 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 787 reg = <0x30b50000 0x10000>; 788 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&clk IMX8MP_CLK_DUMMY>, 790 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 791 <&clk IMX8MP_CLK_USDHC2_ROOT>; 792 clock-names = "ipg", "ahb", "per"; 793 fsl,tuning-start-tap = <20>; 794 fsl,tuning-step= <2>; 795 bus-width = <4>; 796 status = "disabled"; 797 }; 798 799 usdhc3: mmc@30b60000 { 800 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 801 reg = <0x30b60000 0x10000>; 802 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&clk IMX8MP_CLK_DUMMY>, 804 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 805 <&clk IMX8MP_CLK_USDHC3_ROOT>; 806 clock-names = "ipg", "ahb", "per"; 807 fsl,tuning-start-tap = <20>; 808 fsl,tuning-step= <2>; 809 bus-width = <4>; 810 status = "disabled"; 811 }; 812 813 flexspi: spi@30bb0000 { 814 compatible = "nxp,imx8mp-fspi"; 815 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 816 reg-names = "fspi_base", "fspi_mmap"; 817 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 819 <&clk IMX8MP_CLK_QSPI_ROOT>; 820 clock-names = "fspi_en", "fspi"; 821 assigned-clock-rates = <80000000>; 822 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 status = "disabled"; 826 }; 827 828 sdma1: dma-controller@30bd0000 { 829 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 830 reg = <0x30bd0000 0x10000>; 831 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 833 <&clk IMX8MP_CLK_AHB>; 834 clock-names = "ipg", "ahb"; 835 #dma-cells = <3>; 836 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 837 }; 838 839 fec: ethernet@30be0000 { 840 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 841 reg = <0x30be0000 0x10000>; 842 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 847 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 848 <&clk IMX8MP_CLK_ENET_TIMER>, 849 <&clk IMX8MP_CLK_ENET_REF>, 850 <&clk IMX8MP_CLK_ENET_PHY_REF>; 851 clock-names = "ipg", "ahb", "ptp", 852 "enet_clk_ref", "enet_out"; 853 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 854 <&clk IMX8MP_CLK_ENET_TIMER>, 855 <&clk IMX8MP_CLK_ENET_REF>, 856 <&clk IMX8MP_CLK_ENET_PHY_REF>; 857 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 858 <&clk IMX8MP_SYS_PLL2_100M>, 859 <&clk IMX8MP_SYS_PLL2_125M>, 860 <&clk IMX8MP_SYS_PLL2_50M>; 861 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 862 fsl,num-tx-queues = <3>; 863 fsl,num-rx-queues = <3>; 864 nvmem-cells = <ð_mac1>; 865 nvmem-cell-names = "mac-address"; 866 fsl,stop-mode = <&gpr 0x10 3>; 867 status = "disabled"; 868 }; 869 870 eqos: ethernet@30bf0000 { 871 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 872 reg = <0x30bf0000 0x10000>; 873 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-names = "macirq", "eth_wake_irq"; 876 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 877 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 878 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 879 <&clk IMX8MP_CLK_ENET_QOS>; 880 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 881 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 882 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 883 <&clk IMX8MP_CLK_ENET_QOS>; 884 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 885 <&clk IMX8MP_SYS_PLL2_100M>, 886 <&clk IMX8MP_SYS_PLL2_125M>; 887 assigned-clock-rates = <0>, <100000000>, <125000000>; 888 nvmem-cells = <ð_mac2>; 889 nvmem-cell-names = "mac-address"; 890 intf_mode = <&gpr 0x4>; 891 status = "disabled"; 892 }; 893 }; 894 895 gic: interrupt-controller@38800000 { 896 compatible = "arm,gic-v3"; 897 reg = <0x38800000 0x10000>, 898 <0x38880000 0xc0000>; 899 #interrupt-cells = <3>; 900 interrupt-controller; 901 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 902 interrupt-parent = <&gic>; 903 }; 904 905 ddr-pmu@3d800000 { 906 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 907 reg = <0x3d800000 0x400000>; 908 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 909 }; 910 911 usb3_phy0: usb-phy@381f0040 { 912 compatible = "fsl,imx8mp-usb-phy"; 913 reg = <0x381f0040 0x40>; 914 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 915 clock-names = "phy"; 916 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 917 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 918 #phy-cells = <0>; 919 status = "disabled"; 920 }; 921 922 usb3_0: usb@32f10100 { 923 compatible = "fsl,imx8mp-dwc3"; 924 reg = <0x32f10100 0x8>, 925 <0x381f0000 0x20>; 926 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 927 <&clk IMX8MP_CLK_USB_ROOT>; 928 clock-names = "hsio", "suspend"; 929 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 930 #address-cells = <1>; 931 #size-cells = <1>; 932 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 933 ranges; 934 status = "disabled"; 935 936 usb_dwc3_0: usb@38100000 { 937 compatible = "snps,dwc3"; 938 reg = <0x38100000 0x10000>; 939 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 940 <&clk IMX8MP_CLK_USB_CORE_REF>, 941 <&clk IMX8MP_CLK_USB_ROOT>; 942 clock-names = "bus_early", "ref", "suspend"; 943 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 944 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 945 assigned-clock-rates = <500000000>; 946 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 947 phys = <&usb3_phy0>, <&usb3_phy0>; 948 phy-names = "usb2-phy", "usb3-phy"; 949 snps,dis-u2-freeclk-exists-quirk; 950 }; 951 952 }; 953 954 usb3_phy1: usb-phy@382f0040 { 955 compatible = "fsl,imx8mp-usb-phy"; 956 reg = <0x382f0040 0x40>; 957 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 958 clock-names = "phy"; 959 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 960 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 961 #phy-cells = <0>; 962 status = "disabled"; 963 }; 964 965 usb3_1: usb@32f10108 { 966 compatible = "fsl,imx8mp-dwc3"; 967 reg = <0x32f10108 0x8>, 968 <0x382f0000 0x20>; 969 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 970 <&clk IMX8MP_CLK_USB_ROOT>; 971 clock-names = "hsio", "suspend"; 972 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 973 #address-cells = <1>; 974 #size-cells = <1>; 975 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 976 ranges; 977 status = "disabled"; 978 979 usb_dwc3_1: usb@38200000 { 980 compatible = "snps,dwc3"; 981 reg = <0x38200000 0x10000>; 982 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 983 <&clk IMX8MP_CLK_USB_CORE_REF>, 984 <&clk IMX8MP_CLK_USB_ROOT>; 985 clock-names = "bus_early", "ref", "suspend"; 986 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 987 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 988 assigned-clock-rates = <500000000>; 989 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 990 phys = <&usb3_phy1>, <&usb3_phy1>; 991 phy-names = "usb2-phy", "usb3-phy"; 992 snps,dis-u2-freeclk-exists-quirk; 993 }; 994 }; 995 996 dsp: dsp@3b6e8000 { 997 compatible = "fsl,imx8mp-dsp"; 998 reg = <0x3b6e8000 0x88000>; 999 mbox-names = "txdb0", "txdb1", 1000 "rxdb0", "rxdb1"; 1001 mboxes = <&mu2 2 0>, <&mu2 2 1>, 1002 <&mu2 3 0>, <&mu2 3 1>; 1003 memory-region = <&dsp_reserved>; 1004 status = "disabled"; 1005 }; 1006 }; 1007}; 1008