1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/interconnect/fsl,imx8mp.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15#include "imx8mp-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &fec; 24 ethernet1 = &eqos; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 i2c4 = &i2c5; 35 i2c5 = &i2c6; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 spi0 = &flexspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 A53_0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0>; 54 clock-latency = <61036>; 55 clocks = <&clk IMX8MP_CLK_ARM>; 56 enable-method = "psci"; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&A53_L2>; 64 nvmem-cells = <&cpu_speed_grade>; 65 nvmem-cell-names = "speed_grade"; 66 operating-points-v2 = <&a53_opp_table>; 67 #cooling-cells = <2>; 68 }; 69 70 A53_1: cpu@1 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x1>; 74 clock-latency = <61036>; 75 clocks = <&clk IMX8MP_CLK_ARM>; 76 enable-method = "psci"; 77 i-cache-size = <0x8000>; 78 i-cache-line-size = <64>; 79 i-cache-sets = <256>; 80 d-cache-size = <0x8000>; 81 d-cache-line-size = <64>; 82 d-cache-sets = <128>; 83 next-level-cache = <&A53_L2>; 84 operating-points-v2 = <&a53_opp_table>; 85 #cooling-cells = <2>; 86 }; 87 88 A53_2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x2>; 92 clock-latency = <61036>; 93 clocks = <&clk IMX8MP_CLK_ARM>; 94 enable-method = "psci"; 95 i-cache-size = <0x8000>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <0x8000>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&A53_L2>; 102 operating-points-v2 = <&a53_opp_table>; 103 #cooling-cells = <2>; 104 }; 105 106 A53_3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x3>; 110 clock-latency = <61036>; 111 clocks = <&clk IMX8MP_CLK_ARM>; 112 enable-method = "psci"; 113 i-cache-size = <0x8000>; 114 i-cache-line-size = <64>; 115 i-cache-sets = <256>; 116 d-cache-size = <0x8000>; 117 d-cache-line-size = <64>; 118 d-cache-sets = <128>; 119 next-level-cache = <&A53_L2>; 120 operating-points-v2 = <&a53_opp_table>; 121 #cooling-cells = <2>; 122 }; 123 124 A53_L2: l2-cache0 { 125 compatible = "cache"; 126 cache-unified; 127 cache-level = <2>; 128 cache-size = <0x80000>; 129 cache-line-size = <64>; 130 cache-sets = <512>; 131 }; 132 }; 133 134 a53_opp_table: opp-table { 135 compatible = "operating-points-v2"; 136 opp-shared; 137 138 opp-1200000000 { 139 opp-hz = /bits/ 64 <1200000000>; 140 opp-microvolt = <850000>; 141 opp-supported-hw = <0x8a0>, <0x7>; 142 clock-latency-ns = <150000>; 143 opp-suspend; 144 }; 145 146 opp-1600000000 { 147 opp-hz = /bits/ 64 <1600000000>; 148 opp-microvolt = <950000>; 149 opp-supported-hw = <0xa0>, <0x7>; 150 clock-latency-ns = <150000>; 151 opp-suspend; 152 }; 153 154 opp-1800000000 { 155 opp-hz = /bits/ 64 <1800000000>; 156 opp-microvolt = <1000000>; 157 opp-supported-hw = <0x20>, <0x3>; 158 clock-latency-ns = <150000>; 159 opp-suspend; 160 }; 161 }; 162 163 osc_32k: clock-osc-32k { 164 compatible = "fixed-clock"; 165 #clock-cells = <0>; 166 clock-frequency = <32768>; 167 clock-output-names = "osc_32k"; 168 }; 169 170 osc_24m: clock-osc-24m { 171 compatible = "fixed-clock"; 172 #clock-cells = <0>; 173 clock-frequency = <24000000>; 174 clock-output-names = "osc_24m"; 175 }; 176 177 clk_ext1: clock-ext1 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <133000000>; 181 clock-output-names = "clk_ext1"; 182 }; 183 184 clk_ext2: clock-ext2 { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <133000000>; 188 clock-output-names = "clk_ext2"; 189 }; 190 191 clk_ext3: clock-ext3 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext3"; 196 }; 197 198 clk_ext4: clock-ext4 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext4"; 203 }; 204 205 reserved-memory { 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges; 209 210 dsp_reserved: dsp@92400000 { 211 reg = <0 0x92400000 0 0x2000000>; 212 no-map; 213 }; 214 }; 215 216 pmu { 217 compatible = "arm,cortex-a53-pmu"; 218 interrupts = <GIC_PPI 7 219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0"; 224 method = "smc"; 225 }; 226 227 thermal-zones { 228 cpu-thermal { 229 polling-delay-passive = <250>; 230 polling-delay = <2000>; 231 thermal-sensors = <&tmu 0>; 232 trips { 233 cpu_alert0: trip0 { 234 temperature = <85000>; 235 hysteresis = <2000>; 236 type = "passive"; 237 }; 238 239 cpu_crit0: trip1 { 240 temperature = <95000>; 241 hysteresis = <2000>; 242 type = "critical"; 243 }; 244 }; 245 246 cooling-maps { 247 map0 { 248 trip = <&cpu_alert0>; 249 cooling-device = 250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 254 }; 255 }; 256 }; 257 258 soc-thermal { 259 polling-delay-passive = <250>; 260 polling-delay = <2000>; 261 thermal-sensors = <&tmu 1>; 262 trips { 263 soc_alert0: trip0 { 264 temperature = <85000>; 265 hysteresis = <2000>; 266 type = "passive"; 267 }; 268 269 soc_crit0: trip1 { 270 temperature = <95000>; 271 hysteresis = <2000>; 272 type = "critical"; 273 }; 274 }; 275 276 cooling-maps { 277 map0 { 278 trip = <&soc_alert0>; 279 cooling-device = 280 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 281 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 282 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 283 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 284 }; 285 }; 286 }; 287 }; 288 289 timer { 290 compatible = "arm,armv8-timer"; 291 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 293 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 294 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 295 clock-frequency = <8000000>; 296 arm,no-tick-in-suspend; 297 }; 298 299 soc: soc@0 { 300 compatible = "fsl,imx8mp-soc", "simple-bus"; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 ranges = <0x0 0x0 0x0 0x3e000000>; 304 nvmem-cells = <&imx8mp_uid>; 305 nvmem-cell-names = "soc_unique_id"; 306 307 aips1: bus@30000000 { 308 compatible = "fsl,aips-bus", "simple-bus"; 309 reg = <0x30000000 0x400000>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges; 313 314 gpio1: gpio@30200000 { 315 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 316 reg = <0x30200000 0x10000>; 317 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 320 gpio-controller; 321 #gpio-cells = <2>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 gpio-ranges = <&iomuxc 0 5 30>; 325 }; 326 327 gpio2: gpio@30210000 { 328 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 329 reg = <0x30210000 0x10000>; 330 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 gpio-ranges = <&iomuxc 0 35 21>; 338 }; 339 340 gpio3: gpio@30220000 { 341 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 342 reg = <0x30220000 0x10000>; 343 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 351 }; 352 353 gpio4: gpio@30230000 { 354 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 355 reg = <0x30230000 0x10000>; 356 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 359 gpio-controller; 360 #gpio-cells = <2>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 gpio-ranges = <&iomuxc 0 82 32>; 364 }; 365 366 gpio5: gpio@30240000 { 367 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 368 reg = <0x30240000 0x10000>; 369 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 gpio-ranges = <&iomuxc 0 114 30>; 377 }; 378 379 tmu: tmu@30260000 { 380 compatible = "fsl,imx8mp-tmu"; 381 reg = <0x30260000 0x10000>; 382 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 383 nvmem-cells = <&tmu_calib>; 384 nvmem-cell-names = "calib"; 385 #thermal-sensor-cells = <1>; 386 }; 387 388 wdog1: watchdog@30280000 { 389 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 390 reg = <0x30280000 0x10000>; 391 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 393 status = "disabled"; 394 }; 395 396 wdog2: watchdog@30290000 { 397 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 398 reg = <0x30290000 0x10000>; 399 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 401 status = "disabled"; 402 }; 403 404 wdog3: watchdog@302a0000 { 405 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 406 reg = <0x302a0000 0x10000>; 407 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 409 status = "disabled"; 410 }; 411 412 iomuxc: pinctrl@30330000 { 413 compatible = "fsl,imx8mp-iomuxc"; 414 reg = <0x30330000 0x10000>; 415 }; 416 417 gpr: syscon@30340000 { 418 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 419 reg = <0x30340000 0x10000>; 420 }; 421 422 ocotp: efuse@30350000 { 423 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 424 reg = <0x30350000 0x10000>; 425 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 426 /* For nvmem subnodes */ 427 #address-cells = <1>; 428 #size-cells = <1>; 429 430 /* 431 * The register address below maps to the MX8M 432 * Fusemap Description Table entries this way. 433 * Assuming 434 * reg = <ADDR SIZE>; 435 * then 436 * Fuse Address = (ADDR * 4) + 0x400 437 * Note that if SIZE is greater than 4, then 438 * each subsequent fuse is located at offset 439 * +0x10 in Fusemap Description Table (e.g. 440 * reg = <0x8 0x8> describes fuses 0x420 and 441 * 0x430). 442 */ 443 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 444 reg = <0x8 0x8>; 445 }; 446 447 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 448 reg = <0x10 4>; 449 }; 450 451 eth_mac1: mac-address@90 { /* 0x640 */ 452 reg = <0x90 6>; 453 }; 454 455 eth_mac2: mac-address@96 { /* 0x658 */ 456 reg = <0x96 6>; 457 }; 458 459 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 460 reg = <0x264 0x10>; 461 }; 462 }; 463 464 anatop: clock-controller@30360000 { 465 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 466 reg = <0x30360000 0x10000>; 467 #clock-cells = <1>; 468 }; 469 470 snvs: snvs@30370000 { 471 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 472 reg = <0x30370000 0x10000>; 473 474 snvs_rtc: snvs-rtc-lp { 475 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 476 regmap =<&snvs>; 477 offset = <0x34>; 478 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 481 clock-names = "snvs-rtc"; 482 }; 483 484 snvs_pwrkey: snvs-powerkey { 485 compatible = "fsl,sec-v4.0-pwrkey"; 486 regmap = <&snvs>; 487 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 489 clock-names = "snvs-pwrkey"; 490 linux,keycode = <KEY_POWER>; 491 wakeup-source; 492 status = "disabled"; 493 }; 494 495 snvs_lpgpr: snvs-lpgpr { 496 compatible = "fsl,imx8mp-snvs-lpgpr", 497 "fsl,imx7d-snvs-lpgpr"; 498 }; 499 }; 500 501 clk: clock-controller@30380000 { 502 compatible = "fsl,imx8mp-ccm"; 503 reg = <0x30380000 0x10000>; 504 #clock-cells = <1>; 505 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 506 <&clk_ext3>, <&clk_ext4>; 507 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 508 "clk_ext3", "clk_ext4"; 509 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 510 <&clk IMX8MP_CLK_A53_CORE>, 511 <&clk IMX8MP_CLK_NOC>, 512 <&clk IMX8MP_CLK_NOC_IO>, 513 <&clk IMX8MP_CLK_GIC>, 514 <&clk IMX8MP_CLK_AUDIO_AHB>, 515 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, 516 <&clk IMX8MP_AUDIO_PLL1>, 517 <&clk IMX8MP_AUDIO_PLL2>; 518 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 519 <&clk IMX8MP_ARM_PLL_OUT>, 520 <&clk IMX8MP_SYS_PLL2_1000M>, 521 <&clk IMX8MP_SYS_PLL1_800M>, 522 <&clk IMX8MP_SYS_PLL2_500M>, 523 <&clk IMX8MP_SYS_PLL1_800M>, 524 <&clk IMX8MP_SYS_PLL1_800M>; 525 assigned-clock-rates = <0>, <0>, 526 <1000000000>, 527 <800000000>, 528 <500000000>, 529 <400000000>, 530 <800000000>, 531 <393216000>, 532 <361267200>; 533 }; 534 535 src: reset-controller@30390000 { 536 compatible = "fsl,imx8mp-src", "syscon"; 537 reg = <0x30390000 0x10000>; 538 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 539 #reset-cells = <1>; 540 }; 541 542 gpc: gpc@303a0000 { 543 compatible = "fsl,imx8mp-gpc"; 544 reg = <0x303a0000 0x1000>; 545 interrupt-parent = <&gic>; 546 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 547 interrupt-controller; 548 #interrupt-cells = <3>; 549 550 pgc { 551 #address-cells = <1>; 552 #size-cells = <0>; 553 554 pgc_mipi_phy1: power-domain@0 { 555 #power-domain-cells = <0>; 556 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 557 }; 558 559 pgc_pcie_phy: power-domain@1 { 560 #power-domain-cells = <0>; 561 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 562 }; 563 564 pgc_usb1_phy: power-domain@2 { 565 #power-domain-cells = <0>; 566 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 567 }; 568 569 pgc_usb2_phy: power-domain@3 { 570 #power-domain-cells = <0>; 571 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 572 }; 573 574 pgc_gpu2d: power-domain@6 { 575 #power-domain-cells = <0>; 576 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 577 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 578 power-domains = <&pgc_gpumix>; 579 }; 580 581 pgc_gpumix: power-domain@7 { 582 #power-domain-cells = <0>; 583 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 584 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 585 <&clk IMX8MP_CLK_GPU_AHB>; 586 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 587 <&clk IMX8MP_CLK_GPU_AHB>; 588 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 589 <&clk IMX8MP_SYS_PLL1_800M>; 590 assigned-clock-rates = <800000000>, <400000000>; 591 }; 592 593 pgc_gpu3d: power-domain@9 { 594 #power-domain-cells = <0>; 595 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 596 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 597 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 598 power-domains = <&pgc_gpumix>; 599 }; 600 601 pgc_mediamix: power-domain@10 { 602 #power-domain-cells = <0>; 603 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 604 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 605 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 606 }; 607 608 pgc_mipi_phy2: power-domain@16 { 609 #power-domain-cells = <0>; 610 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 611 }; 612 613 pgc_hsiomix: power-domain@17 { 614 #power-domain-cells = <0>; 615 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 616 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 617 <&clk IMX8MP_CLK_HSIO_ROOT>; 618 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 619 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 620 assigned-clock-rates = <500000000>; 621 }; 622 623 pgc_ispdwp: power-domain@18 { 624 #power-domain-cells = <0>; 625 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 626 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 627 }; 628 629 pgc_vpumix: power-domain@19 { 630 #power-domain-cells = <0>; 631 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 632 clocks =<&clk IMX8MP_CLK_VPU_ROOT>; 633 }; 634 635 pgc_vpu_g1: power-domain@20 { 636 #power-domain-cells = <0>; 637 power-domains = <&pgc_vpumix>; 638 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 639 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 640 }; 641 642 pgc_vpu_g2: power-domain@21 { 643 #power-domain-cells = <0>; 644 power-domains = <&pgc_vpumix>; 645 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 646 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 647 }; 648 649 pgc_vpu_vc8000e: power-domain@22 { 650 #power-domain-cells = <0>; 651 power-domains = <&pgc_vpumix>; 652 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 653 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 654 }; 655 656 pgc_mlmix: power-domain@24 { 657 #power-domain-cells = <0>; 658 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 659 clocks = <&clk IMX8MP_CLK_ML_AXI>, 660 <&clk IMX8MP_CLK_ML_AHB>, 661 <&clk IMX8MP_CLK_NPU_ROOT>; 662 }; 663 }; 664 }; 665 }; 666 667 aips2: bus@30400000 { 668 compatible = "fsl,aips-bus", "simple-bus"; 669 reg = <0x30400000 0x400000>; 670 #address-cells = <1>; 671 #size-cells = <1>; 672 ranges; 673 674 pwm1: pwm@30660000 { 675 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 676 reg = <0x30660000 0x10000>; 677 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 679 <&clk IMX8MP_CLK_PWM1_ROOT>; 680 clock-names = "ipg", "per"; 681 #pwm-cells = <3>; 682 status = "disabled"; 683 }; 684 685 pwm2: pwm@30670000 { 686 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 687 reg = <0x30670000 0x10000>; 688 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 690 <&clk IMX8MP_CLK_PWM2_ROOT>; 691 clock-names = "ipg", "per"; 692 #pwm-cells = <3>; 693 status = "disabled"; 694 }; 695 696 pwm3: pwm@30680000 { 697 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 698 reg = <0x30680000 0x10000>; 699 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 701 <&clk IMX8MP_CLK_PWM3_ROOT>; 702 clock-names = "ipg", "per"; 703 #pwm-cells = <3>; 704 status = "disabled"; 705 }; 706 707 pwm4: pwm@30690000 { 708 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 709 reg = <0x30690000 0x10000>; 710 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 711 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 712 <&clk IMX8MP_CLK_PWM4_ROOT>; 713 clock-names = "ipg", "per"; 714 #pwm-cells = <3>; 715 status = "disabled"; 716 }; 717 718 system_counter: timer@306a0000 { 719 compatible = "nxp,sysctr-timer"; 720 reg = <0x306a0000 0x20000>; 721 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&osc_24m>; 723 clock-names = "per"; 724 }; 725 }; 726 727 aips3: bus@30800000 { 728 compatible = "fsl,aips-bus", "simple-bus"; 729 reg = <0x30800000 0x400000>; 730 #address-cells = <1>; 731 #size-cells = <1>; 732 ranges; 733 734 spba-bus@30800000 { 735 compatible = "fsl,spba-bus", "simple-bus"; 736 reg = <0x30800000 0x100000>; 737 #address-cells = <1>; 738 #size-cells = <1>; 739 ranges; 740 741 ecspi1: spi@30820000 { 742 #address-cells = <1>; 743 #size-cells = <0>; 744 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 745 reg = <0x30820000 0x10000>; 746 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 748 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 749 clock-names = "ipg", "per"; 750 assigned-clock-rates = <80000000>; 751 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 752 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 753 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 754 dma-names = "rx", "tx"; 755 status = "disabled"; 756 }; 757 758 ecspi2: spi@30830000 { 759 #address-cells = <1>; 760 #size-cells = <0>; 761 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 762 reg = <0x30830000 0x10000>; 763 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 765 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 766 clock-names = "ipg", "per"; 767 assigned-clock-rates = <80000000>; 768 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 769 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 770 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 771 dma-names = "rx", "tx"; 772 status = "disabled"; 773 }; 774 775 ecspi3: spi@30840000 { 776 #address-cells = <1>; 777 #size-cells = <0>; 778 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 779 reg = <0x30840000 0x10000>; 780 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 782 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 783 clock-names = "ipg", "per"; 784 assigned-clock-rates = <80000000>; 785 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 786 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 787 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 788 dma-names = "rx", "tx"; 789 status = "disabled"; 790 }; 791 792 uart1: serial@30860000 { 793 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 794 reg = <0x30860000 0x10000>; 795 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 797 <&clk IMX8MP_CLK_UART1_ROOT>; 798 clock-names = "ipg", "per"; 799 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 800 dma-names = "rx", "tx"; 801 status = "disabled"; 802 }; 803 804 uart3: serial@30880000 { 805 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 806 reg = <0x30880000 0x10000>; 807 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 809 <&clk IMX8MP_CLK_UART3_ROOT>; 810 clock-names = "ipg", "per"; 811 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 812 dma-names = "rx", "tx"; 813 status = "disabled"; 814 }; 815 816 uart2: serial@30890000 { 817 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 818 reg = <0x30890000 0x10000>; 819 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 821 <&clk IMX8MP_CLK_UART2_ROOT>; 822 clock-names = "ipg", "per"; 823 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 824 dma-names = "rx", "tx"; 825 status = "disabled"; 826 }; 827 828 flexcan1: can@308c0000 { 829 compatible = "fsl,imx8mp-flexcan"; 830 reg = <0x308c0000 0x10000>; 831 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 833 <&clk IMX8MP_CLK_CAN1_ROOT>; 834 clock-names = "ipg", "per"; 835 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 836 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 837 assigned-clock-rates = <40000000>; 838 fsl,clk-source = /bits/ 8 <0>; 839 fsl,stop-mode = <&gpr 0x10 4>; 840 status = "disabled"; 841 }; 842 843 flexcan2: can@308d0000 { 844 compatible = "fsl,imx8mp-flexcan"; 845 reg = <0x308d0000 0x10000>; 846 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 848 <&clk IMX8MP_CLK_CAN2_ROOT>; 849 clock-names = "ipg", "per"; 850 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 851 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 852 assigned-clock-rates = <40000000>; 853 fsl,clk-source = /bits/ 8 <0>; 854 fsl,stop-mode = <&gpr 0x10 5>; 855 status = "disabled"; 856 }; 857 }; 858 859 crypto: crypto@30900000 { 860 compatible = "fsl,sec-v4.0"; 861 #address-cells = <1>; 862 #size-cells = <1>; 863 reg = <0x30900000 0x40000>; 864 ranges = <0 0x30900000 0x40000>; 865 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&clk IMX8MP_CLK_AHB>, 867 <&clk IMX8MP_CLK_IPG_ROOT>; 868 clock-names = "aclk", "ipg"; 869 870 sec_jr0: jr@1000 { 871 compatible = "fsl,sec-v4.0-job-ring"; 872 reg = <0x1000 0x1000>; 873 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 874 status = "disabled"; 875 }; 876 877 sec_jr1: jr@2000 { 878 compatible = "fsl,sec-v4.0-job-ring"; 879 reg = <0x2000 0x1000>; 880 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 881 }; 882 883 sec_jr2: jr@3000 { 884 compatible = "fsl,sec-v4.0-job-ring"; 885 reg = <0x3000 0x1000>; 886 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 887 }; 888 }; 889 890 i2c1: i2c@30a20000 { 891 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 reg = <0x30a20000 0x10000>; 895 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 896 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 897 status = "disabled"; 898 }; 899 900 i2c2: i2c@30a30000 { 901 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 reg = <0x30a30000 0x10000>; 905 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 907 status = "disabled"; 908 }; 909 910 i2c3: i2c@30a40000 { 911 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 reg = <0x30a40000 0x10000>; 915 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 917 status = "disabled"; 918 }; 919 920 i2c4: i2c@30a50000 { 921 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 reg = <0x30a50000 0x10000>; 925 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 927 status = "disabled"; 928 }; 929 930 uart4: serial@30a60000 { 931 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 932 reg = <0x30a60000 0x10000>; 933 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 935 <&clk IMX8MP_CLK_UART4_ROOT>; 936 clock-names = "ipg", "per"; 937 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 938 dma-names = "rx", "tx"; 939 status = "disabled"; 940 }; 941 942 mu: mailbox@30aa0000 { 943 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 944 reg = <0x30aa0000 0x10000>; 945 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 947 #mbox-cells = <2>; 948 }; 949 950 mu2: mailbox@30e60000 { 951 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 952 reg = <0x30e60000 0x10000>; 953 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 954 #mbox-cells = <2>; 955 status = "disabled"; 956 }; 957 958 i2c5: i2c@30ad0000 { 959 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 reg = <0x30ad0000 0x10000>; 963 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 965 status = "disabled"; 966 }; 967 968 i2c6: i2c@30ae0000 { 969 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 reg = <0x30ae0000 0x10000>; 973 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 975 status = "disabled"; 976 }; 977 978 usdhc1: mmc@30b40000 { 979 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 980 reg = <0x30b40000 0x10000>; 981 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&clk IMX8MP_CLK_DUMMY>, 983 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 984 <&clk IMX8MP_CLK_USDHC1_ROOT>; 985 clock-names = "ipg", "ahb", "per"; 986 fsl,tuning-start-tap = <20>; 987 fsl,tuning-step = <2>; 988 bus-width = <4>; 989 status = "disabled"; 990 }; 991 992 usdhc2: mmc@30b50000 { 993 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 994 reg = <0x30b50000 0x10000>; 995 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&clk IMX8MP_CLK_DUMMY>, 997 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 998 <&clk IMX8MP_CLK_USDHC2_ROOT>; 999 clock-names = "ipg", "ahb", "per"; 1000 fsl,tuning-start-tap = <20>; 1001 fsl,tuning-step = <2>; 1002 bus-width = <4>; 1003 status = "disabled"; 1004 }; 1005 1006 usdhc3: mmc@30b60000 { 1007 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1008 reg = <0x30b60000 0x10000>; 1009 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&clk IMX8MP_CLK_DUMMY>, 1011 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1012 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1013 clock-names = "ipg", "ahb", "per"; 1014 fsl,tuning-start-tap = <20>; 1015 fsl,tuning-step = <2>; 1016 bus-width = <4>; 1017 status = "disabled"; 1018 }; 1019 1020 flexspi: spi@30bb0000 { 1021 compatible = "nxp,imx8mp-fspi"; 1022 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1023 reg-names = "fspi_base", "fspi_mmap"; 1024 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1026 <&clk IMX8MP_CLK_QSPI_ROOT>; 1027 clock-names = "fspi_en", "fspi"; 1028 assigned-clock-rates = <80000000>; 1029 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 status = "disabled"; 1033 }; 1034 1035 sdma1: dma-controller@30bd0000 { 1036 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1037 reg = <0x30bd0000 0x10000>; 1038 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1040 <&clk IMX8MP_CLK_AHB>; 1041 clock-names = "ipg", "ahb"; 1042 #dma-cells = <3>; 1043 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1044 }; 1045 1046 fec: ethernet@30be0000 { 1047 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1048 reg = <0x30be0000 0x10000>; 1049 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1054 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1055 <&clk IMX8MP_CLK_ENET_TIMER>, 1056 <&clk IMX8MP_CLK_ENET_REF>, 1057 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1058 clock-names = "ipg", "ahb", "ptp", 1059 "enet_clk_ref", "enet_out"; 1060 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1061 <&clk IMX8MP_CLK_ENET_TIMER>, 1062 <&clk IMX8MP_CLK_ENET_REF>, 1063 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1064 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1065 <&clk IMX8MP_SYS_PLL2_100M>, 1066 <&clk IMX8MP_SYS_PLL2_125M>, 1067 <&clk IMX8MP_SYS_PLL2_50M>; 1068 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1069 fsl,num-tx-queues = <3>; 1070 fsl,num-rx-queues = <3>; 1071 nvmem-cells = <ð_mac1>; 1072 nvmem-cell-names = "mac-address"; 1073 fsl,stop-mode = <&gpr 0x10 3>; 1074 status = "disabled"; 1075 }; 1076 1077 eqos: ethernet@30bf0000 { 1078 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1079 reg = <0x30bf0000 0x10000>; 1080 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1082 interrupt-names = "macirq", "eth_wake_irq"; 1083 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1084 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1085 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1086 <&clk IMX8MP_CLK_ENET_QOS>; 1087 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1088 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1089 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1090 <&clk IMX8MP_CLK_ENET_QOS>; 1091 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1092 <&clk IMX8MP_SYS_PLL2_100M>, 1093 <&clk IMX8MP_SYS_PLL2_125M>; 1094 assigned-clock-rates = <0>, <100000000>, <125000000>; 1095 nvmem-cells = <ð_mac2>; 1096 nvmem-cell-names = "mac-address"; 1097 intf_mode = <&gpr 0x4>; 1098 status = "disabled"; 1099 }; 1100 }; 1101 1102 noc: interconnect@32700000 { 1103 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1104 reg = <0x32700000 0x100000>; 1105 clocks = <&clk IMX8MP_CLK_NOC>; 1106 #interconnect-cells = <1>; 1107 operating-points-v2 = <&noc_opp_table>; 1108 1109 noc_opp_table: opp-table { 1110 compatible = "operating-points-v2"; 1111 1112 opp-200000000 { 1113 opp-hz = /bits/ 64 <200000000>; 1114 }; 1115 1116 opp-1000000000 { 1117 opp-hz = /bits/ 64 <1000000000>; 1118 }; 1119 }; 1120 }; 1121 1122 aips4: bus@32c00000 { 1123 compatible = "fsl,aips-bus", "simple-bus"; 1124 reg = <0x32c00000 0x400000>; 1125 #address-cells = <1>; 1126 #size-cells = <1>; 1127 ranges; 1128 1129 lcdif2: display-controller@32e90000 { 1130 compatible = "fsl,imx8mp-lcdif"; 1131 reg = <0x32e90000 0x238>; 1132 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1134 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1135 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1136 clock-names = "pix", "axi", "disp_axi"; 1137 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1138 <&clk IMX8MP_VIDEO_PLL1>; 1139 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, 1140 <&clk IMX8MP_VIDEO_PLL1_REF_SEL>; 1141 assigned-clock-rates = <0>, <1039500000>; 1142 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1143 status = "disabled"; 1144 1145 port { 1146 lcdif2_to_ldb: endpoint { 1147 remote-endpoint = <&ldb_from_lcdif2>; 1148 }; 1149 }; 1150 }; 1151 1152 media_blk_ctrl: blk-ctrl@32ec0000 { 1153 compatible = "fsl,imx8mp-media-blk-ctrl", 1154 "simple-bus", "syscon"; 1155 reg = <0x32ec0000 0x10000>; 1156 #address-cells = <1>; 1157 #size-cells = <1>; 1158 power-domains = <&pgc_mediamix>, 1159 <&pgc_mipi_phy1>, 1160 <&pgc_mipi_phy1>, 1161 <&pgc_mediamix>, 1162 <&pgc_mediamix>, 1163 <&pgc_mipi_phy2>, 1164 <&pgc_mediamix>, 1165 <&pgc_ispdwp>, 1166 <&pgc_ispdwp>, 1167 <&pgc_mipi_phy2>; 1168 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1169 "lcdif1", "isi", "mipi-csi2", 1170 "lcdif2", "isp", "dwe", 1171 "mipi-dsi2"; 1172 interconnects = 1173 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1174 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1175 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1176 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1177 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1178 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1179 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1180 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1181 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1182 "isi1", "isi2", "isp0", "isp1", 1183 "dwe"; 1184 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1185 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1186 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1187 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1188 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1189 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1190 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1191 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1192 clock-names = "apb", "axi", "cam1", "cam2", 1193 "disp1", "disp2", "isp", "phy"; 1194 1195 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1196 <&clk IMX8MP_CLK_MEDIA_APB>; 1197 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1198 <&clk IMX8MP_SYS_PLL1_800M>; 1199 assigned-clock-rates = <500000000>, <200000000>; 1200 1201 #power-domain-cells = <1>; 1202 1203 lvds_bridge: bridge@5c { 1204 compatible = "fsl,imx8mp-ldb"; 1205 clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1206 clock-names = "ldb"; 1207 reg = <0x5c 0x4>, <0x128 0x4>; 1208 reg-names = "ldb", "lvds"; 1209 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 1210 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 1211 status = "disabled"; 1212 1213 ports { 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 1217 port@0 { 1218 reg = <0>; 1219 1220 ldb_from_lcdif2: endpoint { 1221 remote-endpoint = <&lcdif2_to_ldb>; 1222 }; 1223 }; 1224 1225 port@1 { 1226 reg = <1>; 1227 1228 ldb_lvds_ch0: endpoint { 1229 }; 1230 }; 1231 1232 port@2 { 1233 reg = <2>; 1234 1235 ldb_lvds_ch1: endpoint { 1236 }; 1237 }; 1238 }; 1239 }; 1240 }; 1241 1242 pcie_phy: pcie-phy@32f00000 { 1243 compatible = "fsl,imx8mp-pcie-phy"; 1244 reg = <0x32f00000 0x10000>; 1245 resets = <&src IMX8MP_RESET_PCIEPHY>, 1246 <&src IMX8MP_RESET_PCIEPHY_PERST>; 1247 reset-names = "pciephy", "perst"; 1248 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 1249 #phy-cells = <0>; 1250 status = "disabled"; 1251 }; 1252 1253 hsio_blk_ctrl: blk-ctrl@32f10000 { 1254 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 1255 reg = <0x32f10000 0x24>; 1256 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1257 <&clk IMX8MP_CLK_PCIE_ROOT>; 1258 clock-names = "usb", "pcie"; 1259 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 1260 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 1261 <&pgc_hsiomix>, <&pgc_pcie_phy>; 1262 power-domain-names = "bus", "usb", "usb-phy1", 1263 "usb-phy2", "pcie", "pcie-phy"; 1264 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 1265 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 1266 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 1267 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 1268 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 1269 #power-domain-cells = <1>; 1270 #clock-cells = <0>; 1271 }; 1272 }; 1273 1274 pcie: pcie@33800000 { 1275 compatible = "fsl,imx8mp-pcie"; 1276 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1277 reg-names = "dbi", "config"; 1278 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1279 <&clk IMX8MP_CLK_HSIO_AXI>, 1280 <&clk IMX8MP_CLK_PCIE_ROOT>; 1281 clock-names = "pcie", "pcie_bus", "pcie_aux"; 1282 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 1283 assigned-clock-rates = <10000000>; 1284 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 1285 #address-cells = <3>; 1286 #size-cells = <2>; 1287 device_type = "pci"; 1288 bus-range = <0x00 0xff>; 1289 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1290 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1291 num-lanes = <1>; 1292 num-viewport = <4>; 1293 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1294 interrupt-names = "msi"; 1295 #interrupt-cells = <1>; 1296 interrupt-map-mask = <0 0 0 0x7>; 1297 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1298 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1299 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1300 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1301 fsl,max-link-speed = <3>; 1302 linux,pci-domain = <0>; 1303 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 1304 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 1305 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 1306 reset-names = "apps", "turnoff"; 1307 phys = <&pcie_phy>; 1308 phy-names = "pcie-phy"; 1309 status = "disabled"; 1310 }; 1311 1312 gpu3d: gpu@38000000 { 1313 compatible = "vivante,gc"; 1314 reg = <0x38000000 0x8000>; 1315 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 1317 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 1318 <&clk IMX8MP_CLK_GPU_ROOT>, 1319 <&clk IMX8MP_CLK_GPU_AHB>; 1320 clock-names = "core", "shader", "bus", "reg"; 1321 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 1322 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 1323 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1324 <&clk IMX8MP_SYS_PLL1_800M>; 1325 assigned-clock-rates = <800000000>, <800000000>; 1326 power-domains = <&pgc_gpu3d>; 1327 }; 1328 1329 gpu2d: gpu@38008000 { 1330 compatible = "vivante,gc"; 1331 reg = <0x38008000 0x8000>; 1332 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1333 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 1334 <&clk IMX8MP_CLK_GPU_ROOT>, 1335 <&clk IMX8MP_CLK_GPU_AHB>; 1336 clock-names = "core", "bus", "reg"; 1337 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 1338 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1339 assigned-clock-rates = <800000000>; 1340 power-domains = <&pgc_gpu2d>; 1341 }; 1342 1343 vpu_g1: video-codec@38300000 { 1344 compatible = "nxp,imx8mm-vpu-g1"; 1345 reg = <0x38300000 0x10000>; 1346 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1347 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 1348 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 1349 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 1350 assigned-clock-rates = <600000000>; 1351 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 1352 }; 1353 1354 vpu_g2: video-codec@38310000 { 1355 compatible = "nxp,imx8mq-vpu-g2"; 1356 reg = <0x38310000 0x10000>; 1357 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1358 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 1359 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>; 1360 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 1361 assigned-clock-rates = <500000000>; 1362 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 1363 }; 1364 1365 vpumix_blk_ctrl: blk-ctrl@38330000 { 1366 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 1367 reg = <0x38330000 0x100>; 1368 #power-domain-cells = <1>; 1369 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1370 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 1371 power-domain-names = "bus", "g1", "g2", "vc8000e"; 1372 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 1373 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 1374 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 1375 clock-names = "g1", "g2", "vc8000e"; 1376 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>; 1377 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 1378 assigned-clock-rates = <600000000>, <600000000>; 1379 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 1380 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 1381 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 1382 interconnect-names = "g1", "g2", "vc8000e"; 1383 }; 1384 1385 gic: interrupt-controller@38800000 { 1386 compatible = "arm,gic-v3"; 1387 reg = <0x38800000 0x10000>, 1388 <0x38880000 0xc0000>; 1389 #interrupt-cells = <3>; 1390 interrupt-controller; 1391 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1392 interrupt-parent = <&gic>; 1393 }; 1394 1395 edacmc: memory-controller@3d400000 { 1396 compatible = "snps,ddrc-3.80a"; 1397 reg = <0x3d400000 0x400000>; 1398 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1399 }; 1400 1401 ddr-pmu@3d800000 { 1402 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1403 reg = <0x3d800000 0x400000>; 1404 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1405 }; 1406 1407 usb3_phy0: usb-phy@381f0040 { 1408 compatible = "fsl,imx8mp-usb-phy"; 1409 reg = <0x381f0040 0x40>; 1410 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1411 clock-names = "phy"; 1412 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1413 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1414 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 1415 #phy-cells = <0>; 1416 status = "disabled"; 1417 }; 1418 1419 usb3_0: usb@32f10100 { 1420 compatible = "fsl,imx8mp-dwc3"; 1421 reg = <0x32f10100 0x8>, 1422 <0x381f0000 0x20>; 1423 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1424 <&clk IMX8MP_CLK_USB_SUSP>; 1425 clock-names = "hsio", "suspend"; 1426 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1427 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 1428 #address-cells = <1>; 1429 #size-cells = <1>; 1430 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 1431 ranges; 1432 status = "disabled"; 1433 1434 usb_dwc3_0: usb@38100000 { 1435 compatible = "snps,dwc3"; 1436 reg = <0x38100000 0x10000>; 1437 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1438 <&clk IMX8MP_CLK_USB_CORE_REF>, 1439 <&clk IMX8MP_CLK_USB_SUSP>; 1440 clock-names = "bus_early", "ref", "suspend"; 1441 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1442 phys = <&usb3_phy0>, <&usb3_phy0>; 1443 phy-names = "usb2-phy", "usb3-phy"; 1444 snps,gfladj-refclk-lpm-sel-quirk; 1445 }; 1446 1447 }; 1448 1449 usb3_phy1: usb-phy@382f0040 { 1450 compatible = "fsl,imx8mp-usb-phy"; 1451 reg = <0x382f0040 0x40>; 1452 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 1453 clock-names = "phy"; 1454 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 1455 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 1456 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 1457 #phy-cells = <0>; 1458 status = "disabled"; 1459 }; 1460 1461 usb3_1: usb@32f10108 { 1462 compatible = "fsl,imx8mp-dwc3"; 1463 reg = <0x32f10108 0x8>, 1464 <0x382f0000 0x20>; 1465 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 1466 <&clk IMX8MP_CLK_USB_SUSP>; 1467 clock-names = "hsio", "suspend"; 1468 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1469 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 1470 #address-cells = <1>; 1471 #size-cells = <1>; 1472 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 1473 ranges; 1474 status = "disabled"; 1475 1476 usb_dwc3_1: usb@38200000 { 1477 compatible = "snps,dwc3"; 1478 reg = <0x38200000 0x10000>; 1479 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 1480 <&clk IMX8MP_CLK_USB_CORE_REF>, 1481 <&clk IMX8MP_CLK_USB_SUSP>; 1482 clock-names = "bus_early", "ref", "suspend"; 1483 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1484 phys = <&usb3_phy1>, <&usb3_phy1>; 1485 phy-names = "usb2-phy", "usb3-phy"; 1486 snps,gfladj-refclk-lpm-sel-quirk; 1487 }; 1488 }; 1489 1490 dsp: dsp@3b6e8000 { 1491 compatible = "fsl,imx8mp-dsp"; 1492 reg = <0x3b6e8000 0x88000>; 1493 mbox-names = "txdb0", "txdb1", 1494 "rxdb0", "rxdb1"; 1495 mboxes = <&mu2 2 0>, <&mu2 2 1>, 1496 <&mu2 3 0>, <&mu2 3 1>; 1497 memory-region = <&dsp_reserved>; 1498 status = "disabled"; 1499 }; 1500 }; 1501}; 1502