1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mp.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart3; 13 }; 14 15 aliases { 16 /* Ethernet aliases to ensure correct MAC addresses */ 17 ethernet0 = &eqos; 18 ethernet1 = &fec; 19 rtc0 = &rtc_i2c; 20 rtc1 = &snvs_rtc; 21 }; 22 23 backlight: backlight { 24 compatible = "pwm-backlight"; 25 brightness-levels = <0 45 63 88 119 158 203 255>; 26 default-brightness-level = <4>; 27 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 28 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 31 power-supply = <®_3p3v>; 32 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 33 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; 34 status = "disabled"; 35 }; 36 37 backlight_mezzanine: backlight-mezzanine { 38 compatible = "pwm-backlight"; 39 brightness-levels = <0 45 63 88 119 158 203 255>; 40 default-brightness-level = <4>; 41 /* Verdin GPIO 4 (SODIMM 212) */ 42 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 43 /* Verdin PWM_2 (SODIMM 16) */ 44 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>; 45 status = "disabled"; 46 }; 47 48 gpio-keys { 49 compatible = "gpio-keys"; 50 pinctrl-names = "default"; 51 pinctrl-0 = <&pinctrl_gpio_keys>; 52 53 key-wakeup { 54 debounce-interval = <10>; 55 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 56 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 57 label = "Wake-Up"; 58 linux,code = <KEY_WAKEUP>; 59 wakeup-source; 60 }; 61 }; 62 63 /* Carrier Board Supplies */ 64 reg_1p8v: regulator-1p8v { 65 compatible = "regulator-fixed"; 66 regulator-max-microvolt = <1800000>; 67 regulator-min-microvolt = <1800000>; 68 regulator-name = "+V1.8_SW"; 69 }; 70 71 reg_3p3v: regulator-3p3v { 72 compatible = "regulator-fixed"; 73 regulator-max-microvolt = <3300000>; 74 regulator-min-microvolt = <3300000>; 75 regulator-name = "+V3.3_SW"; 76 }; 77 78 reg_5p0v: regulator-5p0v { 79 compatible = "regulator-fixed"; 80 regulator-max-microvolt = <5000000>; 81 regulator-min-microvolt = <5000000>; 82 regulator-name = "+V5_SW"; 83 }; 84 85 /* Non PMIC On-module Supplies */ 86 reg_module_eth1phy: regulator-module-eth1phy { 87 compatible = "regulator-fixed"; 88 enable-active-high; 89 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 90 off-on-delay = <500000>; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_reg_eth>; 93 regulator-always-on; 94 regulator-boot-on; 95 regulator-max-microvolt = <3300000>; 96 regulator-min-microvolt = <3300000>; 97 regulator-name = "On-module +V3.3_ETH"; 98 startup-delay-us = <200000>; 99 vin-supply = <®_vdd_3v3>; 100 }; 101 102 reg_usb1_vbus: regulator-usb1-vbus { 103 compatible = "regulator-fixed"; 104 enable-active-high; 105 /* Verdin USB_1_EN (SODIMM 155) */ 106 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_usb1_vbus>; 109 regulator-max-microvolt = <5000000>; 110 regulator-min-microvolt = <5000000>; 111 regulator-name = "USB_1_EN"; 112 }; 113 114 reg_usb2_vbus: regulator-usb2-vbus { 115 compatible = "regulator-fixed"; 116 enable-active-high; 117 /* Verdin USB_2_EN (SODIMM 185) */ 118 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_usb2_vbus>; 121 regulator-max-microvolt = <5000000>; 122 regulator-min-microvolt = <5000000>; 123 regulator-name = "USB_2_EN"; 124 }; 125 126 reg_usdhc2_vmmc: regulator-usdhc2 { 127 compatible = "regulator-fixed"; 128 enable-active-high; 129 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 130 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; 131 off-on-delay = <100000>; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 134 regulator-max-microvolt = <3300000>; 135 regulator-min-microvolt = <3300000>; 136 regulator-name = "+V3.3_SD"; 137 startup-delay-us = <2000>; 138 }; 139 140 reserved-memory { 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 145 /* Use the kernel configuration settings instead */ 146 /delete-node/ linux,cma; 147 }; 148}; 149 150&A53_0 { 151 cpu-supply = <®_vdd_arm>; 152}; 153 154&A53_1 { 155 cpu-supply = <®_vdd_arm>; 156}; 157 158&A53_2 { 159 cpu-supply = <®_vdd_arm>; 160}; 161 162&A53_3 { 163 cpu-supply = <®_vdd_arm>; 164}; 165 166&cpu_alert0 { 167 temperature = <95000>; 168}; 169 170&cpu_crit0 { 171 temperature = <105000>; 172}; 173 174/* Verdin SPI_1 */ 175&ecspi1 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_ecspi1>; 181}; 182 183/* Verdin ETH_1 (On-module PHY) */ 184&eqos { 185 phy-handle = <ðphy0>; 186 phy-mode = "rgmii-id"; 187 phy-supply = <®_module_eth1phy>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_eqos>; 190 snps,force_thresh_dma_mode; 191 snps,mtl-rx-config = <&mtl_rx_setup>; 192 snps,mtl-tx-config = <&mtl_tx_setup>; 193 194 mdio { 195 compatible = "snps,dwmac-mdio"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 ethphy0: ethernet-phy@7 { 200 compatible = "ethernet-phy-ieee802.3-c22"; 201 eee-broken-100tx; 202 eee-broken-1000t; 203 interrupt-parent = <&gpio1>; 204 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 205 micrel,led-mode = <0>; 206 reg = <7>; 207 }; 208 }; 209 210 mtl_rx_setup: rx-queues-config { 211 snps,rx-queues-to-use = <5>; 212 snps,rx-sched-sp; 213 214 queue0 { 215 snps,dcb-algorithm; 216 snps,priority = <0x1>; 217 snps,map-to-dma-channel = <0>; 218 }; 219 220 queue1 { 221 snps,dcb-algorithm; 222 snps,priority = <0x2>; 223 snps,map-to-dma-channel = <1>; 224 }; 225 226 queue2 { 227 snps,dcb-algorithm; 228 snps,priority = <0x4>; 229 snps,map-to-dma-channel = <2>; 230 }; 231 232 queue3 { 233 snps,dcb-algorithm; 234 snps,priority = <0x8>; 235 snps,map-to-dma-channel = <3>; 236 }; 237 238 queue4 { 239 snps,dcb-algorithm; 240 snps,priority = <0xf0>; 241 snps,map-to-dma-channel = <4>; 242 }; 243 }; 244 245 mtl_tx_setup: tx-queues-config { 246 snps,tx-queues-to-use = <5>; 247 snps,tx-sched-sp; 248 249 queue0 { 250 snps,dcb-algorithm; 251 snps,priority = <0x1>; 252 }; 253 254 queue1 { 255 snps,dcb-algorithm; 256 snps,priority = <0x2>; 257 }; 258 259 queue2 { 260 snps,dcb-algorithm; 261 snps,priority = <0x4>; 262 }; 263 264 queue3 { 265 snps,dcb-algorithm; 266 snps,priority = <0x8>; 267 }; 268 269 queue4 { 270 snps,dcb-algorithm; 271 snps,priority = <0xf0>; 272 }; 273 }; 274}; 275 276/* Verdin ETH_2_RGMII */ 277&fec { 278 fsl,magic-packet; 279 phy-handle = <ðphy1>; 280 phy-mode = "rgmii-id"; 281 pinctrl-names = "default", "sleep"; 282 pinctrl-0 = <&pinctrl_fec>; 283 pinctrl-1 = <&pinctrl_fec_sleep>; 284 285 mdio { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 289 ethphy1: ethernet-phy@7 { 290 compatible = "ethernet-phy-ieee802.3-c22"; 291 interrupt-parent = <&gpio4>; 292 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 293 micrel,led-mode = <0>; 294 reg = <7>; 295 }; 296 }; 297}; 298 299/* Verdin CAN_1 */ 300&flexcan1 { 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_flexcan1>; 303 status = "disabled"; 304}; 305 306/* Verdin CAN_2 */ 307&flexcan2 { 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pinctrl_flexcan2>; 310 status = "disabled"; 311}; 312 313/* Verdin QSPI_1 */ 314&flexspi { 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_flexspi0>; 317}; 318 319&gpio1 { 320 gpio-line-names = "SODIMM_206", 321 "SODIMM_208", 322 "", 323 "", 324 "", 325 "SODIMM_210", 326 "SODIMM_212", 327 "SODIMM_216", 328 "SODIMM_218", 329 "", 330 "", 331 "SODIMM_16", 332 "SODIMM_155", 333 "SODIMM_157", 334 "SODIMM_185", 335 "SODIMM_91"; 336}; 337 338&gpio2 { 339 gpio-line-names = "", 340 "", 341 "", 342 "", 343 "", 344 "", 345 "SODIMM_143", 346 "SODIMM_141", 347 "", 348 "", 349 "SODIMM_161", 350 "", 351 "SODIMM_84", 352 "SODIMM_78", 353 "SODIMM_74", 354 "SODIMM_80", 355 "SODIMM_82", 356 "SODIMM_70", 357 "SODIMM_72"; 358}; 359 360&gpio3 { 361 gpio-line-names = "SODIMM_52", 362 "SODIMM_54", 363 "", 364 "", 365 "", 366 "", 367 "SODIMM_56", 368 "SODIMM_58", 369 "SODIMM_60", 370 "SODIMM_62", 371 "", 372 "", 373 "", 374 "", 375 "SODIMM_66", 376 "", 377 "SODIMM_64", 378 "", 379 "", 380 "SODIMM_34", 381 "SODIMM_19", 382 "", 383 "SODIMM_32", 384 "", 385 "", 386 "SODIMM_30", 387 "SODIMM_59", 388 "SODIMM_57", 389 "SODIMM_63", 390 "SODIMM_61"; 391}; 392 393&gpio4 { 394 gpio-line-names = "SODIMM_252", 395 "SODIMM_222", 396 "SODIMM_36", 397 "SODIMM_220", 398 "SODIMM_193", 399 "SODIMM_191", 400 "SODIMM_201", 401 "SODIMM_203", 402 "SODIMM_205", 403 "SODIMM_207", 404 "SODIMM_199", 405 "SODIMM_197", 406 "SODIMM_221", 407 "SODIMM_219", 408 "SODIMM_217", 409 "SODIMM_215", 410 "SODIMM_211", 411 "SODIMM_213", 412 "SODIMM_189", 413 "SODIMM_244", 414 "SODIMM_38", 415 "", 416 "SODIMM_76", 417 "SODIMM_135", 418 "SODIMM_133", 419 "SODIMM_17", 420 "SODIMM_24", 421 "SODIMM_26", 422 "SODIMM_21", 423 "SODIMM_256", 424 "SODIMM_48", 425 "SODIMM_44"; 426 427 ctrl-sleep-moci-hog { 428 gpio-hog; 429 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 430 gpios = <29 GPIO_ACTIVE_HIGH>; 431 line-name = "CTRL_SLEEP_MOCI#"; 432 output-high; 433 pinctrl-names = "default"; 434 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 435 }; 436}; 437 438/* On-module I2C */ 439&i2c1 { 440 clock-frequency = <400000>; 441 pinctrl-names = "default", "gpio"; 442 pinctrl-0 = <&pinctrl_i2c1>; 443 pinctrl-1 = <&pinctrl_i2c1_gpio>; 444 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 445 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 446 status = "okay"; 447 448 pca9450: pmic@25 { 449 compatible = "nxp,pca9450c"; 450 interrupt-parent = <&gpio1>; 451 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 452 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_pmic>; 455 reg = <0x25>; 456 457 /* 458 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the 459 * I2C level shifter for the TLA2024 ADC behind this PMIC. 460 */ 461 462 regulators { 463 BUCK1 { 464 regulator-always-on; 465 regulator-boot-on; 466 regulator-max-microvolt = <1000000>; 467 regulator-min-microvolt = <720000>; 468 regulator-name = "On-module +VDD_SOC (BUCK1)"; 469 regulator-ramp-delay = <3125>; 470 }; 471 472 reg_vdd_arm: BUCK2 { 473 nxp,dvs-run-voltage = <950000>; 474 nxp,dvs-standby-voltage = <850000>; 475 regulator-always-on; 476 regulator-boot-on; 477 regulator-max-microvolt = <1025000>; 478 regulator-min-microvolt = <720000>; 479 regulator-name = "On-module +VDD_ARM (BUCK2)"; 480 regulator-ramp-delay = <3125>; 481 }; 482 483 reg_vdd_3v3: BUCK4 { 484 regulator-always-on; 485 regulator-boot-on; 486 regulator-max-microvolt = <3300000>; 487 regulator-min-microvolt = <3300000>; 488 regulator-name = "On-module +V3.3 (BUCK4)"; 489 }; 490 491 reg_vdd_1v8: BUCK5 { 492 regulator-always-on; 493 regulator-boot-on; 494 regulator-max-microvolt = <1800000>; 495 regulator-min-microvolt = <1800000>; 496 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 497 }; 498 499 BUCK6 { 500 regulator-always-on; 501 regulator-boot-on; 502 regulator-max-microvolt = <1155000>; 503 regulator-min-microvolt = <1045000>; 504 regulator-name = "On-module +VDD_DDR (BUCK6)"; 505 }; 506 507 LDO1 { 508 regulator-always-on; 509 regulator-boot-on; 510 regulator-max-microvolt = <1950000>; 511 regulator-min-microvolt = <1650000>; 512 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 513 }; 514 515 LDO2 { 516 regulator-always-on; 517 regulator-boot-on; 518 regulator-max-microvolt = <1150000>; 519 regulator-min-microvolt = <800000>; 520 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 521 }; 522 523 LDO3 { 524 regulator-always-on; 525 regulator-boot-on; 526 regulator-max-microvolt = <1800000>; 527 regulator-min-microvolt = <1800000>; 528 regulator-name = "On-module +V1.8A (LDO3)"; 529 }; 530 531 LDO4 { 532 regulator-always-on; 533 regulator-boot-on; 534 regulator-max-microvolt = <3300000>; 535 regulator-min-microvolt = <3300000>; 536 regulator-name = "On-module +V3.3_ADC (LDO4)"; 537 }; 538 539 LDO5 { 540 regulator-max-microvolt = <3300000>; 541 regulator-min-microvolt = <1800000>; 542 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 543 }; 544 }; 545 }; 546 547 rtc_i2c: rtc@32 { 548 compatible = "epson,rx8130"; 549 reg = <0x32>; 550 }; 551 552 /* On-module temperature sensor */ 553 hwmon_temp_module: sensor@48 { 554 compatible = "ti,tmp1075"; 555 reg = <0x48>; 556 vs-supply = <®_vdd_1v8>; 557 }; 558 559 adc@49 { 560 compatible = "ti,ads1015"; 561 reg = <0x49>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 565 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 566 channel@0 { 567 reg = <0>; 568 ti,datarate = <4>; 569 ti,gain = <2>; 570 }; 571 572 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 573 channel@1 { 574 reg = <1>; 575 ti,datarate = <4>; 576 ti,gain = <2>; 577 }; 578 579 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 580 channel@2 { 581 reg = <2>; 582 ti,datarate = <4>; 583 ti,gain = <2>; 584 }; 585 586 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 587 channel@3 { 588 reg = <3>; 589 ti,datarate = <4>; 590 ti,gain = <2>; 591 }; 592 593 /* Verdin I2C_1 ADC_4 */ 594 channel@4 { 595 reg = <4>; 596 ti,datarate = <4>; 597 ti,gain = <2>; 598 }; 599 600 /* Verdin I2C_1 ADC_3 */ 601 channel@5 { 602 reg = <5>; 603 ti,datarate = <4>; 604 ti,gain = <2>; 605 }; 606 607 /* Verdin I2C_1 ADC_2 */ 608 channel@6 { 609 reg = <6>; 610 ti,datarate = <4>; 611 ti,gain = <2>; 612 }; 613 614 /* Verdin I2C_1 ADC_1 */ 615 channel@7 { 616 reg = <7>; 617 ti,datarate = <4>; 618 ti,gain = <2>; 619 }; 620 }; 621 622 eeprom@50 { 623 compatible = "st,24c02"; 624 pagesize = <16>; 625 reg = <0x50>; 626 }; 627}; 628 629/* Verdin I2C_2_DSI */ 630&i2c2 { 631 /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ 632 clock-frequency = <10000>; 633 pinctrl-names = "default", "gpio"; 634 pinctrl-0 = <&pinctrl_i2c2>; 635 pinctrl-1 = <&pinctrl_i2c2_gpio>; 636 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 637 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 638 639 atmel_mxt_ts_mezzanine: touch-mezzanine@4a { 640 compatible = "atmel,maxtouch"; 641 /* Verdin GPIO_3 (SODIMM 210) */ 642 interrupt-parent = <&gpio1>; 643 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 644 reg = <0x4a>; 645 /* Verdin GPIO_2 (SODIMM 208) */ 646 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 647 status = "disabled"; 648 }; 649}; 650 651/* TODO: Verdin I2C_3_HDMI */ 652 653/* Verdin I2C_4_CSI */ 654&i2c3 { 655 clock-frequency = <400000>; 656 pinctrl-names = "default", "gpio"; 657 pinctrl-0 = <&pinctrl_i2c3>; 658 pinctrl-1 = <&pinctrl_i2c3_gpio>; 659 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 660 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 661}; 662 663/* Verdin I2C_1 */ 664&i2c4 { 665 clock-frequency = <400000>; 666 pinctrl-names = "default", "gpio"; 667 pinctrl-0 = <&pinctrl_i2c4>; 668 pinctrl-1 = <&pinctrl_i2c4_gpio>; 669 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 670 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 671 672 gpio_expander_21: gpio-expander@21 { 673 compatible = "nxp,pcal6416"; 674 #gpio-cells = <2>; 675 gpio-controller; 676 reg = <0x21>; 677 vcc-supply = <®_3p3v>; 678 status = "disabled"; 679 }; 680 681 lvds_ti_sn65dsi84: bridge@2c { 682 compatible = "ti,sn65dsi84"; 683 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 684 /* Verdin GPIO_10_DSI (SODIMM 21) */ 685 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 686 pinctrl-names = "default"; 687 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 688 reg = <0x2c>; 689 status = "disabled"; 690 }; 691 692 /* Current measurement into module VCC */ 693 hwmon: hwmon@40 { 694 compatible = "ti,ina219"; 695 reg = <0x40>; 696 shunt-resistor = <10000>; 697 status = "disabled"; 698 }; 699 700 hdmi_lontium_lt8912: hdmi@48 { 701 compatible = "lontium,lt8912b"; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; 704 reg = <0x48>; 705 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 706 /* Verdin GPIO_10_DSI (SODIMM 21) */ 707 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 708 status = "disabled"; 709 }; 710 711 atmel_mxt_ts: touch@4a { 712 compatible = "atmel,maxtouch"; 713 /* 714 * Verdin GPIO_9_DSI 715 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 716 */ 717 interrupt-parent = <&gpio4>; 718 interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 721 reg = <0x4a>; 722 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 723 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 724 status = "disabled"; 725 }; 726 727 /* Temperature sensor on carrier board */ 728 hwmon_temp: sensor@4f { 729 compatible = "ti,tmp75c"; 730 reg = <0x4f>; 731 status = "disabled"; 732 }; 733 734 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 735 eeprom_display_adapter: eeprom@50 { 736 compatible = "st,24c02"; 737 pagesize = <16>; 738 reg = <0x50>; 739 status = "disabled"; 740 }; 741 742 /* EEPROM on carrier board */ 743 eeprom_carrier_board: eeprom@57 { 744 compatible = "st,24c02"; 745 pagesize = <16>; 746 reg = <0x57>; 747 status = "disabled"; 748 }; 749}; 750 751/* TODO: Verdin PCIE_1 */ 752 753/* Verdin PWM_1 */ 754&pwm1 { 755 pinctrl-names = "default"; 756 pinctrl-0 = <&pinctrl_pwm_1>; 757 #pwm-cells = <3>; 758}; 759 760/* Verdin PWM_2 */ 761&pwm2 { 762 pinctrl-names = "default"; 763 pinctrl-0 = <&pinctrl_pwm_2>; 764 #pwm-cells = <3>; 765}; 766 767/* Verdin PWM_3_DSI */ 768&pwm3 { 769 pinctrl-names = "default"; 770 pinctrl-0 = <&pinctrl_pwm_3>; 771 #pwm-cells = <3>; 772}; 773 774/* TODO: Verdin I2S_1 */ 775 776/* TODO: Verdin I2S_2 */ 777 778&snvs_pwrkey { 779 status = "okay"; 780}; 781 782/* Verdin UART_1 */ 783&uart1 { 784 pinctrl-names = "default"; 785 pinctrl-0 = <&pinctrl_uart1>; 786 uart-has-rtscts; 787}; 788 789/* Verdin UART_2 */ 790&uart2 { 791 pinctrl-names = "default"; 792 pinctrl-0 = <&pinctrl_uart2>; 793 uart-has-rtscts; 794}; 795 796/* Verdin UART_3, used as the Linux Console */ 797&uart3 { 798 pinctrl-names = "default"; 799 pinctrl-0 = <&pinctrl_uart3>; 800}; 801 802/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */ 803&uart4 { 804 pinctrl-names = "default"; 805 pinctrl-0 = <&pinctrl_uart4>; 806}; 807 808/* Verdin USB_1 */ 809&usb3_0 { 810 fsl,disable-port-power-control; 811 fsl,over-current-active-low; 812 pinctrl-names = "default"; 813 pinctrl-0 = <&pinctrl_usb_1_oc_n>; 814}; 815 816&usb_dwc3_0 { 817 /* dual role only, not full featured OTG */ 818 adp-disable; 819 dr_mode = "otg"; 820 hnp-disable; 821 maximum-speed = "high-speed"; 822 role-switch-default-mode = "peripheral"; 823 srp-disable; 824 usb-role-switch; 825 826 connector { 827 compatible = "gpio-usb-b-connector", "usb-b-connector"; 828 id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 829 label = "Type-C"; 830 pinctrl-names = "default"; 831 pinctrl-0 = <&pinctrl_usb_1_id>; 832 self-powered; 833 type = "micro"; 834 vbus-supply = <®_usb1_vbus>; 835 }; 836}; 837 838/* Verdin USB_2 */ 839&usb3_1 { 840 fsl,disable-port-power-control; 841}; 842 843&usb3_phy1 { 844 vbus-supply = <®_usb2_vbus>; 845}; 846 847&usb_dwc3_1 { 848 dr_mode = "host"; 849}; 850 851/* Verdin SD_1 */ 852&usdhc2 { 853 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 854 assigned-clock-rates = <400000000>; 855 bus-width = <4>; 856 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 857 disable-wp; 858 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 859 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 860 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 861 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 862 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 863 vmmc-supply = <®_usdhc2_vmmc>; 864}; 865 866/* On-module eMMC */ 867&usdhc3 { 868 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; 869 assigned-clock-rates = <400000000>; 870 bus-width = <8>; 871 non-removable; 872 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 873 pinctrl-0 = <&pinctrl_usdhc3>; 874 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 875 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 876 status = "okay"; 877}; 878 879&wdog1 { 880 fsl,ext-reset-output; 881 pinctrl-names = "default"; 882 pinctrl-0 = <&pinctrl_wdog>; 883 status = "okay"; 884}; 885 886&iomuxc { 887 pinctrl_bt_uart: btuartgrp { 888 fsl,pins = 889 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>, 890 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>, 891 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>, 892 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>; 893 }; 894 895 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 896 fsl,pins = 897 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */ 898 }; 899 900 pinctrl_ecspi1: ecspi1grp { 901 fsl,pins = 902 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */ 903 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */ 904 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */ 905 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */ 906 }; 907 908 /* Connection On Board PHY */ 909 pinctrl_eqos: eqosgrp { 910 fsl,pins = 911 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>, 912 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>, 913 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>, 914 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>, 915 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>, 916 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>, 917 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>, 918 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>, 919 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>, 920 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>, 921 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>, 922 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>, 923 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>, 924 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>; 925 }; 926 927 /* ETH_INT# shared with TPM_INT# (usually N/A) */ 928 pinctrl_eth_tpm_int: ethtpmintgrp { 929 fsl,pins = 930 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>; 931 }; 932 933 /* Connection Carrier Board PHY ETH_2 */ 934 pinctrl_fec: fecgrp { 935 fsl,pins = 936 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ 937 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ 938 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ 939 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ 940 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ 941 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ 942 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ 943 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ 944 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */ 945 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */ 946 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */ 947 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */ 948 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */ 949 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */ 950 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */ 951 }; 952 953 pinctrl_fec_sleep: fecsleepgrp { 954 fsl,pins = 955 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ 956 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ 957 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ 958 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ 959 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ 960 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ 961 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ 962 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ 963 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */ 964 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */ 965 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */ 966 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */ 967 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */ 968 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */ 969 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */ 970 }; 971 972 pinctrl_flexcan1: flexcan1grp { 973 fsl,pins = 974 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */ 975 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */ 976 }; 977 978 pinctrl_flexcan2: flexcan2grp { 979 fsl,pins = 980 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */ 981 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */ 982 }; 983 984 pinctrl_flexspi0: flexspi0grp { 985 fsl,pins = 986 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */ 987 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */ 988 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */ 989 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */ 990 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */ 991 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */ 992 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */ 993 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */ 994 }; 995 996 pinctrl_gpio1: gpio1grp { 997 fsl,pins = 998 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */ 999 }; 1000 1001 pinctrl_gpio2: gpio2grp { 1002 fsl,pins = 1003 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */ 1004 }; 1005 1006 pinctrl_gpio3: gpio3grp { 1007 fsl,pins = 1008 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */ 1009 }; 1010 1011 pinctrl_gpio4: gpio4grp { 1012 fsl,pins = 1013 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */ 1014 }; 1015 1016 pinctrl_gpio5: gpio5grp { 1017 fsl,pins = 1018 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */ 1019 }; 1020 1021 pinctrl_gpio6: gpio6grp { 1022 fsl,pins = 1023 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */ 1024 }; 1025 1026 pinctrl_gpio7: gpio7grp { 1027 fsl,pins = 1028 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */ 1029 }; 1030 1031 pinctrl_gpio8: gpio8grp { 1032 fsl,pins = 1033 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */ 1034 }; 1035 1036 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 1037 pinctrl_gpio_9_dsi: gpio9dsigrp { 1038 fsl,pins = 1039 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */ 1040 }; 1041 1042 /* Verdin GPIO_10_DSI */ 1043 pinctrl_gpio_10_dsi: gpio10dsigrp { 1044 fsl,pins = 1045 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */ 1046 }; 1047 1048 /* Non-wifi MSP usage only */ 1049 pinctrl_gpio_hog1: gpiohog1grp { 1050 fsl,pins = 1051 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */ 1052 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */ 1053 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */ 1054 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */ 1055 }; 1056 1057 /* USB_2_OC# */ 1058 pinctrl_gpio_hog2: gpiohog2grp { 1059 fsl,pins = 1060 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */ 1061 }; 1062 1063 pinctrl_gpio_hog3: gpiohog3grp { 1064 fsl,pins = 1065 /* CSI_1_MCLK */ 1066 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */ 1067 }; 1068 1069 /* Wifi usage only */ 1070 pinctrl_gpio_hog4: gpiohog4grp { 1071 fsl,pins = 1072 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */ 1073 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */ 1074 }; 1075 1076 pinctrl_gpio_keys: gpiokeysgrp { 1077 fsl,pins = 1078 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */ 1079 }; 1080 1081 pinctrl_hdmi_hog: hdmihoggrp { 1082 fsl,pins = 1083 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */ 1084 <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */ 1085 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */ 1086 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */ 1087 }; 1088 1089 /* On-module I2C */ 1090 pinctrl_i2c1: i2c1grp { 1091 fsl,pins = 1092 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */ 1093 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */ 1094 }; 1095 1096 pinctrl_i2c1_gpio: i2c1gpiogrp { 1097 fsl,pins = 1098 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */ 1099 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */ 1100 }; 1101 1102 /* Verdin I2C_2_DSI */ 1103 pinctrl_i2c2: i2c2grp { 1104 fsl,pins = 1105 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */ 1106 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */ 1107 }; 1108 1109 pinctrl_i2c2_gpio: i2c2gpiogrp { 1110 fsl,pins = 1111 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */ 1112 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */ 1113 }; 1114 1115 /* Verdin I2C_4_CSI */ 1116 pinctrl_i2c3: i2c3grp { 1117 fsl,pins = 1118 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */ 1119 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */ 1120 }; 1121 1122 pinctrl_i2c3_gpio: i2c3gpiogrp { 1123 fsl,pins = 1124 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */ 1125 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */ 1126 }; 1127 1128 /* Verdin I2C_1 */ 1129 pinctrl_i2c4: i2c4grp { 1130 fsl,pins = 1131 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */ 1132 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */ 1133 }; 1134 1135 pinctrl_i2c4_gpio: i2c4gpiogrp { 1136 fsl,pins = 1137 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */ 1138 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */ 1139 }; 1140 1141 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1142 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1143 fsl,pins = 1144 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */ 1145 }; 1146 1147 /* Verdin I2S_2_D_OUT shared with SAI3 */ 1148 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1149 fsl,pins = 1150 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */ 1151 }; 1152 1153 pinctrl_pcie: pciegrp { 1154 fsl,pins = 1155 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */ 1156 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */ 1157 }; 1158 1159 pinctrl_pmic: pmicirqgrp { 1160 fsl,pins = 1161 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */ 1162 }; 1163 1164 pinctrl_pwm_1: pwm1grp { 1165 fsl,pins = 1166 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */ 1167 }; 1168 1169 pinctrl_pwm_2: pwm2grp { 1170 fsl,pins = 1171 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */ 1172 }; 1173 1174 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */ 1175 pinctrl_pwm_3: pwm3grp { 1176 fsl,pins = 1177 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */ 1178 }; 1179 1180 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */ 1181 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp { 1182 fsl,pins = 1183 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */ 1184 }; 1185 1186 pinctrl_reg_eth: regethgrp { 1187 fsl,pins = 1188 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */ 1189 }; 1190 1191 pinctrl_sai1: sai1grp { 1192 fsl,pins = 1193 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */ 1194 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */ 1195 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */ 1196 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */ 1197 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */ 1198 }; 1199 1200 pinctrl_sai3: sai3grp { 1201 fsl,pins = 1202 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */ 1203 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */ 1204 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */ 1205 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */ 1206 }; 1207 1208 pinctrl_uart1: uart1grp { 1209 fsl,pins = 1210 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */ 1211 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */ 1212 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */ 1213 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */ 1214 }; 1215 1216 pinctrl_uart2: uart2grp { 1217 fsl,pins = 1218 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */ 1219 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */ 1220 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */ 1221 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */ 1222 }; 1223 1224 pinctrl_uart3: uart3grp { 1225 fsl,pins = 1226 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */ 1227 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */ 1228 }; 1229 1230 /* Non-wifi usage only */ 1231 pinctrl_uart4: uart4grp { 1232 fsl,pins = 1233 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */ 1234 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */ 1235 }; 1236 1237 pinctrl_usb1_vbus: usb1vbusgrp { 1238 fsl,pins = 1239 <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */ 1240 }; 1241 1242 /* USB_1_ID */ 1243 pinctrl_usb_1_id: usb1idgrp { 1244 fsl,pins = 1245 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */ 1246 }; 1247 1248 /* USB_1_OC# */ 1249 pinctrl_usb_1_oc_n: usb1ocngrp { 1250 fsl,pins = 1251 <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */ 1252 }; 1253 1254 pinctrl_usb2_vbus: usb2vbusgrp { 1255 fsl,pins = 1256 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */ 1257 }; 1258 1259 /* On-module Wi-Fi */ 1260 pinctrl_usdhc1: usdhc1grp { 1261 fsl,pins = 1262 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, 1263 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, 1264 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, 1265 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, 1266 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, 1267 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; 1268 }; 1269 1270 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1271 fsl,pins = 1272 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, 1273 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, 1274 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, 1275 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, 1276 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, 1277 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; 1278 }; 1279 1280 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1281 fsl,pins = 1282 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, 1283 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, 1284 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, 1285 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, 1286 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, 1287 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; 1288 }; 1289 1290 pinctrl_usdhc2_cd: usdhc2cdgrp { 1291 fsl,pins = 1292 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */ 1293 }; 1294 1295 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1296 fsl,pins = 1297 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */ 1298 }; 1299 1300 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1301 fsl,pins = 1302 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */ 1303 }; 1304 1305 pinctrl_usdhc2: usdhc2grp { 1306 fsl,pins = 1307 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */ 1308 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */ 1309 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */ 1310 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */ 1311 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */ 1312 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */ 1313 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */ 1314 }; 1315 1316 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1317 fsl,pins = 1318 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, 1319 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 1320 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 1321 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1322 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1323 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1324 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1325 }; 1326 1327 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1328 fsl,pins = 1329 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, 1330 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, 1331 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, 1332 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, 1333 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, 1334 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, 1335 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; 1336 }; 1337 1338 /* Avoid backfeeding with removed card power */ 1339 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1340 fsl,pins = 1341 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>, 1342 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, 1343 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, 1344 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, 1345 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, 1346 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, 1347 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; 1348 }; 1349 1350 pinctrl_usdhc3: usdhc3grp { 1351 fsl,pins = 1352 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1353 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, 1354 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, 1355 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, 1356 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, 1357 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, 1358 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, 1359 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, 1360 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, 1361 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, 1362 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, 1363 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; 1364 }; 1365 1366 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1367 fsl,pins = 1368 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1369 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, 1370 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 1371 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 1372 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 1373 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 1374 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 1375 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 1376 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 1377 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 1378 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 1379 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; 1380 }; 1381 1382 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1383 fsl,pins = 1384 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1385 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, 1386 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, 1387 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, 1388 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, 1389 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, 1390 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, 1391 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, 1392 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, 1393 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, 1394 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, 1395 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; 1396 }; 1397 1398 pinctrl_wdog: wdoggrp { 1399 fsl,pins = 1400 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */ 1401 }; 1402 1403 pinctrl_bluetooth_ctrl: bluetoothctrlgrp { 1404 fsl,pins = 1405 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */ 1406 }; 1407 1408 pinctrl_wifi_ctrl: wifictrlgrp { 1409 fsl,pins = 1410 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */ 1411 }; 1412 1413 pinctrl_wifi_i2s: wifii2sgrp { 1414 fsl,pins = 1415 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */ 1416 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */ 1417 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */ 1418 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */ 1419 }; 1420 1421 pinctrl_wifi_pwr_en: wifipwrengrp { 1422 fsl,pins = 1423 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */ 1424 }; 1425}; 1426