1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include <dt-bindings/pwm/pwm.h> 8#include "imx8mp.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart3; 13 }; 14 15 aliases { 16 /* Ethernet aliases to ensure correct MAC addresses */ 17 ethernet0 = &eqos; 18 ethernet1 = &fec; 19 rtc0 = &rtc_i2c; 20 rtc1 = &snvs_rtc; 21 }; 22 23 backlight: backlight { 24 compatible = "pwm-backlight"; 25 brightness-levels = <0 45 63 88 119 158 203 255>; 26 default-brightness-level = <4>; 27 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 28 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 31 power-supply = <®_3p3v>; 32 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 33 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; 34 status = "disabled"; 35 }; 36 37 backlight_mezzanine: backlight-mezzanine { 38 compatible = "pwm-backlight"; 39 brightness-levels = <0 45 63 88 119 158 203 255>; 40 default-brightness-level = <4>; 41 /* Verdin GPIO 4 (SODIMM 212) */ 42 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 43 /* Verdin PWM_2 (SODIMM 16) */ 44 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>; 45 status = "disabled"; 46 }; 47 48 gpio-keys { 49 compatible = "gpio-keys"; 50 pinctrl-names = "default"; 51 pinctrl-0 = <&pinctrl_gpio_keys>; 52 53 button-wakeup { 54 debounce-interval = <10>; 55 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 56 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 57 label = "Wake-Up"; 58 linux,code = <KEY_WAKEUP>; 59 wakeup-source; 60 }; 61 }; 62 63 /* Carrier Board Supplies */ 64 reg_1p8v: regulator-1p8v { 65 compatible = "regulator-fixed"; 66 regulator-max-microvolt = <1800000>; 67 regulator-min-microvolt = <1800000>; 68 regulator-name = "+V1.8_SW"; 69 }; 70 71 reg_3p3v: regulator-3p3v { 72 compatible = "regulator-fixed"; 73 regulator-max-microvolt = <3300000>; 74 regulator-min-microvolt = <3300000>; 75 regulator-name = "+V3.3_SW"; 76 }; 77 78 reg_5p0v: regulator-5p0v { 79 compatible = "regulator-fixed"; 80 regulator-max-microvolt = <5000000>; 81 regulator-min-microvolt = <5000000>; 82 regulator-name = "+V5_SW"; 83 }; 84 85 /* Non PMIC On-module Supplies */ 86 reg_module_eth1phy: regulator-module-eth1phy { 87 compatible = "regulator-fixed"; 88 enable-active-high; 89 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 90 off-on-delay = <500000>; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_reg_eth>; 93 regulator-always-on; 94 regulator-boot-on; 95 regulator-max-microvolt = <3300000>; 96 regulator-min-microvolt = <3300000>; 97 regulator-name = "On-module +V3.3_ETH"; 98 startup-delay-us = <200000>; 99 vin-supply = <®_vdd_3v3>; 100 }; 101 102 reg_usb1_vbus: regulator-usb1-vbus { 103 compatible = "regulator-fixed"; 104 enable-active-high; 105 /* Verdin USB_1_EN (SODIMM 155) */ 106 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_usb1_vbus>; 109 regulator-max-microvolt = <5000000>; 110 regulator-min-microvolt = <5000000>; 111 regulator-name = "USB_1_EN"; 112 }; 113 114 reg_usb2_vbus: regulator-usb2-vbus { 115 compatible = "regulator-fixed"; 116 enable-active-high; 117 /* Verdin USB_2_EN (SODIMM 185) */ 118 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_usb2_vbus>; 121 regulator-max-microvolt = <5000000>; 122 regulator-min-microvolt = <5000000>; 123 regulator-name = "USB_2_EN"; 124 }; 125 126 reg_usdhc2_vmmc: regulator-usdhc2 { 127 compatible = "regulator-fixed"; 128 enable-active-high; 129 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 130 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; 131 off-on-delay = <100000>; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 134 regulator-max-microvolt = <3300000>; 135 regulator-min-microvolt = <3300000>; 136 regulator-name = "+V3.3_SD"; 137 startup-delay-us = <2000>; 138 }; 139 140 reserved-memory { 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 145 /* Use the kernel configuration settings instead */ 146 /delete-node/ linux,cma; 147 }; 148}; 149 150&A53_0 { 151 cpu-supply = <®_vdd_arm>; 152}; 153 154&A53_1 { 155 cpu-supply = <®_vdd_arm>; 156}; 157 158&A53_2 { 159 cpu-supply = <®_vdd_arm>; 160}; 161 162&A53_3 { 163 cpu-supply = <®_vdd_arm>; 164}; 165 166&cpu_alert0 { 167 temperature = <95000>; 168}; 169 170&cpu_crit0 { 171 temperature = <105000>; 172}; 173 174/* Verdin SPI_1 */ 175&ecspi1 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_ecspi1>; 181}; 182 183/* Verdin ETH_1 (On-module PHY) */ 184&eqos { 185 phy-handle = <ðphy0>; 186 phy-mode = "rgmii-id"; 187 phy-supply = <®_module_eth1phy>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_eqos>; 190 snps,force_thresh_dma_mode; 191 snps,mtl-rx-config = <&mtl_rx_setup>; 192 snps,mtl-tx-config = <&mtl_tx_setup>; 193 194 mdio { 195 compatible = "snps,dwmac-mdio"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 ethphy0: ethernet-phy@7 { 200 compatible = "ethernet-phy-ieee802.3-c22"; 201 eee-broken-100tx; 202 eee-broken-1000t; 203 interrupt-parent = <&gpio1>; 204 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 205 micrel,led-mode = <0>; 206 reg = <7>; 207 }; 208 }; 209 210 mtl_rx_setup: rx-queues-config { 211 snps,rx-queues-to-use = <5>; 212 snps,rx-sched-sp; 213 214 queue0 { 215 snps,dcb-algorithm; 216 snps,priority = <0x1>; 217 snps,map-to-dma-channel = <0>; 218 }; 219 220 queue1 { 221 snps,dcb-algorithm; 222 snps,priority = <0x2>; 223 snps,map-to-dma-channel = <1>; 224 }; 225 226 queue2 { 227 snps,dcb-algorithm; 228 snps,priority = <0x4>; 229 snps,map-to-dma-channel = <2>; 230 }; 231 232 queue3 { 233 snps,dcb-algorithm; 234 snps,priority = <0x8>; 235 snps,map-to-dma-channel = <3>; 236 }; 237 238 queue4 { 239 snps,dcb-algorithm; 240 snps,priority = <0xf0>; 241 snps,map-to-dma-channel = <4>; 242 }; 243 }; 244 245 mtl_tx_setup: tx-queues-config { 246 snps,tx-queues-to-use = <5>; 247 snps,tx-sched-sp; 248 249 queue0 { 250 snps,dcb-algorithm; 251 snps,priority = <0x1>; 252 }; 253 254 queue1 { 255 snps,dcb-algorithm; 256 snps,priority = <0x2>; 257 }; 258 259 queue2 { 260 snps,dcb-algorithm; 261 snps,priority = <0x4>; 262 }; 263 264 queue3 { 265 snps,dcb-algorithm; 266 snps,priority = <0x8>; 267 }; 268 269 queue4 { 270 snps,dcb-algorithm; 271 snps,priority = <0xf0>; 272 }; 273 }; 274}; 275 276/* Verdin ETH_2_RGMII */ 277&fec { 278 fsl,magic-packet; 279 phy-handle = <ðphy1>; 280 phy-mode = "rgmii-id"; 281 pinctrl-names = "default", "sleep"; 282 pinctrl-0 = <&pinctrl_fec>; 283 pinctrl-1 = <&pinctrl_fec_sleep>; 284 285 mdio { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 289 ethphy1: ethernet-phy@7 { 290 compatible = "ethernet-phy-ieee802.3-c22"; 291 interrupt-parent = <&gpio4>; 292 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 293 micrel,led-mode = <0>; 294 reg = <7>; 295 }; 296 }; 297}; 298 299/* Verdin CAN_1 */ 300&flexcan1 { 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_flexcan1>; 303 status = "disabled"; 304}; 305 306/* Verdin CAN_2 */ 307&flexcan2 { 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pinctrl_flexcan2>; 310 status = "disabled"; 311}; 312 313/* Verdin QSPI_1 */ 314&flexspi { 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_flexspi0>; 317}; 318 319&gpio1 { 320 gpio-line-names = "SODIMM_206", 321 "SODIMM_208", 322 "", 323 "", 324 "", 325 "SODIMM_210", 326 "SODIMM_212", 327 "SODIMM_216", 328 "SODIMM_218", 329 "", 330 "", 331 "SODIMM_16", 332 "SODIMM_155", 333 "SODIMM_157", 334 "SODIMM_185", 335 "SODIMM_91"; 336}; 337 338&gpio2 { 339 gpio-line-names = "", 340 "", 341 "", 342 "", 343 "", 344 "", 345 "SODIMM_143", 346 "SODIMM_141", 347 "", 348 "", 349 "SODIMM_161", 350 "", 351 "SODIMM_84", 352 "SODIMM_78", 353 "SODIMM_74", 354 "SODIMM_80", 355 "SODIMM_82", 356 "SODIMM_70", 357 "SODIMM_72"; 358}; 359 360&gpio3 { 361 gpio-line-names = "SODIMM_52", 362 "SODIMM_54", 363 "", 364 "", 365 "", 366 "", 367 "SODIMM_56", 368 "SODIMM_58", 369 "SODIMM_60", 370 "SODIMM_62", 371 "", 372 "", 373 "", 374 "", 375 "SODIMM_66", 376 "", 377 "SODIMM_64", 378 "", 379 "", 380 "SODIMM_34", 381 "SODIMM_19", 382 "", 383 "SODIMM_32", 384 "", 385 "", 386 "SODIMM_30", 387 "SODIMM_59", 388 "SODIMM_57", 389 "SODIMM_63", 390 "SODIMM_61"; 391}; 392 393&gpio4 { 394 gpio-line-names = "SODIMM_252", 395 "SODIMM_222", 396 "SODIMM_36", 397 "SODIMM_220", 398 "SODIMM_193", 399 "SODIMM_191", 400 "SODIMM_201", 401 "SODIMM_203", 402 "SODIMM_205", 403 "SODIMM_207", 404 "SODIMM_199", 405 "SODIMM_197", 406 "SODIMM_221", 407 "SODIMM_219", 408 "SODIMM_217", 409 "SODIMM_215", 410 "SODIMM_211", 411 "SODIMM_213", 412 "SODIMM_189", 413 "SODIMM_244", 414 "SODIMM_38", 415 "", 416 "SODIMM_76", 417 "SODIMM_135", 418 "SODIMM_133", 419 "SODIMM_17", 420 "SODIMM_24", 421 "SODIMM_26", 422 "SODIMM_21", 423 "SODIMM_256", 424 "SODIMM_48", 425 "SODIMM_44"; 426 427 ctrl-sleep-moci-hog { 428 gpio-hog; 429 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 430 gpios = <29 GPIO_ACTIVE_HIGH>; 431 line-name = "CTRL_SLEEP_MOCI#"; 432 output-high; 433 pinctrl-names = "default"; 434 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 435 }; 436}; 437 438/* On-module I2C */ 439&i2c1 { 440 clock-frequency = <400000>; 441 pinctrl-names = "default", "gpio"; 442 pinctrl-0 = <&pinctrl_i2c1>; 443 pinctrl-1 = <&pinctrl_i2c1_gpio>; 444 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 445 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 446 status = "okay"; 447 448 pca9450: pmic@25 { 449 compatible = "nxp,pca9450c"; 450 interrupt-parent = <&gpio1>; 451 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 452 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_pmic>; 455 reg = <0x25>; 456 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 457 458 /* 459 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the 460 * I2C level shifter for the TLA2024 ADC behind this PMIC. 461 */ 462 463 regulators { 464 BUCK1 { 465 regulator-always-on; 466 regulator-boot-on; 467 regulator-max-microvolt = <1000000>; 468 regulator-min-microvolt = <720000>; 469 regulator-name = "On-module +VDD_SOC (BUCK1)"; 470 regulator-ramp-delay = <3125>; 471 }; 472 473 reg_vdd_arm: BUCK2 { 474 nxp,dvs-run-voltage = <950000>; 475 nxp,dvs-standby-voltage = <850000>; 476 regulator-always-on; 477 regulator-boot-on; 478 regulator-max-microvolt = <1025000>; 479 regulator-min-microvolt = <720000>; 480 regulator-name = "On-module +VDD_ARM (BUCK2)"; 481 regulator-ramp-delay = <3125>; 482 }; 483 484 reg_vdd_3v3: BUCK4 { 485 regulator-always-on; 486 regulator-boot-on; 487 regulator-max-microvolt = <3300000>; 488 regulator-min-microvolt = <3300000>; 489 regulator-name = "On-module +V3.3 (BUCK4)"; 490 }; 491 492 reg_vdd_1v8: BUCK5 { 493 regulator-always-on; 494 regulator-boot-on; 495 regulator-max-microvolt = <1800000>; 496 regulator-min-microvolt = <1800000>; 497 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 498 }; 499 500 BUCK6 { 501 regulator-always-on; 502 regulator-boot-on; 503 regulator-max-microvolt = <1155000>; 504 regulator-min-microvolt = <1045000>; 505 regulator-name = "On-module +VDD_DDR (BUCK6)"; 506 }; 507 508 LDO1 { 509 regulator-always-on; 510 regulator-boot-on; 511 regulator-max-microvolt = <1950000>; 512 regulator-min-microvolt = <1650000>; 513 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 514 }; 515 516 LDO2 { 517 regulator-always-on; 518 regulator-boot-on; 519 regulator-max-microvolt = <1150000>; 520 regulator-min-microvolt = <800000>; 521 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 522 }; 523 524 LDO3 { 525 regulator-always-on; 526 regulator-boot-on; 527 regulator-max-microvolt = <1800000>; 528 regulator-min-microvolt = <1800000>; 529 regulator-name = "On-module +V1.8A (LDO3)"; 530 }; 531 532 LDO4 { 533 regulator-always-on; 534 regulator-boot-on; 535 regulator-max-microvolt = <3300000>; 536 regulator-min-microvolt = <3300000>; 537 regulator-name = "On-module +V3.3_ADC (LDO4)"; 538 }; 539 540 LDO5 { 541 regulator-max-microvolt = <3300000>; 542 regulator-min-microvolt = <1800000>; 543 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 544 }; 545 }; 546 }; 547 548 rtc_i2c: rtc@32 { 549 compatible = "epson,rx8130"; 550 reg = <0x32>; 551 }; 552 553 /* On-module temperature sensor */ 554 hwmon_temp_module: sensor@48 { 555 compatible = "ti,tmp1075"; 556 reg = <0x48>; 557 vs-supply = <®_vdd_1v8>; 558 }; 559 560 adc@49 { 561 compatible = "ti,ads1015"; 562 reg = <0x49>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 566 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 567 channel@0 { 568 reg = <0>; 569 ti,datarate = <4>; 570 ti,gain = <2>; 571 }; 572 573 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 574 channel@1 { 575 reg = <1>; 576 ti,datarate = <4>; 577 ti,gain = <2>; 578 }; 579 580 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 581 channel@2 { 582 reg = <2>; 583 ti,datarate = <4>; 584 ti,gain = <2>; 585 }; 586 587 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 588 channel@3 { 589 reg = <3>; 590 ti,datarate = <4>; 591 ti,gain = <2>; 592 }; 593 594 /* Verdin I2C_1 ADC_4 */ 595 channel@4 { 596 reg = <4>; 597 ti,datarate = <4>; 598 ti,gain = <2>; 599 }; 600 601 /* Verdin I2C_1 ADC_3 */ 602 channel@5 { 603 reg = <5>; 604 ti,datarate = <4>; 605 ti,gain = <2>; 606 }; 607 608 /* Verdin I2C_1 ADC_2 */ 609 channel@6 { 610 reg = <6>; 611 ti,datarate = <4>; 612 ti,gain = <2>; 613 }; 614 615 /* Verdin I2C_1 ADC_1 */ 616 channel@7 { 617 reg = <7>; 618 ti,datarate = <4>; 619 ti,gain = <2>; 620 }; 621 }; 622 623 eeprom@50 { 624 compatible = "st,24c02"; 625 pagesize = <16>; 626 reg = <0x50>; 627 }; 628}; 629 630/* Verdin I2C_2_DSI */ 631&i2c2 { 632 /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ 633 clock-frequency = <10000>; 634 pinctrl-names = "default", "gpio"; 635 pinctrl-0 = <&pinctrl_i2c2>; 636 pinctrl-1 = <&pinctrl_i2c2_gpio>; 637 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 638 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 639 640 atmel_mxt_ts_mezzanine: touch-mezzanine@4a { 641 compatible = "atmel,maxtouch"; 642 /* Verdin GPIO_3 (SODIMM 210) */ 643 interrupt-parent = <&gpio1>; 644 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 645 reg = <0x4a>; 646 /* Verdin GPIO_2 (SODIMM 208) */ 647 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 648 status = "disabled"; 649 }; 650}; 651 652/* TODO: Verdin I2C_3_HDMI */ 653 654/* Verdin I2C_4_CSI */ 655&i2c3 { 656 clock-frequency = <400000>; 657 pinctrl-names = "default", "gpio"; 658 pinctrl-0 = <&pinctrl_i2c3>; 659 pinctrl-1 = <&pinctrl_i2c3_gpio>; 660 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 661 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 662}; 663 664/* Verdin I2C_1 */ 665&i2c4 { 666 clock-frequency = <400000>; 667 pinctrl-names = "default", "gpio"; 668 pinctrl-0 = <&pinctrl_i2c4>; 669 pinctrl-1 = <&pinctrl_i2c4_gpio>; 670 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 671 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 672 673 gpio_expander_21: gpio-expander@21 { 674 compatible = "nxp,pcal6416"; 675 #gpio-cells = <2>; 676 gpio-controller; 677 reg = <0x21>; 678 vcc-supply = <®_3p3v>; 679 status = "disabled"; 680 }; 681 682 lvds_ti_sn65dsi84: bridge@2c { 683 compatible = "ti,sn65dsi84"; 684 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 685 /* Verdin GPIO_10_DSI (SODIMM 21) */ 686 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 689 reg = <0x2c>; 690 status = "disabled"; 691 }; 692 693 /* Current measurement into module VCC */ 694 hwmon: hwmon@40 { 695 compatible = "ti,ina219"; 696 reg = <0x40>; 697 shunt-resistor = <10000>; 698 status = "disabled"; 699 }; 700 701 hdmi_lontium_lt8912: hdmi@48 { 702 compatible = "lontium,lt8912b"; 703 pinctrl-names = "default"; 704 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; 705 reg = <0x48>; 706 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 707 /* Verdin GPIO_10_DSI (SODIMM 21) */ 708 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 709 status = "disabled"; 710 }; 711 712 atmel_mxt_ts: touch@4a { 713 compatible = "atmel,maxtouch"; 714 /* 715 * Verdin GPIO_9_DSI 716 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) 717 */ 718 interrupt-parent = <&gpio4>; 719 interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 720 pinctrl-names = "default"; 721 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 722 reg = <0x4a>; 723 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 724 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 725 status = "disabled"; 726 }; 727 728 /* Temperature sensor on carrier board */ 729 hwmon_temp: sensor@4f { 730 compatible = "ti,tmp75c"; 731 reg = <0x4f>; 732 status = "disabled"; 733 }; 734 735 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 736 eeprom_display_adapter: eeprom@50 { 737 compatible = "st,24c02"; 738 pagesize = <16>; 739 reg = <0x50>; 740 status = "disabled"; 741 }; 742 743 /* EEPROM on carrier board */ 744 eeprom_carrier_board: eeprom@57 { 745 compatible = "st,24c02"; 746 pagesize = <16>; 747 reg = <0x57>; 748 status = "disabled"; 749 }; 750}; 751 752/* TODO: Verdin PCIE_1 */ 753 754/* Verdin PWM_1 */ 755&pwm1 { 756 pinctrl-names = "default"; 757 pinctrl-0 = <&pinctrl_pwm_1>; 758 #pwm-cells = <3>; 759}; 760 761/* Verdin PWM_2 */ 762&pwm2 { 763 pinctrl-names = "default"; 764 pinctrl-0 = <&pinctrl_pwm_2>; 765 #pwm-cells = <3>; 766}; 767 768/* Verdin PWM_3_DSI */ 769&pwm3 { 770 pinctrl-names = "default"; 771 pinctrl-0 = <&pinctrl_pwm_3>; 772 #pwm-cells = <3>; 773}; 774 775/* TODO: Verdin I2S_1 */ 776 777/* TODO: Verdin I2S_2 */ 778 779&snvs_pwrkey { 780 status = "okay"; 781}; 782 783/* Verdin UART_1 */ 784&uart1 { 785 pinctrl-names = "default"; 786 pinctrl-0 = <&pinctrl_uart1>; 787 uart-has-rtscts; 788}; 789 790/* Verdin UART_2 */ 791&uart2 { 792 pinctrl-names = "default"; 793 pinctrl-0 = <&pinctrl_uart2>; 794 uart-has-rtscts; 795}; 796 797/* Verdin UART_3, used as the Linux Console */ 798&uart3 { 799 pinctrl-names = "default"; 800 pinctrl-0 = <&pinctrl_uart3>; 801}; 802 803/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */ 804&uart4 { 805 pinctrl-names = "default"; 806 pinctrl-0 = <&pinctrl_uart4>; 807}; 808 809/* Verdin USB_1 */ 810&usb3_0 { 811 fsl,disable-port-power-control; 812 fsl,over-current-active-low; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&pinctrl_usb_1_oc_n>; 815}; 816 817&usb_dwc3_0 { 818 /* dual role only, not full featured OTG */ 819 adp-disable; 820 dr_mode = "otg"; 821 hnp-disable; 822 maximum-speed = "high-speed"; 823 role-switch-default-mode = "peripheral"; 824 srp-disable; 825 usb-role-switch; 826 827 connector { 828 compatible = "gpio-usb-b-connector", "usb-b-connector"; 829 id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 830 label = "Type-C"; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&pinctrl_usb_1_id>; 833 self-powered; 834 type = "micro"; 835 vbus-supply = <®_usb1_vbus>; 836 }; 837}; 838 839/* Verdin USB_2 */ 840&usb3_1 { 841 fsl,disable-port-power-control; 842}; 843 844&usb3_phy1 { 845 vbus-supply = <®_usb2_vbus>; 846}; 847 848&usb_dwc3_1 { 849 dr_mode = "host"; 850}; 851 852/* Verdin SD_1 */ 853&usdhc2 { 854 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 855 assigned-clock-rates = <400000000>; 856 bus-width = <4>; 857 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 858 disable-wp; 859 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 860 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 861 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 862 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 863 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 864 vmmc-supply = <®_usdhc2_vmmc>; 865}; 866 867/* On-module eMMC */ 868&usdhc3 { 869 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; 870 assigned-clock-rates = <400000000>; 871 bus-width = <8>; 872 non-removable; 873 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 874 pinctrl-0 = <&pinctrl_usdhc3>; 875 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 876 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 877 status = "okay"; 878}; 879 880&wdog1 { 881 fsl,ext-reset-output; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&pinctrl_wdog>; 884 status = "okay"; 885}; 886 887&iomuxc { 888 pinctrl_bt_uart: btuartgrp { 889 fsl,pins = 890 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>, 891 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>, 892 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>, 893 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>; 894 }; 895 896 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 897 fsl,pins = 898 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */ 899 }; 900 901 pinctrl_ecspi1: ecspi1grp { 902 fsl,pins = 903 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */ 904 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */ 905 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */ 906 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */ 907 }; 908 909 /* Connection On Board PHY */ 910 pinctrl_eqos: eqosgrp { 911 fsl,pins = 912 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>, 913 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>, 914 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>, 915 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>, 916 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>, 917 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>, 918 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>, 919 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>, 920 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>, 921 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>, 922 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>, 923 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>, 924 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>, 925 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>; 926 }; 927 928 /* ETH_INT# shared with TPM_INT# (usually N/A) */ 929 pinctrl_eth_tpm_int: ethtpmintgrp { 930 fsl,pins = 931 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>; 932 }; 933 934 /* Connection Carrier Board PHY ETH_2 */ 935 pinctrl_fec: fecgrp { 936 fsl,pins = 937 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ 938 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ 939 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ 940 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ 941 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ 942 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ 943 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ 944 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ 945 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */ 946 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */ 947 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */ 948 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */ 949 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */ 950 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */ 951 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */ 952 }; 953 954 pinctrl_fec_sleep: fecsleepgrp { 955 fsl,pins = 956 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ 957 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ 958 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ 959 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ 960 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ 961 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ 962 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ 963 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ 964 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */ 965 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */ 966 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */ 967 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */ 968 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */ 969 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */ 970 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */ 971 }; 972 973 pinctrl_flexcan1: flexcan1grp { 974 fsl,pins = 975 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */ 976 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */ 977 }; 978 979 pinctrl_flexcan2: flexcan2grp { 980 fsl,pins = 981 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */ 982 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */ 983 }; 984 985 pinctrl_flexspi0: flexspi0grp { 986 fsl,pins = 987 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */ 988 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */ 989 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */ 990 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */ 991 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */ 992 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */ 993 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */ 994 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */ 995 }; 996 997 pinctrl_gpio1: gpio1grp { 998 fsl,pins = 999 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */ 1000 }; 1001 1002 pinctrl_gpio2: gpio2grp { 1003 fsl,pins = 1004 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */ 1005 }; 1006 1007 pinctrl_gpio3: gpio3grp { 1008 fsl,pins = 1009 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */ 1010 }; 1011 1012 pinctrl_gpio4: gpio4grp { 1013 fsl,pins = 1014 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */ 1015 }; 1016 1017 pinctrl_gpio5: gpio5grp { 1018 fsl,pins = 1019 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */ 1020 }; 1021 1022 pinctrl_gpio6: gpio6grp { 1023 fsl,pins = 1024 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */ 1025 }; 1026 1027 pinctrl_gpio7: gpio7grp { 1028 fsl,pins = 1029 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */ 1030 }; 1031 1032 pinctrl_gpio8: gpio8grp { 1033 fsl,pins = 1034 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */ 1035 }; 1036 1037 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 1038 pinctrl_gpio_9_dsi: gpio9dsigrp { 1039 fsl,pins = 1040 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */ 1041 }; 1042 1043 /* Verdin GPIO_10_DSI */ 1044 pinctrl_gpio_10_dsi: gpio10dsigrp { 1045 fsl,pins = 1046 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */ 1047 }; 1048 1049 /* Non-wifi MSP usage only */ 1050 pinctrl_gpio_hog1: gpiohog1grp { 1051 fsl,pins = 1052 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */ 1053 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */ 1054 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */ 1055 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */ 1056 }; 1057 1058 /* USB_2_OC# */ 1059 pinctrl_gpio_hog2: gpiohog2grp { 1060 fsl,pins = 1061 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */ 1062 }; 1063 1064 pinctrl_gpio_hog3: gpiohog3grp { 1065 fsl,pins = 1066 /* CSI_1_MCLK */ 1067 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */ 1068 }; 1069 1070 /* Wifi usage only */ 1071 pinctrl_gpio_hog4: gpiohog4grp { 1072 fsl,pins = 1073 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */ 1074 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */ 1075 }; 1076 1077 pinctrl_gpio_keys: gpiokeysgrp { 1078 fsl,pins = 1079 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */ 1080 }; 1081 1082 pinctrl_hdmi_hog: hdmihoggrp { 1083 fsl,pins = 1084 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */ 1085 <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */ 1086 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */ 1087 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */ 1088 }; 1089 1090 /* On-module I2C */ 1091 pinctrl_i2c1: i2c1grp { 1092 fsl,pins = 1093 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */ 1094 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */ 1095 }; 1096 1097 pinctrl_i2c1_gpio: i2c1gpiogrp { 1098 fsl,pins = 1099 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */ 1100 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */ 1101 }; 1102 1103 /* Verdin I2C_2_DSI */ 1104 pinctrl_i2c2: i2c2grp { 1105 fsl,pins = 1106 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */ 1107 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */ 1108 }; 1109 1110 pinctrl_i2c2_gpio: i2c2gpiogrp { 1111 fsl,pins = 1112 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */ 1113 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */ 1114 }; 1115 1116 /* Verdin I2C_4_CSI */ 1117 pinctrl_i2c3: i2c3grp { 1118 fsl,pins = 1119 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */ 1120 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */ 1121 }; 1122 1123 pinctrl_i2c3_gpio: i2c3gpiogrp { 1124 fsl,pins = 1125 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */ 1126 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */ 1127 }; 1128 1129 /* Verdin I2C_1 */ 1130 pinctrl_i2c4: i2c4grp { 1131 fsl,pins = 1132 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */ 1133 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */ 1134 }; 1135 1136 pinctrl_i2c4_gpio: i2c4gpiogrp { 1137 fsl,pins = 1138 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */ 1139 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */ 1140 }; 1141 1142 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1143 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1144 fsl,pins = 1145 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */ 1146 }; 1147 1148 /* Verdin I2S_2_D_OUT shared with SAI3 */ 1149 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1150 fsl,pins = 1151 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */ 1152 }; 1153 1154 pinctrl_pcie: pciegrp { 1155 fsl,pins = 1156 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */ 1157 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */ 1158 }; 1159 1160 pinctrl_pmic: pmicirqgrp { 1161 fsl,pins = 1162 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */ 1163 }; 1164 1165 pinctrl_pwm_1: pwm1grp { 1166 fsl,pins = 1167 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */ 1168 }; 1169 1170 pinctrl_pwm_2: pwm2grp { 1171 fsl,pins = 1172 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */ 1173 }; 1174 1175 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */ 1176 pinctrl_pwm_3: pwm3grp { 1177 fsl,pins = 1178 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */ 1179 }; 1180 1181 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */ 1182 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp { 1183 fsl,pins = 1184 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */ 1185 }; 1186 1187 pinctrl_reg_eth: regethgrp { 1188 fsl,pins = 1189 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */ 1190 }; 1191 1192 pinctrl_sai1: sai1grp { 1193 fsl,pins = 1194 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */ 1195 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */ 1196 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */ 1197 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */ 1198 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */ 1199 }; 1200 1201 pinctrl_sai3: sai3grp { 1202 fsl,pins = 1203 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */ 1204 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */ 1205 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */ 1206 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */ 1207 }; 1208 1209 pinctrl_uart1: uart1grp { 1210 fsl,pins = 1211 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */ 1212 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */ 1213 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */ 1214 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */ 1215 }; 1216 1217 pinctrl_uart2: uart2grp { 1218 fsl,pins = 1219 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */ 1220 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */ 1221 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */ 1222 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */ 1223 }; 1224 1225 pinctrl_uart3: uart3grp { 1226 fsl,pins = 1227 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */ 1228 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */ 1229 }; 1230 1231 /* Non-wifi usage only */ 1232 pinctrl_uart4: uart4grp { 1233 fsl,pins = 1234 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */ 1235 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */ 1236 }; 1237 1238 pinctrl_usb1_vbus: usb1vbusgrp { 1239 fsl,pins = 1240 <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */ 1241 }; 1242 1243 /* USB_1_ID */ 1244 pinctrl_usb_1_id: usb1idgrp { 1245 fsl,pins = 1246 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */ 1247 }; 1248 1249 /* USB_1_OC# */ 1250 pinctrl_usb_1_oc_n: usb1ocngrp { 1251 fsl,pins = 1252 <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */ 1253 }; 1254 1255 pinctrl_usb2_vbus: usb2vbusgrp { 1256 fsl,pins = 1257 <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */ 1258 }; 1259 1260 /* On-module Wi-Fi */ 1261 pinctrl_usdhc1: usdhc1grp { 1262 fsl,pins = 1263 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, 1264 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, 1265 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, 1266 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, 1267 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, 1268 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; 1269 }; 1270 1271 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1272 fsl,pins = 1273 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, 1274 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, 1275 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, 1276 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, 1277 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, 1278 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; 1279 }; 1280 1281 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1282 fsl,pins = 1283 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, 1284 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, 1285 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, 1286 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, 1287 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, 1288 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; 1289 }; 1290 1291 pinctrl_usdhc2_cd: usdhc2cdgrp { 1292 fsl,pins = 1293 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */ 1294 }; 1295 1296 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1297 fsl,pins = 1298 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */ 1299 }; 1300 1301 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1302 fsl,pins = 1303 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */ 1304 }; 1305 1306 pinctrl_usdhc2: usdhc2grp { 1307 fsl,pins = 1308 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */ 1309 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */ 1310 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */ 1311 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */ 1312 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */ 1313 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */ 1314 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */ 1315 }; 1316 1317 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1318 fsl,pins = 1319 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, 1320 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 1321 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 1322 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1323 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1324 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1325 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1326 }; 1327 1328 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1329 fsl,pins = 1330 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, 1331 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, 1332 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, 1333 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, 1334 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, 1335 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, 1336 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; 1337 }; 1338 1339 /* Avoid backfeeding with removed card power */ 1340 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1341 fsl,pins = 1342 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>, 1343 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, 1344 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, 1345 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, 1346 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, 1347 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, 1348 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; 1349 }; 1350 1351 pinctrl_usdhc3: usdhc3grp { 1352 fsl,pins = 1353 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1354 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, 1355 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, 1356 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, 1357 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, 1358 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, 1359 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, 1360 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, 1361 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, 1362 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, 1363 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, 1364 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; 1365 }; 1366 1367 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1368 fsl,pins = 1369 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1370 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, 1371 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 1372 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 1373 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 1374 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 1375 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 1376 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 1377 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 1378 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 1379 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 1380 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; 1381 }; 1382 1383 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1384 fsl,pins = 1385 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1386 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, 1387 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, 1388 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, 1389 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, 1390 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, 1391 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, 1392 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, 1393 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, 1394 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, 1395 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, 1396 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; 1397 }; 1398 1399 pinctrl_wdog: wdoggrp { 1400 fsl,pins = 1401 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */ 1402 }; 1403 1404 pinctrl_bluetooth_ctrl: bluetoothctrlgrp { 1405 fsl,pins = 1406 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */ 1407 }; 1408 1409 pinctrl_wifi_ctrl: wifictrlgrp { 1410 fsl,pins = 1411 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */ 1412 }; 1413 1414 pinctrl_wifi_i2s: wifii2sgrp { 1415 fsl,pins = 1416 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */ 1417 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */ 1418 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */ 1419 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */ 1420 }; 1421 1422 pinctrl_wifi_pwr_en: wifipwrengrp { 1423 fsl,pins = 1424 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */ 1425 }; 1426}; 1427