1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "dt-bindings/pwm/pwm.h"
7#include "imx8mp.dtsi"
8
9/ {
10	chosen {
11		stdout-path = &uart3;
12	};
13
14	aliases {
15		/* Ethernet aliases to ensure correct MAC addresses */
16		ethernet0 = &eqos;
17		ethernet1 = &fec;
18		rtc0 = &rtc_i2c;
19		rtc1 = &snvs_rtc;
20	};
21
22	backlight: backlight {
23		compatible = "pwm-backlight";
24		brightness-levels = <0 45 63 88 119 158 203 255>;
25		default-brightness-level = <4>;
26		/* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
27		enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
28		pinctrl-names = "default";
29		pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
30		power-supply = <&reg_3p3v>;
31		/* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
32		pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
33		status = "disabled";
34	};
35
36	backlight_mezzanine: backlight-mezzanine {
37		compatible = "pwm-backlight";
38		brightness-levels = <0 45 63 88 119 158 203 255>;
39		default-brightness-level = <4>;
40		/* Verdin GPIO 4 (SODIMM 212) */
41		enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
42		/* Verdin PWM_2 (SODIMM 16) */
43		pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
44		status = "disabled";
45	};
46
47	gpio-keys {
48		compatible = "gpio-keys";
49		pinctrl-names = "default";
50		pinctrl-0 = <&pinctrl_gpio_keys>;
51
52		button-wakeup {
53			debounce-interval = <10>;
54			/* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
55			gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
56			label = "Wake-Up";
57			linux,code = <KEY_WAKEUP>;
58			wakeup-source;
59		};
60	};
61
62	/* Carrier Board Supplies */
63	reg_1p8v: regulator-1p8v {
64		compatible = "regulator-fixed";
65		regulator-max-microvolt = <1800000>;
66		regulator-min-microvolt = <1800000>;
67		regulator-name = "+V1.8_SW";
68	};
69
70	reg_3p3v: regulator-3p3v {
71		compatible = "regulator-fixed";
72		regulator-max-microvolt = <3300000>;
73		regulator-min-microvolt = <3300000>;
74		regulator-name = "+V3.3_SW";
75	};
76
77	reg_5p0v: regulator-5p0v {
78		compatible = "regulator-fixed";
79		regulator-max-microvolt = <5000000>;
80		regulator-min-microvolt = <5000000>;
81		regulator-name = "+V5_SW";
82	};
83
84	/* Non PMIC On-module Supplies */
85	reg_module_eth1phy: regulator-module-eth1phy {
86		compatible = "regulator-fixed";
87		enable-active-high;
88		gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
89		off-on-delay = <500000>;
90		pinctrl-names = "default";
91		pinctrl-0 = <&pinctrl_reg_eth>;
92		regulator-always-on;
93		regulator-boot-on;
94		regulator-max-microvolt = <3300000>;
95		regulator-min-microvolt = <3300000>;
96		regulator-name = "On-module +V3.3_ETH";
97		startup-delay-us = <200000>;
98		vin-supply = <&reg_vdd_3v3>;
99	};
100
101	reg_usb1_vbus: regulator-usb1-vbus {
102		compatible = "regulator-fixed";
103		enable-active-high;
104		/* Verdin USB_1_EN (SODIMM 155) */
105		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
106		pinctrl-names = "default";
107		pinctrl-0 = <&pinctrl_usb1_vbus>;
108		regulator-max-microvolt = <5000000>;
109		regulator-min-microvolt = <5000000>;
110		regulator-name = "USB_1_EN";
111	};
112
113	reg_usb2_vbus: regulator-usb2-vbus {
114		compatible = "regulator-fixed";
115		enable-active-high;
116		/* Verdin USB_2_EN (SODIMM 185) */
117		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
118		pinctrl-names = "default";
119		pinctrl-0 = <&pinctrl_usb2_vbus>;
120		regulator-max-microvolt = <5000000>;
121		regulator-min-microvolt = <5000000>;
122		regulator-name = "USB_2_EN";
123	};
124
125	reg_usdhc2_vmmc: regulator-usdhc2 {
126		compatible = "regulator-fixed";
127		enable-active-high;
128		/* Verdin SD_1_PWR_EN (SODIMM 76) */
129		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
130		off-on-delay = <100000>;
131		pinctrl-names = "default";
132		pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
133		regulator-max-microvolt = <3300000>;
134		regulator-min-microvolt = <3300000>;
135		regulator-name = "+V3.3_SD";
136		startup-delay-us = <2000>;
137	};
138
139	reserved-memory {
140		#address-cells = <2>;
141		#size-cells = <2>;
142		ranges;
143
144		/* Use the kernel configuration settings instead */
145		/delete-node/ linux,cma;
146	};
147};
148
149&cpu_alert0 {
150	temperature = <95000>;
151};
152
153&cpu_crit0 {
154	temperature = <105000>;
155};
156
157/* Verdin SPI_1 */
158&ecspi1 {
159	#address-cells = <1>;
160	#size-cells = <0>;
161	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
162	pinctrl-names = "default";
163	pinctrl-0 = <&pinctrl_ecspi1>;
164};
165
166/* Verdin ETH_1 (On-module PHY) */
167&eqos {
168	phy-handle = <&ethphy0>;
169	phy-mode = "rgmii-id";
170	phy-supply = <&reg_module_eth1phy>;
171	pinctrl-names = "default";
172	pinctrl-0 = <&pinctrl_eqos>;
173	snps,force_thresh_dma_mode;
174	snps,mtl-rx-config = <&mtl_rx_setup>;
175	snps,mtl-tx-config = <&mtl_tx_setup>;
176
177	mdio {
178		compatible = "snps,dwmac-mdio";
179		#address-cells = <1>;
180		#size-cells = <0>;
181
182		ethphy0: ethernet-phy@7 {
183			compatible = "ethernet-phy-ieee802.3-c22";
184			eee-broken-100tx;
185			eee-broken-1000t;
186			interrupt-parent = <&gpio1>;
187			interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
188			micrel,led-mode = <0>;
189			reg = <7>;
190		};
191	};
192
193	mtl_rx_setup: rx-queues-config {
194		snps,rx-queues-to-use = <5>;
195		snps,rx-sched-sp;
196
197		queue0 {
198			snps,dcb-algorithm;
199			snps,priority = <0x1>;
200			snps,map-to-dma-channel = <0>;
201		};
202
203		queue1 {
204			snps,dcb-algorithm;
205			snps,priority = <0x2>;
206			snps,map-to-dma-channel = <1>;
207		};
208
209		queue2 {
210			snps,dcb-algorithm;
211			snps,priority = <0x4>;
212			snps,map-to-dma-channel = <2>;
213		};
214
215		queue3 {
216			snps,dcb-algorithm;
217			snps,priority = <0x8>;
218			snps,map-to-dma-channel = <3>;
219		};
220
221		queue4 {
222			snps,dcb-algorithm;
223			snps,priority = <0xf0>;
224			snps,map-to-dma-channel = <4>;
225		};
226	};
227
228	mtl_tx_setup: tx-queues-config {
229		snps,tx-queues-to-use = <5>;
230		snps,tx-sched-sp;
231
232		queue0 {
233			snps,dcb-algorithm;
234			snps,priority = <0x1>;
235		};
236
237		queue1 {
238			snps,dcb-algorithm;
239			snps,priority = <0x2>;
240		};
241
242		queue2 {
243			snps,dcb-algorithm;
244			snps,priority = <0x4>;
245		};
246
247		queue3 {
248			snps,dcb-algorithm;
249			snps,priority = <0x8>;
250		};
251
252		queue4 {
253			snps,dcb-algorithm;
254			snps,priority = <0xf0>;
255		};
256	};
257};
258
259/* Verdin ETH_2_RGMII */
260&fec {
261	fsl,magic-packet;
262	phy-handle = <&ethphy1>;
263	phy-mode = "rgmii-id";
264	pinctrl-names = "default", "sleep";
265	pinctrl-0 = <&pinctrl_fec>;
266	pinctrl-1 = <&pinctrl_fec_sleep>;
267
268	mdio {
269		#address-cells = <1>;
270		#size-cells = <0>;
271
272		ethphy1: ethernet-phy@7 {
273			compatible = "ethernet-phy-ieee802.3-c22";
274			interrupt-parent = <&gpio4>;
275			interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
276			micrel,led-mode = <0>;
277			reg = <7>;
278		};
279	};
280};
281
282/* Verdin CAN_1 */
283&flexcan1 {
284	pinctrl-names = "default";
285	pinctrl-0 = <&pinctrl_flexcan1>;
286	status = "disabled";
287};
288
289
290/* Verdin CAN_2 */
291&flexcan2 {
292	pinctrl-names = "default";
293	pinctrl-0 = <&pinctrl_flexcan2>;
294	status = "disabled";
295};
296
297/* Verdin QSPI_1 */
298&flexspi {
299	pinctrl-names = "default";
300	pinctrl-0 = <&pinctrl_flexspi0>;
301};
302
303&gpio1 {
304	gpio-line-names = "SODIMM_206",
305			  "SODIMM_208",
306			  "",
307			  "",
308			  "",
309			  "SODIMM_210",
310			  "SODIMM_212",
311			  "SODIMM_216",
312			  "SODIMM_218",
313			  "",
314			  "",
315			  "SODIMM_16",
316			  "SODIMM_155",
317			  "SODIMM_157",
318			  "SODIMM_185",
319			  "SODIMM_91";
320};
321
322&gpio2 {
323	gpio-line-names = "",
324			  "",
325			  "",
326			  "",
327			  "",
328			  "",
329			  "SODIMM_143",
330			  "SODIMM_141",
331			  "",
332			  "",
333			  "SODIMM_161",
334			  "",
335			  "SODIMM_84",
336			  "SODIMM_78",
337			  "SODIMM_74",
338			  "SODIMM_80",
339			  "SODIMM_82",
340			  "SODIMM_70",
341			  "SODIMM_72";
342
343	ctrl-sleep-moci-hog {
344		gpio-hog;
345		/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
346		gpios = <29 GPIO_ACTIVE_HIGH>;
347		line-name = "CTRL_SLEEP_MOCI#";
348		output-high;
349		pinctrl-names = "default";
350		pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
351	};
352};
353
354&gpio3 {
355	gpio-line-names = "SODIMM_52",
356			  "SODIMM_54",
357			  "",
358			  "",
359			  "",
360			  "",
361			  "SODIMM_56",
362			  "SODIMM_58",
363			  "SODIMM_60",
364			  "SODIMM_62",
365			  "",
366			  "",
367			  "",
368			  "",
369			  "SODIMM_66",
370			  "",
371			  "SODIMM_64",
372			  "",
373			  "",
374			  "SODIMM_34",
375			  "SODIMM_19",
376			  "",
377			  "SODIMM_32",
378			  "",
379			  "",
380			  "SODIMM_30",
381			  "SODIMM_59",
382			  "SODIMM_57",
383			  "SODIMM_63",
384			  "SODIMM_61";
385};
386
387&gpio4 {
388	gpio-line-names = "SODIMM_252",
389			  "SODIMM_222",
390			  "SODIMM_36",
391			  "SODIMM_220",
392			  "SODIMM_193",
393			  "SODIMM_191",
394			  "SODIMM_201",
395			  "SODIMM_203",
396			  "SODIMM_205",
397			  "SODIMM_207",
398			  "SODIMM_199",
399			  "SODIMM_197",
400			  "SODIMM_221",
401			  "SODIMM_219",
402			  "SODIMM_217",
403			  "SODIMM_215",
404			  "SODIMM_211",
405			  "SODIMM_213",
406			  "SODIMM_189",
407			  "SODIMM_244",
408			  "SODIMM_38",
409			  "",
410			  "SODIMM_76",
411			  "SODIMM_135",
412			  "SODIMM_133",
413			  "SODIMM_17",
414			  "SODIMM_24",
415			  "SODIMM_26",
416			  "SODIMM_21",
417			  "SODIMM_256",
418			  "SODIMM_48",
419			  "SODIMM_44";
420};
421
422/* On-module I2C */
423&i2c1 {
424	clock-frequency = <400000>;
425	pinctrl-names = "default", "gpio";
426	pinctrl-0 = <&pinctrl_i2c1>;
427	pinctrl-1 = <&pinctrl_i2c1_gpio>;
428	scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
429	sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
430	status = "okay";
431
432	pca9450: pmic@25 {
433		compatible = "nxp,pca9450c";
434		interrupt-parent = <&gpio1>;
435		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
436		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
437		pinctrl-names = "default";
438		pinctrl-0 = <&pinctrl_pmic>;
439		reg = <0x25>;
440		sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
441
442		/*
443		 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
444		 * I2C level shifter for the TLA2024 ADC behind this PMIC.
445		 */
446
447		regulators {
448			BUCK1 {
449				regulator-always-on;
450				regulator-boot-on;
451				regulator-max-microvolt = <1000000>;
452				regulator-min-microvolt = <720000>;
453				regulator-name = "On-module +VDD_SOC (BUCK1)";
454				regulator-ramp-delay = <3125>;
455			};
456
457			BUCK2 {
458				nxp,dvs-run-voltage = <950000>;
459				nxp,dvs-standby-voltage = <850000>;
460				regulator-always-on;
461				regulator-boot-on;
462				regulator-max-microvolt = <1025000>;
463				regulator-min-microvolt = <720000>;
464				regulator-name = "On-module +VDD_ARM (BUCK2)";
465				regulator-ramp-delay = <3125>;
466			};
467
468			reg_vdd_3v3: BUCK4 {
469				regulator-always-on;
470				regulator-boot-on;
471				regulator-max-microvolt = <3300000>;
472				regulator-min-microvolt = <3300000>;
473				regulator-name = "On-module +V3.3 (BUCK4)";
474			};
475
476			reg_vdd_1v8: BUCK5 {
477				regulator-always-on;
478				regulator-boot-on;
479				regulator-max-microvolt = <1800000>;
480				regulator-min-microvolt = <1800000>;
481				regulator-name = "PWR_1V8_MOCI (BUCK5)";
482			};
483
484			BUCK6 {
485				regulator-always-on;
486				regulator-boot-on;
487				regulator-max-microvolt = <1155000>;
488				regulator-min-microvolt = <1045000>;
489				regulator-name = "On-module +VDD_DDR (BUCK6)";
490			};
491
492			LDO1 {
493				regulator-always-on;
494				regulator-boot-on;
495				regulator-max-microvolt = <1950000>;
496				regulator-min-microvolt = <1650000>;
497				regulator-name = "On-module +V1.8_SNVS (LDO1)";
498			};
499
500			LDO2 {
501				regulator-always-on;
502				regulator-boot-on;
503				regulator-max-microvolt = <1150000>;
504				regulator-min-microvolt = <800000>;
505				regulator-name = "On-module +V0.8_SNVS (LDO2)";
506			};
507
508			LDO3 {
509				regulator-always-on;
510				regulator-boot-on;
511				regulator-max-microvolt = <1800000>;
512				regulator-min-microvolt = <1800000>;
513				regulator-name = "On-module +V1.8A (LDO3)";
514			};
515
516			LDO4 {
517				regulator-always-on;
518				regulator-boot-on;
519				regulator-max-microvolt = <3300000>;
520				regulator-min-microvolt = <3300000>;
521				regulator-name = "On-module +V3.3_ADC (LDO4)";
522			};
523
524			LDO5 {
525				regulator-max-microvolt = <3300000>;
526				regulator-min-microvolt = <1800000>;
527				regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
528			};
529		};
530	};
531
532	rtc_i2c: rtc@32 {
533		compatible = "epson,rx8130";
534		reg = <0x32>;
535	};
536
537	/* On-module temperature sensor */
538	hwmon_temp_module: sensor@48 {
539		compatible = "ti,tmp1075";
540		reg = <0x48>;
541		vs-supply = <&reg_vdd_1v8>;
542	};
543
544	adc@49 {
545		compatible = "ti,ads1015";
546		reg = <0x49>;
547		#address-cells = <1>;
548		#size-cells = <0>;
549
550		/* Verdin I2C_1 (ADC_4 - ADC_3) */
551		channel@0 {
552			reg = <0>;
553			ti,datarate = <4>;
554			ti,gain = <2>;
555		};
556
557		/* Verdin I2C_1 (ADC_4 - ADC_1) */
558		channel@1 {
559			reg = <1>;
560			ti,datarate = <4>;
561			ti,gain = <2>;
562		};
563
564		/* Verdin I2C_1 (ADC_3 - ADC_1) */
565		channel@2 {
566			reg = <2>;
567			ti,datarate = <4>;
568			ti,gain = <2>;
569		};
570
571		/* Verdin I2C_1 (ADC_2 - ADC_1) */
572		channel@3 {
573			reg = <3>;
574			ti,datarate = <4>;
575			ti,gain = <2>;
576		};
577
578		/* Verdin I2C_1 ADC_4 */
579		channel@4 {
580			reg = <4>;
581			ti,datarate = <4>;
582			ti,gain = <2>;
583		};
584
585		/* Verdin I2C_1 ADC_3 */
586		channel@5 {
587			reg = <5>;
588			ti,datarate = <4>;
589			ti,gain = <2>;
590		};
591
592		/* Verdin I2C_1 ADC_2 */
593		channel@6 {
594			reg = <6>;
595			ti,datarate = <4>;
596			ti,gain = <2>;
597		};
598
599		/* Verdin I2C_1 ADC_1 */
600		channel@7 {
601			reg = <7>;
602			ti,datarate = <4>;
603			ti,gain = <2>;
604		};
605	};
606
607	eeprom@50 {
608		compatible = "st,24c02";
609		pagesize = <16>;
610		reg = <0x50>;
611	};
612};
613
614/* Verdin I2C_2_DSI */
615&i2c2 {
616	/* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */
617	clock-frequency = <10000>;
618	pinctrl-names = "default", "gpio";
619	pinctrl-0 = <&pinctrl_i2c2>;
620	pinctrl-1 = <&pinctrl_i2c2_gpio>;
621	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
622	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
623
624	atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
625		compatible = "atmel,maxtouch";
626		/* Verdin GPIO_3 (SODIMM 210) */
627		interrupt-parent = <&gpio1>;
628		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
629		reg = <0x4a>;
630		/* Verdin GPIO_2 (SODIMM 208) */
631		reset-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
632		status = "disabled";
633	};
634};
635
636/* TODO: Verdin I2C_3_HDMI */
637
638/* Verdin I2C_4_CSI */
639&i2c3 {
640	clock-frequency = <400000>;
641	pinctrl-names = "default", "gpio";
642	pinctrl-0 = <&pinctrl_i2c3>;
643	pinctrl-1 = <&pinctrl_i2c3_gpio>;
644	scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
645	sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
646};
647
648/* Verdin I2C_1 */
649&i2c4 {
650	clock-frequency = <400000>;
651	pinctrl-names = "default", "gpio";
652	pinctrl-0 = <&pinctrl_i2c4>;
653	pinctrl-1 = <&pinctrl_i2c4_gpio>;
654	scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
655	sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
656
657	gpio_expander_21: gpio-expander@21 {
658		compatible = "nxp,pcal6416";
659		#gpio-cells = <2>;
660		gpio-controller;
661		reg = <0x21>;
662		vcc-supply = <&reg_3p3v>;
663		status = "disabled";
664	};
665
666	lvds_ti_sn65dsi83: bridge@2c {
667		compatible = "ti,sn65dsi83";
668		/* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
669		/* Verdin GPIO_10_DSI (SODIMM 21) */
670		enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
671		pinctrl-names = "default";
672		pinctrl-0 = <&pinctrl_gpio_10_dsi>;
673		reg = <0x2c>;
674		status = "disabled";
675	};
676
677	/* Current measurement into module VCC */
678	hwmon: hwmon@40 {
679		compatible = "ti,ina219";
680		reg = <0x40>;
681		shunt-resistor = <10000>;
682		status = "disabled";
683	};
684
685	hdmi_lontium_lt8912: hdmi@48 {
686		compatible = "lontium,lt8912b";
687		pinctrl-names = "default";
688		pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
689		reg = <0x48>;
690		/* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
691		/* Verdin GPIO_10_DSI (SODIMM 21) */
692		reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
693		status = "disabled";
694	};
695
696	atmel_mxt_ts: touch@4a {
697		compatible = "atmel,maxtouch";
698		/*
699		 * Verdin GPIO_9_DSI
700		 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
701		 */
702		interrupt-parent = <&gpio4>;
703		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
704		pinctrl-names = "default";
705		pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
706		reg = <0x4a>;
707		/* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
708		reset-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
709		status = "disabled";
710	};
711
712	/* Temperature sensor on carrier board */
713	hwmon_temp: sensor@4f {
714		compatible = "ti,tmp75c";
715		reg = <0x4f>;
716		status = "disabled";
717	};
718
719	/* EEPROM on display adapter (MIPI DSI Display Adapter) */
720	eeprom_display_adapter: eeprom@50 {
721		compatible = "st,24c02";
722		pagesize = <16>;
723		reg = <0x50>;
724		status = "disabled";
725	};
726
727	/* EEPROM on carrier board */
728	eeprom_carrier_board: eeprom@57 {
729		compatible = "st,24c02";
730		pagesize = <16>;
731		reg = <0x57>;
732		status = "disabled";
733	};
734};
735
736/* TODO: Verdin PCIE_1 */
737
738/* Verdin PWM_1 */
739&pwm1 {
740	pinctrl-names = "default";
741	pinctrl-0 = <&pinctrl_pwm_1>;
742	#pwm-cells = <3>;
743};
744
745/* Verdin PWM_2 */
746&pwm2 {
747	pinctrl-names = "default";
748	pinctrl-0 = <&pinctrl_pwm_2>;
749	#pwm-cells = <3>;
750};
751
752/* Verdin PWM_3_DSI */
753&pwm3 {
754	pinctrl-names = "default";
755	pinctrl-0 = <&pinctrl_pwm_3>;
756	#pwm-cells = <3>;
757};
758
759/* TODO: Verdin I2S_1 */
760
761/* TODO: Verdin I2S_2 */
762
763&snvs_pwrkey {
764	status = "okay";
765};
766
767/* Verdin UART_1 */
768&uart1 {
769	pinctrl-names = "default";
770	pinctrl-0 = <&pinctrl_uart1>;
771	uart-has-rtscts;
772};
773
774/* Verdin UART_2 */
775&uart2 {
776	pinctrl-names = "default";
777	pinctrl-0 = <&pinctrl_uart2>;
778	uart-has-rtscts;
779};
780
781/* Verdin UART_3, used as the Linux Console */
782&uart3 {
783	pinctrl-names = "default";
784	pinctrl-0 = <&pinctrl_uart3>;
785};
786
787/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
788&uart4 {
789	pinctrl-names = "default";
790	pinctrl-0 = <&pinctrl_uart4>;
791};
792
793/* Verdin USB_1 */
794&usb3_phy0 {
795	vbus-supply = <&reg_usb1_vbus>;
796};
797
798&usb_dwc3_0 {
799	adp-disable;
800	dr_mode = "otg";
801	hnp-disable;
802	maximum-speed = "high-speed";
803	over-current-active-low;
804	pinctrl-names = "default";
805	pinctrl-0 = <&pinctrl_usb_1_id>;
806	srp-disable;
807};
808
809/* Verdin USB_2 */
810&usb3_phy1 {
811	vbus-supply = <&reg_usb2_vbus>;
812};
813
814&usb_dwc3_1 {
815	disable-over-current;
816	dr_mode = "host";
817};
818
819/* Verdin SD_1 */
820&usdhc2 {
821	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
822	assigned-clock-rates = <400000000>;
823	bus-width = <4>;
824	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
825	disable-wp;
826	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
827	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
828	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
829	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
830	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
831	vmmc-supply = <&reg_usdhc2_vmmc>;
832};
833
834/* On-module eMMC */
835&usdhc3 {
836	assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
837	assigned-clock-rates = <400000000>;
838	bus-width = <8>;
839	non-removable;
840	pinctrl-names = "default", "state_100mhz", "state_200mhz";
841	pinctrl-0 = <&pinctrl_usdhc3>;
842	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
843	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
844	status = "okay";
845};
846
847&wdog1 {
848	fsl,ext-reset-output;
849	pinctrl-names = "default";
850	pinctrl-0 = <&pinctrl_wdog>;
851	status = "okay";
852};
853
854&iomuxc {
855	pinctrl_bt_uart: btuartgrp {
856		fsl,pins =
857			<MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS	0x1c4>,
858			<MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX		0x1c4>,
859			<MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX		0x1c4>,
860			<MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS		0x1c4>;
861	};
862
863	pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
864		fsl,pins =
865			<MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29		0x1c4>;	/* SODIMM 256 */
866	};
867
868	pinctrl_ecspi1: ecspi1grp {
869		fsl,pins =
870			<MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO		0x1c4>,	/* SODIMM 198 */
871			<MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI		0x4>,	/* SODIMM 200 */
872			<MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK		0x4>,	/* SODIMM 196 */
873			<MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09		0x1c4>;	/* SODIMM 202 */
874	};
875
876	/* Connection On Board PHY */
877	pinctrl_eqos: eqosgrp {
878		fsl,pins =
879			<MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3>,
880			<MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3>,
881			<MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x91>,
882			<MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x91>,
883			<MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x91>,
884			<MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x91>,
885			<MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91>,
886			<MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x91>,
887			<MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x1f>,
888			<MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x1f>,
889			<MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x1f>,
890			<MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x1f>,
891			<MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x1f>,
892			<MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f>;
893	};
894
895	/* ETH_INT# shared with TPM_INT# (usually N/A) */
896	pinctrl_eth_tpm_int: ethtpmintgrp {
897		fsl,pins =
898			<MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x1c4>;
899	};
900
901	/* Connection Carrier Board PHY ETH_2 */
902	pinctrl_fec: fecgrp {
903		fsl,pins =
904			<MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3>,	/* SODIMM 193 */
905			<MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3>,	/* SODIMM 191 */
906			<MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x91>,	/* SODIMM 201 */
907			<MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x91>,	/* SODIMM 203 */
908			<MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x91>,	/* SODIMM 205 */
909			<MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x91>,	/* SODIMM 207 */
910			<MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91>,	/* SODIMM 197 */
911			<MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91>,	/* SODIMM 199 */
912			<MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0	0x1f>,	/* SODIMM 221 */
913			<MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1	0x1f>,	/* SODIMM 219 */
914			<MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2	0x1f>,	/* SODIMM 217 */
915			<MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3	0x1f>,	/* SODIMM 215 */
916			<MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f>,	/* SODIMM 211 */
917			<MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC	0x1f>,	/* SODIMM 213 */
918			<MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x1c4>;	/* SODIMM 189 */
919	};
920
921	pinctrl_fec_sleep: fecsleepgrp {
922		fsl,pins =
923			<MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC		0x3>,	/* SODIMM 193 */
924			<MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO		0x3>,	/* SODIMM 191 */
925			<MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0	0x91>,	/* SODIMM 201 */
926			<MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1	0x91>,	/* SODIMM 203 */
927			<MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2	0x91>,	/* SODIMM 205 */
928			<MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3	0x91>,	/* SODIMM 207 */
929			<MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91>,	/* SODIMM 197 */
930			<MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91>,	/* SODIMM 199 */
931			<MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12		0x1f>,	/* SODIMM 221 */
932			<MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13		0x1f>,	/* SODIMM 219 */
933			<MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14		0x1f>,	/* SODIMM 217 */
934			<MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15		0x1f>,	/* SODIMM 215 */
935			<MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16		0x1f>,	/* SODIMM 211 */
936			<MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17		0x1f>,	/* SODIMM 213 */
937			<MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18		0x184>;	/* SODIMM 189 */
938	};
939
940	pinctrl_flexcan1: flexcan1grp {
941		fsl,pins =
942			<MX8MP_IOMUXC_SPDIF_RX__CAN1_RX			0x154>,	/* SODIMM 22 */
943			<MX8MP_IOMUXC_SPDIF_TX__CAN1_TX			0x154>;	/* SODIMM 20 */
944	};
945
946	pinctrl_flexcan2: flexcan2grp {
947		fsl,pins =
948			<MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX		0x154>,	/* SODIMM 26 */
949			<MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX		0x154>;	/* SODIMM 24 */
950	};
951
952	pinctrl_flexspi0: flexspi0grp {
953		fsl,pins =
954			<MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2>,	/* SODIMM 52 */
955			<MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82>,	/* SODIMM 54 */
956			<MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS		0x82>,	/* SODIMM 66 */
957			<MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82>,	/* SODIMM 56 */
958			<MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82>,	/* SODIMM 58 */
959			<MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82>,	/* SODIMM 60 */
960			<MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82>,	/* SODIMM 62 */
961			<MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16		0x82>;	/* SODIMM 64 */
962	};
963
964	pinctrl_gpio1: gpio1grp {
965		fsl,pins =
966			<MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00		0x184>;	/* SODIMM 206 */
967	};
968
969	pinctrl_gpio2: gpio2grp {
970		fsl,pins =
971			<MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x1c4>;	/* SODIMM 208 */
972	};
973
974	pinctrl_gpio3: gpio3grp {
975		fsl,pins =
976			<MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x184>;	/* SODIMM 210 */
977	};
978
979	pinctrl_gpio4: gpio4grp {
980		fsl,pins =
981			<MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x184>;	/* SODIMM 212 */
982	};
983
984	pinctrl_gpio5: gpio5grp {
985		fsl,pins =
986			<MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x184>;	/* SODIMM 216 */
987	};
988
989	pinctrl_gpio6: gpio6grp {
990		fsl,pins =
991			<MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x184>;	/* SODIMM 218 */
992	};
993
994	pinctrl_gpio7: gpio7grp {
995		fsl,pins =
996			<MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03		0x184>;	/* SODIMM 220 */
997	};
998
999	pinctrl_gpio8: gpio8grp {
1000		fsl,pins =
1001			<MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01		0x184>;	/* SODIMM 222 */
1002	};
1003
1004	/* Verdin GPIO_9_DSI (pulled-up as active-low) */
1005	pinctrl_gpio_9_dsi: gpio9dsigrp {
1006		fsl,pins =
1007			<MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25		0x1c4>;	/* SODIMM 17 */
1008	};
1009
1010	/* Verdin GPIO_10_DSI */
1011	pinctrl_gpio_10_dsi: gpio10dsigrp {
1012		fsl,pins =
1013			<MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x1c4>;	/* SODIMM 21 */
1014	};
1015
1016	/* Non-wifi MSP usage only */
1017	pinctrl_gpio_hog1: gpiohog1grp {
1018		fsl,pins =
1019			<MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12		0x1c4>,	/* SODIMM 116 */
1020			<MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11		0x1c4>,	/* SODIMM 152 */
1021			<MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10		0x1c4>,	/* SODIMM 164 */
1022			<MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x1c4>;	/* SODIMM 128 */
1023	};
1024
1025	/* USB_2_OC# */
1026	pinctrl_gpio_hog2: gpiohog2grp {
1027		fsl,pins =
1028			<MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02		0x1c4>;	/* SODIMM 187 */
1029	};
1030
1031	pinctrl_gpio_hog3: gpiohog3grp {
1032		fsl,pins =
1033			<MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x1c4>,	/* SODIMM 157 */
1034			/* CSI_1_MCLK */
1035			<MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x1c4>;	/* SODIMM 91 */
1036	};
1037
1038	/* Wifi usage only */
1039	pinctrl_gpio_hog4: gpiohog4grp {
1040		fsl,pins =
1041			<MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28		0x1c4>,	/* SODIMM 151 */
1042			<MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29		0x1c4>;	/* SODIMM 153 */
1043	};
1044
1045	pinctrl_gpio_keys: gpiokeysgrp {
1046		fsl,pins =
1047			<MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00		0x1c4>;	/* SODIMM 252 */
1048	};
1049
1050	pinctrl_hdmi_hog: hdmihoggrp {
1051		fsl,pins =
1052			<MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC	0x40000019>,	/* SODIMM 63 */
1053			<MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3>,	/* SODIMM 59 */
1054			<MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3>,	/* SODIMM 57 */
1055			<MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD	0x40000019>;	/* SODIMM 61 */
1056	};
1057
1058	/* On-module I2C */
1059	pinctrl_i2c1: i2c1grp {
1060		fsl,pins =
1061			<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c6>,	/* PMIC_I2C_SCL */
1062			<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c6>;	/* PMIC_I2C_SDA */
1063	};
1064
1065	pinctrl_i2c1_gpio: i2c1gpiogrp {
1066		fsl,pins =
1067			<MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14		0x400001c6>,	/* PMIC_I2C_SCL */
1068			<MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15		0x400001c6>;	/* PMIC_I2C_SDA */
1069	};
1070
1071	/* Verdin I2C_2_DSI */
1072	pinctrl_i2c2: i2c2grp {
1073		fsl,pins =
1074			<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c6>,	/* SODIMM 55 */
1075			<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c6>;	/* SODIMM 53 */
1076	};
1077
1078	pinctrl_i2c2_gpio: i2c2gpiogrp {
1079		fsl,pins =
1080			<MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16		0x400001c6>,	/* SODIMM 55 */
1081			<MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17		0x400001c6>;	/* SODIMM 53 */
1082	};
1083
1084	/* Verdin I2C_4_CSI */
1085	pinctrl_i2c3: i2c3grp {
1086		fsl,pins =
1087			<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c6>,	/* SODIMM 95 */
1088			<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c6>;	/* SODIMM 93 */
1089	};
1090
1091	pinctrl_i2c3_gpio: i2c3gpiogrp {
1092		fsl,pins =
1093			<MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18		0x400001c6>,	/* SODIMM 95 */
1094			<MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19		0x400001c6>;	/* SODIMM 93 */
1095	};
1096
1097	/* Verdin I2C_1 */
1098	pinctrl_i2c4: i2c4grp {
1099		fsl,pins =
1100			<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c6>,	/* SODIMM 14 */
1101			<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c6>;	/* SODIMM 12 */
1102	};
1103
1104	pinctrl_i2c4_gpio: i2c4gpiogrp {
1105		fsl,pins =
1106			<MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20		0x400001c6>,	/* SODIMM 14 */
1107			<MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21		0x400001c6>;	/* SODIMM 12 */
1108	};
1109
1110	/* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1111	pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1112		fsl,pins =
1113			<MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00		0x184>;	/* SODIMM 42 */
1114	};
1115
1116	/* Verdin I2S_2_D_OUT shared with SAI3 */
1117	pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1118		fsl,pins =
1119			<MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01		0x184>;	/* SODIMM 46 */
1120	};
1121
1122	pinctrl_pcie: pciegrp {
1123		fsl,pins =
1124			<MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19		0x4>,	/* SODIMM 244 */
1125			<MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x1c4>;	/* PMIC_EN_PCIe_CLK, unused */
1126	};
1127
1128	pinctrl_pmic: pmicirqgrp {
1129		fsl,pins =
1130			<MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03		0x1c4>;	/* PMIC_INT# */
1131	};
1132
1133	pinctrl_pwm_1: pwm1grp {
1134		fsl,pins =
1135			<MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT		0x6>;	/* SODIMM 15 */
1136	};
1137
1138	pinctrl_pwm_2: pwm2grp {
1139		fsl,pins =
1140			<MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT		0x6>;	/* SODIMM 16 */
1141	};
1142
1143	/* Verdin PWM_3_DSI shared with GPIO3_IO20 */
1144	pinctrl_pwm_3: pwm3grp {
1145		fsl,pins =
1146			<MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT		0x6>;	/* SODIMM 19 */
1147	};
1148
1149	/* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
1150	pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
1151		fsl,pins =
1152			<MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20		0x184>;	/* SODIMM 19 */
1153	};
1154
1155	pinctrl_reg_eth: regethgrp {
1156		fsl,pins =
1157			<MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x184>;	/* PMIC_EN_ETH */
1158	};
1159
1160	pinctrl_sai1: sai1grp {
1161		fsl,pins =
1162			<MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK		0x96>,	/* SODIMM 38 */
1163			<MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00	0x1d6>,	/* SODIMM 36 */
1164			<MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK		0x1d6>,	/* SODIMM 30 */
1165			<MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC		0x1d6>,	/* SODIMM 32 */
1166			<MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00	0x96>;	/* SODIMM 34 */
1167	};
1168
1169	pinctrl_sai3: sai3grp {
1170		fsl,pins =
1171			<MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0x1d6>,	/* SODIMM 48 */
1172			<MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0x1d6>,	/* SODIMM 42 */
1173			<MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0x96>,	/* SODIMM 46 */
1174			<MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0x1d6>;	/* SODIMM 44 */
1175	};
1176
1177	pinctrl_uart1: uart1grp {
1178		fsl,pins =
1179			<MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS		0x1c4>,	/* SODIMM 135 */
1180			<MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS		0x1c4>,	/* SODIMM 133 */
1181			<MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX		0x1c4>,	/* SODIMM 129 */
1182			<MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX		0x1c4>;	/* SODIMM 131 */
1183	};
1184
1185	pinctrl_uart2: uart2grp {
1186		fsl,pins =
1187			<MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS		0x1c4>,	/* SODIMM 143 */
1188			<MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS		0x1c4>,	/* SODIMM 141 */
1189			<MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX		0x1c4>,	/* SODIMM 137 */
1190			<MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX		0x1c4>; /* SODIMM 139 */
1191	};
1192
1193	pinctrl_uart3: uart3grp {
1194		fsl,pins =
1195			<MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX		0x1c4>,	/* SODIMM 147 */
1196			<MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX		0x1c4>;	/* SODIMM 149 */
1197	};
1198
1199	/* Non-wifi usage only */
1200	pinctrl_uart4: uart4grp {
1201		fsl,pins =
1202			<MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX		0x1c4>,	/* SODIMM 151 */
1203			<MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX		0x1c4>;	/* SODIMM 153 */
1204	};
1205
1206	pinctrl_usb1_vbus: usb1vbusgrp {
1207		fsl,pins =
1208			<MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR		0x19>;	/* SODIMM 155 */
1209	};
1210
1211	/* USB_1_ID */
1212	pinctrl_usb_1_id: usb1idgrp {
1213		fsl,pins =
1214			<MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10		0x1c4>;	/* SODIMM 161 */
1215	};
1216
1217	pinctrl_usb2_vbus: usb2vbusgrp {
1218		fsl,pins =
1219			<MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR		0x19>;	/* SODIMM 185 */
1220	};
1221
1222	/* On-module Wi-Fi */
1223	pinctrl_usdhc1: usdhc1grp {
1224		fsl,pins =
1225			<MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x190>,
1226			<MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d0>,
1227			<MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d0>,
1228			<MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d0>,
1229			<MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d0>,
1230			<MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d0>;
1231	};
1232
1233	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1234		fsl,pins =
1235			<MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x194>,
1236			<MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d4>,
1237			<MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d4>,
1238			<MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d4>,
1239			<MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d4>,
1240			<MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d4>;
1241	};
1242
1243	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1244		fsl,pins =
1245			<MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK		0x196>,
1246			<MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD		0x1d6>,
1247			<MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0		0x1d6>,
1248			<MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1		0x1d6>,
1249			<MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2		0x1d6>,
1250			<MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3		0x1d6>;
1251	};
1252
1253	pinctrl_usdhc2_cd: usdhc2cdgrp {
1254		fsl,pins =
1255			<MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x1c4>;	/* SODIMM 84 */
1256	};
1257
1258	pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1259		fsl,pins =
1260			<MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12		0x0>;	/* SODIMM 84 */
1261	};
1262
1263	pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1264		fsl,pins =
1265			<MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x4>;	/* SODIMM 76 */
1266	};
1267
1268	pinctrl_usdhc2: usdhc2grp {
1269		fsl,pins =
1270			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x4>,	/* PMIC_USDHC_VSELECT */
1271			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190>,	/* SODIMM 78 */
1272			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0>,	/* SODIMM 74 */
1273			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0>,	/* SODIMM 80 */
1274			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0>,	/* SODIMM 82 */
1275			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0>,	/* SODIMM 70 */
1276			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0>;	/* SODIMM 72 */
1277	};
1278
1279	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1280		fsl,pins =
1281			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x4>,
1282			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194>,
1283			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4>,
1284			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4>,
1285			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4>,
1286			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4>,
1287			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4>;
1288	};
1289
1290	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1291		fsl,pins =
1292			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x4>,
1293			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196>,
1294			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6>,
1295			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6>,
1296			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6>,
1297			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6>,
1298			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6>;
1299	};
1300
1301	/* Avoid backfeeding with removed card power */
1302	pinctrl_usdhc2_sleep: usdhc2slpgrp {
1303		fsl,pins =
1304			<MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0x0>,
1305			<MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x100>,
1306			<MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x100>,
1307			<MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x100>,
1308			<MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x100>,
1309			<MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x100>,
1310			<MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x100>;
1311	};
1312
1313	pinctrl_usdhc3: usdhc3grp {
1314		fsl,pins =
1315			<MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B	0x1d1>,
1316			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x190>,
1317			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d0>,
1318			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d0>,
1319			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d0>,
1320			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d0>,
1321			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d0>,
1322			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d0>,
1323			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d0>,
1324			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d0>,
1325			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x190>,
1326			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d0>;
1327	};
1328
1329	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1330		fsl,pins =
1331			<MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B	0x1d1>,
1332			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x194>,
1333			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d4>,
1334			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d4>,
1335			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d4>,
1336			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d4>,
1337			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d4>,
1338			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d4>,
1339			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d4>,
1340			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d4>,
1341			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x194>,
1342			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d4>;
1343	};
1344
1345	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1346		fsl,pins =
1347			<MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B	0x1d1>,
1348			<MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE		0x196>,
1349			<MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5		0x1d2>,
1350			<MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6		0x1d2>,
1351			<MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7		0x1d2>,
1352			<MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0		0x1d2>,
1353			<MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1		0x1d2>,
1354			<MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2		0x1d2>,
1355			<MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3		0x1d2>,
1356			<MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4		0x1d2>,
1357			<MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK		0x196>,
1358			<MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD		0x1d6>;
1359	};
1360
1361	pinctrl_wdog: wdoggrp {
1362		fsl,pins =
1363			<MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B		0xc6>;	/* PMIC_WDI */
1364	};
1365
1366	pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
1367		fsl,pins =
1368			<MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08		0x1c4>;	/* WIFI_WKUP_BT */
1369	};
1370
1371	pinctrl_wifi_ctrl: wifictrlgrp {
1372		fsl,pins =
1373			<MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09		0x1c4>;	/* WIFI_WKUP_WLAN */
1374	};
1375
1376	pinctrl_wifi_i2s: wifii2sgrp {
1377		fsl,pins =
1378			<MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x1d6>,	/* WIFI_TX_SYNC */
1379			<MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21		0x96>,	/* WIFI_RX_DATA0 */
1380			<MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23		0x1d6>,	/* WIFI_TX_BCLK */
1381			<MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24		0x1d6>;	/* WIFI_TX_DATA0 */
1382	};
1383
1384	pinctrl_wifi_pwr_en: wifipwrengrp {
1385		fsl,pins =
1386			<MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11		0x184>;	/* PMIC_EN_WIFI */
1387	};
1388};
1389