1a39ed23bSMarcel Ziswiler// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2a39ed23bSMarcel Ziswiler/* 3a39ed23bSMarcel Ziswiler * Copyright 2022 Toradex 4a39ed23bSMarcel Ziswiler */ 5a39ed23bSMarcel Ziswiler 6a39ed23bSMarcel Ziswiler#include "dt-bindings/pwm/pwm.h" 7a39ed23bSMarcel Ziswiler#include "imx8mp.dtsi" 8a39ed23bSMarcel Ziswiler 9a39ed23bSMarcel Ziswiler/ { 10a39ed23bSMarcel Ziswiler chosen { 11a39ed23bSMarcel Ziswiler stdout-path = &uart3; 12a39ed23bSMarcel Ziswiler }; 13a39ed23bSMarcel Ziswiler 14a39ed23bSMarcel Ziswiler aliases { 15a39ed23bSMarcel Ziswiler /* Ethernet aliases to ensure correct MAC addresses */ 16a39ed23bSMarcel Ziswiler ethernet0 = &eqos; 17a39ed23bSMarcel Ziswiler ethernet1 = &fec; 18a39ed23bSMarcel Ziswiler rtc0 = &rtc_i2c; 19a39ed23bSMarcel Ziswiler rtc1 = &snvs_rtc; 20a39ed23bSMarcel Ziswiler }; 21a39ed23bSMarcel Ziswiler 22a39ed23bSMarcel Ziswiler backlight: backlight { 23a39ed23bSMarcel Ziswiler compatible = "pwm-backlight"; 24a39ed23bSMarcel Ziswiler brightness-levels = <0 45 63 88 119 158 203 255>; 25a39ed23bSMarcel Ziswiler default-brightness-level = <4>; 26a39ed23bSMarcel Ziswiler /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 27a39ed23bSMarcel Ziswiler enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 28a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 29a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 30a39ed23bSMarcel Ziswiler power-supply = <®_3p3v>; 31a39ed23bSMarcel Ziswiler /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 32a39ed23bSMarcel Ziswiler pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; 33a39ed23bSMarcel Ziswiler status = "disabled"; 34a39ed23bSMarcel Ziswiler }; 35a39ed23bSMarcel Ziswiler 36a39ed23bSMarcel Ziswiler backlight_mezzanine: backlight-mezzanine { 37a39ed23bSMarcel Ziswiler compatible = "pwm-backlight"; 38a39ed23bSMarcel Ziswiler brightness-levels = <0 45 63 88 119 158 203 255>; 39a39ed23bSMarcel Ziswiler default-brightness-level = <4>; 40a39ed23bSMarcel Ziswiler /* Verdin GPIO 4 (SODIMM 212) */ 41a39ed23bSMarcel Ziswiler enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 42a39ed23bSMarcel Ziswiler /* Verdin PWM_2 (SODIMM 16) */ 43a39ed23bSMarcel Ziswiler pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>; 44a39ed23bSMarcel Ziswiler status = "disabled"; 45a39ed23bSMarcel Ziswiler }; 46a39ed23bSMarcel Ziswiler 47a39ed23bSMarcel Ziswiler gpio-keys { 48a39ed23bSMarcel Ziswiler compatible = "gpio-keys"; 49a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 50a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_gpio_keys>; 51a39ed23bSMarcel Ziswiler 52b803d15eSKrzysztof Kozlowski button-wakeup { 53a39ed23bSMarcel Ziswiler debounce-interval = <10>; 54a39ed23bSMarcel Ziswiler /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 55a39ed23bSMarcel Ziswiler gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 56a39ed23bSMarcel Ziswiler label = "Wake-Up"; 57a39ed23bSMarcel Ziswiler linux,code = <KEY_WAKEUP>; 58a39ed23bSMarcel Ziswiler wakeup-source; 59a39ed23bSMarcel Ziswiler }; 60a39ed23bSMarcel Ziswiler }; 61a39ed23bSMarcel Ziswiler 62a39ed23bSMarcel Ziswiler /* Carrier Board Supplies */ 63a39ed23bSMarcel Ziswiler reg_1p8v: regulator-1p8v { 64a39ed23bSMarcel Ziswiler compatible = "regulator-fixed"; 65a39ed23bSMarcel Ziswiler regulator-max-microvolt = <1800000>; 66a39ed23bSMarcel Ziswiler regulator-min-microvolt = <1800000>; 67a39ed23bSMarcel Ziswiler regulator-name = "+V1.8_SW"; 68a39ed23bSMarcel Ziswiler }; 69a39ed23bSMarcel Ziswiler 70a39ed23bSMarcel Ziswiler reg_3p3v: regulator-3p3v { 71a39ed23bSMarcel Ziswiler compatible = "regulator-fixed"; 72a39ed23bSMarcel Ziswiler regulator-max-microvolt = <3300000>; 73a39ed23bSMarcel Ziswiler regulator-min-microvolt = <3300000>; 74a39ed23bSMarcel Ziswiler regulator-name = "+V3.3_SW"; 75a39ed23bSMarcel Ziswiler }; 76a39ed23bSMarcel Ziswiler 77a39ed23bSMarcel Ziswiler reg_5p0v: regulator-5p0v { 78a39ed23bSMarcel Ziswiler compatible = "regulator-fixed"; 79a39ed23bSMarcel Ziswiler regulator-max-microvolt = <5000000>; 80a39ed23bSMarcel Ziswiler regulator-min-microvolt = <5000000>; 81a39ed23bSMarcel Ziswiler regulator-name = "+V5_SW"; 82a39ed23bSMarcel Ziswiler }; 83a39ed23bSMarcel Ziswiler 84a39ed23bSMarcel Ziswiler /* Non PMIC On-module Supplies */ 85a39ed23bSMarcel Ziswiler reg_module_eth1phy: regulator-module-eth1phy { 86a39ed23bSMarcel Ziswiler compatible = "regulator-fixed"; 87a39ed23bSMarcel Ziswiler enable-active-high; 88a39ed23bSMarcel Ziswiler gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 89a39ed23bSMarcel Ziswiler off-on-delay = <500000>; 90a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 91a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_reg_eth>; 92a39ed23bSMarcel Ziswiler regulator-always-on; 93a39ed23bSMarcel Ziswiler regulator-boot-on; 94a39ed23bSMarcel Ziswiler regulator-max-microvolt = <3300000>; 95a39ed23bSMarcel Ziswiler regulator-min-microvolt = <3300000>; 96a39ed23bSMarcel Ziswiler regulator-name = "On-module +V3.3_ETH"; 97a39ed23bSMarcel Ziswiler startup-delay-us = <200000>; 98a39ed23bSMarcel Ziswiler vin-supply = <®_vdd_3v3>; 99a39ed23bSMarcel Ziswiler }; 100a39ed23bSMarcel Ziswiler 101a39ed23bSMarcel Ziswiler reg_usb1_vbus: regulator-usb1-vbus { 102a39ed23bSMarcel Ziswiler compatible = "regulator-fixed"; 103a39ed23bSMarcel Ziswiler enable-active-high; 104a39ed23bSMarcel Ziswiler /* Verdin USB_1_EN (SODIMM 155) */ 105a39ed23bSMarcel Ziswiler gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 106a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 107a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_usb1_vbus>; 108a39ed23bSMarcel Ziswiler regulator-max-microvolt = <5000000>; 109a39ed23bSMarcel Ziswiler regulator-min-microvolt = <5000000>; 110a39ed23bSMarcel Ziswiler regulator-name = "USB_1_EN"; 111a39ed23bSMarcel Ziswiler }; 112a39ed23bSMarcel Ziswiler 113a39ed23bSMarcel Ziswiler reg_usb2_vbus: regulator-usb2-vbus { 114a39ed23bSMarcel Ziswiler compatible = "regulator-fixed"; 115a39ed23bSMarcel Ziswiler enable-active-high; 116a39ed23bSMarcel Ziswiler /* Verdin USB_2_EN (SODIMM 185) */ 117a39ed23bSMarcel Ziswiler gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 118a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 119a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_usb2_vbus>; 120a39ed23bSMarcel Ziswiler regulator-max-microvolt = <5000000>; 121a39ed23bSMarcel Ziswiler regulator-min-microvolt = <5000000>; 122a39ed23bSMarcel Ziswiler regulator-name = "USB_2_EN"; 123a39ed23bSMarcel Ziswiler }; 124a39ed23bSMarcel Ziswiler 125a39ed23bSMarcel Ziswiler reg_usdhc2_vmmc: regulator-usdhc2 { 126a39ed23bSMarcel Ziswiler compatible = "regulator-fixed"; 127a39ed23bSMarcel Ziswiler enable-active-high; 128a39ed23bSMarcel Ziswiler /* Verdin SD_1_PWR_EN (SODIMM 76) */ 129a39ed23bSMarcel Ziswiler gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; 130a39ed23bSMarcel Ziswiler off-on-delay = <100000>; 131a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 132a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 133a39ed23bSMarcel Ziswiler regulator-max-microvolt = <3300000>; 134a39ed23bSMarcel Ziswiler regulator-min-microvolt = <3300000>; 135a39ed23bSMarcel Ziswiler regulator-name = "+V3.3_SD"; 136a39ed23bSMarcel Ziswiler startup-delay-us = <2000>; 137a39ed23bSMarcel Ziswiler }; 138a39ed23bSMarcel Ziswiler 139a39ed23bSMarcel Ziswiler reserved-memory { 140a39ed23bSMarcel Ziswiler #address-cells = <2>; 141a39ed23bSMarcel Ziswiler #size-cells = <2>; 142a39ed23bSMarcel Ziswiler ranges; 143a39ed23bSMarcel Ziswiler 144a39ed23bSMarcel Ziswiler /* Use the kernel configuration settings instead */ 145a39ed23bSMarcel Ziswiler /delete-node/ linux,cma; 146a39ed23bSMarcel Ziswiler }; 147a39ed23bSMarcel Ziswiler}; 148a39ed23bSMarcel Ziswiler 149310dde60SMax Krummenacher&A53_0 { 150310dde60SMax Krummenacher cpu-supply = <®_vdd_arm>; 151310dde60SMax Krummenacher}; 152310dde60SMax Krummenacher 153310dde60SMax Krummenacher&A53_1 { 154310dde60SMax Krummenacher cpu-supply = <®_vdd_arm>; 155310dde60SMax Krummenacher}; 156310dde60SMax Krummenacher 157310dde60SMax Krummenacher&A53_2 { 158310dde60SMax Krummenacher cpu-supply = <®_vdd_arm>; 159310dde60SMax Krummenacher}; 160310dde60SMax Krummenacher 161310dde60SMax Krummenacher&A53_3 { 162310dde60SMax Krummenacher cpu-supply = <®_vdd_arm>; 163310dde60SMax Krummenacher}; 164310dde60SMax Krummenacher 165a242ef5fSPhilippe Schenker&cpu_alert0 { 166a242ef5fSPhilippe Schenker temperature = <95000>; 167a242ef5fSPhilippe Schenker}; 168a242ef5fSPhilippe Schenker 169a242ef5fSPhilippe Schenker&cpu_crit0 { 170a242ef5fSPhilippe Schenker temperature = <105000>; 171a242ef5fSPhilippe Schenker}; 172a242ef5fSPhilippe Schenker 173a39ed23bSMarcel Ziswiler/* Verdin SPI_1 */ 174a39ed23bSMarcel Ziswiler&ecspi1 { 175a39ed23bSMarcel Ziswiler #address-cells = <1>; 176a39ed23bSMarcel Ziswiler #size-cells = <0>; 177a39ed23bSMarcel Ziswiler cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 178a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 179a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_ecspi1>; 180a39ed23bSMarcel Ziswiler}; 181a39ed23bSMarcel Ziswiler 182a39ed23bSMarcel Ziswiler/* Verdin ETH_1 (On-module PHY) */ 183a39ed23bSMarcel Ziswiler&eqos { 184a39ed23bSMarcel Ziswiler phy-handle = <ðphy0>; 185a39ed23bSMarcel Ziswiler phy-mode = "rgmii-id"; 186a39ed23bSMarcel Ziswiler phy-supply = <®_module_eth1phy>; 187a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 188a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_eqos>; 189a39ed23bSMarcel Ziswiler snps,force_thresh_dma_mode; 190a39ed23bSMarcel Ziswiler snps,mtl-rx-config = <&mtl_rx_setup>; 191a39ed23bSMarcel Ziswiler snps,mtl-tx-config = <&mtl_tx_setup>; 192a39ed23bSMarcel Ziswiler 193a39ed23bSMarcel Ziswiler mdio { 194a39ed23bSMarcel Ziswiler compatible = "snps,dwmac-mdio"; 195a39ed23bSMarcel Ziswiler #address-cells = <1>; 196a39ed23bSMarcel Ziswiler #size-cells = <0>; 197a39ed23bSMarcel Ziswiler 198a39ed23bSMarcel Ziswiler ethphy0: ethernet-phy@7 { 199a39ed23bSMarcel Ziswiler compatible = "ethernet-phy-ieee802.3-c22"; 200a39ed23bSMarcel Ziswiler eee-broken-100tx; 201a39ed23bSMarcel Ziswiler eee-broken-1000t; 202a39ed23bSMarcel Ziswiler interrupt-parent = <&gpio1>; 203a39ed23bSMarcel Ziswiler interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 204a39ed23bSMarcel Ziswiler micrel,led-mode = <0>; 205a39ed23bSMarcel Ziswiler reg = <7>; 206a39ed23bSMarcel Ziswiler }; 207a39ed23bSMarcel Ziswiler }; 208a39ed23bSMarcel Ziswiler 209a39ed23bSMarcel Ziswiler mtl_rx_setup: rx-queues-config { 210a39ed23bSMarcel Ziswiler snps,rx-queues-to-use = <5>; 211a39ed23bSMarcel Ziswiler snps,rx-sched-sp; 212a39ed23bSMarcel Ziswiler 213a39ed23bSMarcel Ziswiler queue0 { 214a39ed23bSMarcel Ziswiler snps,dcb-algorithm; 215a39ed23bSMarcel Ziswiler snps,priority = <0x1>; 216a39ed23bSMarcel Ziswiler snps,map-to-dma-channel = <0>; 217a39ed23bSMarcel Ziswiler }; 218a39ed23bSMarcel Ziswiler 219a39ed23bSMarcel Ziswiler queue1 { 220a39ed23bSMarcel Ziswiler snps,dcb-algorithm; 221a39ed23bSMarcel Ziswiler snps,priority = <0x2>; 222a39ed23bSMarcel Ziswiler snps,map-to-dma-channel = <1>; 223a39ed23bSMarcel Ziswiler }; 224a39ed23bSMarcel Ziswiler 225a39ed23bSMarcel Ziswiler queue2 { 226a39ed23bSMarcel Ziswiler snps,dcb-algorithm; 227a39ed23bSMarcel Ziswiler snps,priority = <0x4>; 228a39ed23bSMarcel Ziswiler snps,map-to-dma-channel = <2>; 229a39ed23bSMarcel Ziswiler }; 230a39ed23bSMarcel Ziswiler 231a39ed23bSMarcel Ziswiler queue3 { 232a39ed23bSMarcel Ziswiler snps,dcb-algorithm; 233a39ed23bSMarcel Ziswiler snps,priority = <0x8>; 234a39ed23bSMarcel Ziswiler snps,map-to-dma-channel = <3>; 235a39ed23bSMarcel Ziswiler }; 236a39ed23bSMarcel Ziswiler 237a39ed23bSMarcel Ziswiler queue4 { 238a39ed23bSMarcel Ziswiler snps,dcb-algorithm; 239a39ed23bSMarcel Ziswiler snps,priority = <0xf0>; 240a39ed23bSMarcel Ziswiler snps,map-to-dma-channel = <4>; 241a39ed23bSMarcel Ziswiler }; 242a39ed23bSMarcel Ziswiler }; 243a39ed23bSMarcel Ziswiler 244a39ed23bSMarcel Ziswiler mtl_tx_setup: tx-queues-config { 245a39ed23bSMarcel Ziswiler snps,tx-queues-to-use = <5>; 246a39ed23bSMarcel Ziswiler snps,tx-sched-sp; 247a39ed23bSMarcel Ziswiler 248a39ed23bSMarcel Ziswiler queue0 { 249a39ed23bSMarcel Ziswiler snps,dcb-algorithm; 250a39ed23bSMarcel Ziswiler snps,priority = <0x1>; 251a39ed23bSMarcel Ziswiler }; 252a39ed23bSMarcel Ziswiler 253a39ed23bSMarcel Ziswiler queue1 { 254a39ed23bSMarcel Ziswiler snps,dcb-algorithm; 255a39ed23bSMarcel Ziswiler snps,priority = <0x2>; 256a39ed23bSMarcel Ziswiler }; 257a39ed23bSMarcel Ziswiler 258a39ed23bSMarcel Ziswiler queue2 { 259a39ed23bSMarcel Ziswiler snps,dcb-algorithm; 260a39ed23bSMarcel Ziswiler snps,priority = <0x4>; 261a39ed23bSMarcel Ziswiler }; 262a39ed23bSMarcel Ziswiler 263a39ed23bSMarcel Ziswiler queue3 { 264a39ed23bSMarcel Ziswiler snps,dcb-algorithm; 265a39ed23bSMarcel Ziswiler snps,priority = <0x8>; 266a39ed23bSMarcel Ziswiler }; 267a39ed23bSMarcel Ziswiler 268a39ed23bSMarcel Ziswiler queue4 { 269a39ed23bSMarcel Ziswiler snps,dcb-algorithm; 270a39ed23bSMarcel Ziswiler snps,priority = <0xf0>; 271a39ed23bSMarcel Ziswiler }; 272a39ed23bSMarcel Ziswiler }; 273a39ed23bSMarcel Ziswiler}; 274a39ed23bSMarcel Ziswiler 275a39ed23bSMarcel Ziswiler/* Verdin ETH_2_RGMII */ 276a39ed23bSMarcel Ziswiler&fec { 277a39ed23bSMarcel Ziswiler fsl,magic-packet; 278a39ed23bSMarcel Ziswiler phy-handle = <ðphy1>; 279a39ed23bSMarcel Ziswiler phy-mode = "rgmii-id"; 280a39ed23bSMarcel Ziswiler pinctrl-names = "default", "sleep"; 281a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_fec>; 282a39ed23bSMarcel Ziswiler pinctrl-1 = <&pinctrl_fec_sleep>; 283a39ed23bSMarcel Ziswiler 284a39ed23bSMarcel Ziswiler mdio { 285a39ed23bSMarcel Ziswiler #address-cells = <1>; 286a39ed23bSMarcel Ziswiler #size-cells = <0>; 287a39ed23bSMarcel Ziswiler 288a39ed23bSMarcel Ziswiler ethphy1: ethernet-phy@7 { 289a39ed23bSMarcel Ziswiler compatible = "ethernet-phy-ieee802.3-c22"; 290a39ed23bSMarcel Ziswiler interrupt-parent = <&gpio4>; 291a39ed23bSMarcel Ziswiler interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 292a39ed23bSMarcel Ziswiler micrel,led-mode = <0>; 293a39ed23bSMarcel Ziswiler reg = <7>; 294a39ed23bSMarcel Ziswiler }; 295a39ed23bSMarcel Ziswiler }; 296a39ed23bSMarcel Ziswiler}; 297a39ed23bSMarcel Ziswiler 298a39ed23bSMarcel Ziswiler/* Verdin CAN_1 */ 299a39ed23bSMarcel Ziswiler&flexcan1 { 300a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 301a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_flexcan1>; 302a39ed23bSMarcel Ziswiler status = "disabled"; 303a39ed23bSMarcel Ziswiler}; 304a39ed23bSMarcel Ziswiler 305a39ed23bSMarcel Ziswiler/* Verdin CAN_2 */ 306a39ed23bSMarcel Ziswiler&flexcan2 { 307a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 308a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_flexcan2>; 309a39ed23bSMarcel Ziswiler status = "disabled"; 310a39ed23bSMarcel Ziswiler}; 311a39ed23bSMarcel Ziswiler 312a39ed23bSMarcel Ziswiler/* Verdin QSPI_1 */ 313a39ed23bSMarcel Ziswiler&flexspi { 314a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 315a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_flexspi0>; 316a39ed23bSMarcel Ziswiler}; 317a39ed23bSMarcel Ziswiler 318a39ed23bSMarcel Ziswiler&gpio1 { 319a39ed23bSMarcel Ziswiler gpio-line-names = "SODIMM_206", 320a39ed23bSMarcel Ziswiler "SODIMM_208", 321a39ed23bSMarcel Ziswiler "", 322a39ed23bSMarcel Ziswiler "", 323a39ed23bSMarcel Ziswiler "", 324a39ed23bSMarcel Ziswiler "SODIMM_210", 325a39ed23bSMarcel Ziswiler "SODIMM_212", 326a39ed23bSMarcel Ziswiler "SODIMM_216", 327a39ed23bSMarcel Ziswiler "SODIMM_218", 328a39ed23bSMarcel Ziswiler "", 329a39ed23bSMarcel Ziswiler "", 330a39ed23bSMarcel Ziswiler "SODIMM_16", 331a39ed23bSMarcel Ziswiler "SODIMM_155", 332a39ed23bSMarcel Ziswiler "SODIMM_157", 333a39ed23bSMarcel Ziswiler "SODIMM_185", 334a39ed23bSMarcel Ziswiler "SODIMM_91"; 335a39ed23bSMarcel Ziswiler}; 336a39ed23bSMarcel Ziswiler 337a39ed23bSMarcel Ziswiler&gpio2 { 338a39ed23bSMarcel Ziswiler gpio-line-names = "", 339a39ed23bSMarcel Ziswiler "", 340a39ed23bSMarcel Ziswiler "", 341a39ed23bSMarcel Ziswiler "", 342a39ed23bSMarcel Ziswiler "", 343a39ed23bSMarcel Ziswiler "", 344a39ed23bSMarcel Ziswiler "SODIMM_143", 345a39ed23bSMarcel Ziswiler "SODIMM_141", 346a39ed23bSMarcel Ziswiler "", 347a39ed23bSMarcel Ziswiler "", 348a39ed23bSMarcel Ziswiler "SODIMM_161", 349a39ed23bSMarcel Ziswiler "", 350a39ed23bSMarcel Ziswiler "SODIMM_84", 351a39ed23bSMarcel Ziswiler "SODIMM_78", 352a39ed23bSMarcel Ziswiler "SODIMM_74", 353a39ed23bSMarcel Ziswiler "SODIMM_80", 354a39ed23bSMarcel Ziswiler "SODIMM_82", 355a39ed23bSMarcel Ziswiler "SODIMM_70", 356a39ed23bSMarcel Ziswiler "SODIMM_72"; 357a39ed23bSMarcel Ziswiler}; 358a39ed23bSMarcel Ziswiler 359a39ed23bSMarcel Ziswiler&gpio3 { 360a39ed23bSMarcel Ziswiler gpio-line-names = "SODIMM_52", 361a39ed23bSMarcel Ziswiler "SODIMM_54", 362a39ed23bSMarcel Ziswiler "", 363a39ed23bSMarcel Ziswiler "", 364a39ed23bSMarcel Ziswiler "", 365a39ed23bSMarcel Ziswiler "", 366a39ed23bSMarcel Ziswiler "SODIMM_56", 367a39ed23bSMarcel Ziswiler "SODIMM_58", 368a39ed23bSMarcel Ziswiler "SODIMM_60", 369a39ed23bSMarcel Ziswiler "SODIMM_62", 370a39ed23bSMarcel Ziswiler "", 371a39ed23bSMarcel Ziswiler "", 372a39ed23bSMarcel Ziswiler "", 373a39ed23bSMarcel Ziswiler "", 374a39ed23bSMarcel Ziswiler "SODIMM_66", 375a39ed23bSMarcel Ziswiler "", 376a39ed23bSMarcel Ziswiler "SODIMM_64", 377a39ed23bSMarcel Ziswiler "", 378a39ed23bSMarcel Ziswiler "", 379a39ed23bSMarcel Ziswiler "SODIMM_34", 380a39ed23bSMarcel Ziswiler "SODIMM_19", 381a39ed23bSMarcel Ziswiler "", 382a39ed23bSMarcel Ziswiler "SODIMM_32", 383a39ed23bSMarcel Ziswiler "", 384a39ed23bSMarcel Ziswiler "", 385a39ed23bSMarcel Ziswiler "SODIMM_30", 386a39ed23bSMarcel Ziswiler "SODIMM_59", 387a39ed23bSMarcel Ziswiler "SODIMM_57", 388a39ed23bSMarcel Ziswiler "SODIMM_63", 389a39ed23bSMarcel Ziswiler "SODIMM_61"; 390a39ed23bSMarcel Ziswiler}; 391a39ed23bSMarcel Ziswiler 392a39ed23bSMarcel Ziswiler&gpio4 { 393a39ed23bSMarcel Ziswiler gpio-line-names = "SODIMM_252", 394a39ed23bSMarcel Ziswiler "SODIMM_222", 395a39ed23bSMarcel Ziswiler "SODIMM_36", 396a39ed23bSMarcel Ziswiler "SODIMM_220", 397a39ed23bSMarcel Ziswiler "SODIMM_193", 398a39ed23bSMarcel Ziswiler "SODIMM_191", 399a39ed23bSMarcel Ziswiler "SODIMM_201", 400a39ed23bSMarcel Ziswiler "SODIMM_203", 401a39ed23bSMarcel Ziswiler "SODIMM_205", 402a39ed23bSMarcel Ziswiler "SODIMM_207", 403a39ed23bSMarcel Ziswiler "SODIMM_199", 404a39ed23bSMarcel Ziswiler "SODIMM_197", 405a39ed23bSMarcel Ziswiler "SODIMM_221", 406a39ed23bSMarcel Ziswiler "SODIMM_219", 407a39ed23bSMarcel Ziswiler "SODIMM_217", 408a39ed23bSMarcel Ziswiler "SODIMM_215", 409a39ed23bSMarcel Ziswiler "SODIMM_211", 410a39ed23bSMarcel Ziswiler "SODIMM_213", 411a39ed23bSMarcel Ziswiler "SODIMM_189", 412a39ed23bSMarcel Ziswiler "SODIMM_244", 413a39ed23bSMarcel Ziswiler "SODIMM_38", 414a39ed23bSMarcel Ziswiler "", 415a39ed23bSMarcel Ziswiler "SODIMM_76", 416a39ed23bSMarcel Ziswiler "SODIMM_135", 417a39ed23bSMarcel Ziswiler "SODIMM_133", 418a39ed23bSMarcel Ziswiler "SODIMM_17", 419a39ed23bSMarcel Ziswiler "SODIMM_24", 420a39ed23bSMarcel Ziswiler "SODIMM_26", 421a39ed23bSMarcel Ziswiler "SODIMM_21", 422a39ed23bSMarcel Ziswiler "SODIMM_256", 423a39ed23bSMarcel Ziswiler "SODIMM_48", 424a39ed23bSMarcel Ziswiler "SODIMM_44"; 425*2f321fd6SMax Krummenacher 426*2f321fd6SMax Krummenacher ctrl-sleep-moci-hog { 427*2f321fd6SMax Krummenacher gpio-hog; 428*2f321fd6SMax Krummenacher /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 429*2f321fd6SMax Krummenacher gpios = <29 GPIO_ACTIVE_HIGH>; 430*2f321fd6SMax Krummenacher line-name = "CTRL_SLEEP_MOCI#"; 431*2f321fd6SMax Krummenacher output-high; 432*2f321fd6SMax Krummenacher pinctrl-names = "default"; 433*2f321fd6SMax Krummenacher pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 434*2f321fd6SMax Krummenacher }; 435a39ed23bSMarcel Ziswiler}; 436a39ed23bSMarcel Ziswiler 437a39ed23bSMarcel Ziswiler/* On-module I2C */ 438a39ed23bSMarcel Ziswiler&i2c1 { 439a39ed23bSMarcel Ziswiler clock-frequency = <400000>; 440a39ed23bSMarcel Ziswiler pinctrl-names = "default", "gpio"; 441a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_i2c1>; 442a39ed23bSMarcel Ziswiler pinctrl-1 = <&pinctrl_i2c1_gpio>; 443a39ed23bSMarcel Ziswiler scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 444a39ed23bSMarcel Ziswiler sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 445a39ed23bSMarcel Ziswiler status = "okay"; 446a39ed23bSMarcel Ziswiler 447a39ed23bSMarcel Ziswiler pca9450: pmic@25 { 448a39ed23bSMarcel Ziswiler compatible = "nxp,pca9450c"; 449a39ed23bSMarcel Ziswiler interrupt-parent = <&gpio1>; 450a39ed23bSMarcel Ziswiler /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 451a39ed23bSMarcel Ziswiler interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 452a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 453a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_pmic>; 454a39ed23bSMarcel Ziswiler reg = <0x25>; 455a39ed23bSMarcel Ziswiler sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 456a39ed23bSMarcel Ziswiler 457a39ed23bSMarcel Ziswiler /* 458a39ed23bSMarcel Ziswiler * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the 459a39ed23bSMarcel Ziswiler * I2C level shifter for the TLA2024 ADC behind this PMIC. 460a39ed23bSMarcel Ziswiler */ 461a39ed23bSMarcel Ziswiler 462a39ed23bSMarcel Ziswiler regulators { 463a39ed23bSMarcel Ziswiler BUCK1 { 464a39ed23bSMarcel Ziswiler regulator-always-on; 465a39ed23bSMarcel Ziswiler regulator-boot-on; 466a39ed23bSMarcel Ziswiler regulator-max-microvolt = <1000000>; 467a39ed23bSMarcel Ziswiler regulator-min-microvolt = <720000>; 468a39ed23bSMarcel Ziswiler regulator-name = "On-module +VDD_SOC (BUCK1)"; 469a39ed23bSMarcel Ziswiler regulator-ramp-delay = <3125>; 470a39ed23bSMarcel Ziswiler }; 471a39ed23bSMarcel Ziswiler 472310dde60SMax Krummenacher reg_vdd_arm: BUCK2 { 473a39ed23bSMarcel Ziswiler nxp,dvs-run-voltage = <950000>; 474a39ed23bSMarcel Ziswiler nxp,dvs-standby-voltage = <850000>; 475a39ed23bSMarcel Ziswiler regulator-always-on; 476a39ed23bSMarcel Ziswiler regulator-boot-on; 477a39ed23bSMarcel Ziswiler regulator-max-microvolt = <1025000>; 478a39ed23bSMarcel Ziswiler regulator-min-microvolt = <720000>; 479a39ed23bSMarcel Ziswiler regulator-name = "On-module +VDD_ARM (BUCK2)"; 480a39ed23bSMarcel Ziswiler regulator-ramp-delay = <3125>; 481a39ed23bSMarcel Ziswiler }; 482a39ed23bSMarcel Ziswiler 483a39ed23bSMarcel Ziswiler reg_vdd_3v3: BUCK4 { 484a39ed23bSMarcel Ziswiler regulator-always-on; 485a39ed23bSMarcel Ziswiler regulator-boot-on; 486a39ed23bSMarcel Ziswiler regulator-max-microvolt = <3300000>; 487a39ed23bSMarcel Ziswiler regulator-min-microvolt = <3300000>; 488a39ed23bSMarcel Ziswiler regulator-name = "On-module +V3.3 (BUCK4)"; 489a39ed23bSMarcel Ziswiler }; 490a39ed23bSMarcel Ziswiler 491a39ed23bSMarcel Ziswiler reg_vdd_1v8: BUCK5 { 492a39ed23bSMarcel Ziswiler regulator-always-on; 493a39ed23bSMarcel Ziswiler regulator-boot-on; 494a39ed23bSMarcel Ziswiler regulator-max-microvolt = <1800000>; 495a39ed23bSMarcel Ziswiler regulator-min-microvolt = <1800000>; 496a39ed23bSMarcel Ziswiler regulator-name = "PWR_1V8_MOCI (BUCK5)"; 497a39ed23bSMarcel Ziswiler }; 498a39ed23bSMarcel Ziswiler 499a39ed23bSMarcel Ziswiler BUCK6 { 500a39ed23bSMarcel Ziswiler regulator-always-on; 501a39ed23bSMarcel Ziswiler regulator-boot-on; 502a39ed23bSMarcel Ziswiler regulator-max-microvolt = <1155000>; 503a39ed23bSMarcel Ziswiler regulator-min-microvolt = <1045000>; 504a39ed23bSMarcel Ziswiler regulator-name = "On-module +VDD_DDR (BUCK6)"; 505a39ed23bSMarcel Ziswiler }; 506a39ed23bSMarcel Ziswiler 507a39ed23bSMarcel Ziswiler LDO1 { 508a39ed23bSMarcel Ziswiler regulator-always-on; 509a39ed23bSMarcel Ziswiler regulator-boot-on; 510a39ed23bSMarcel Ziswiler regulator-max-microvolt = <1950000>; 511a39ed23bSMarcel Ziswiler regulator-min-microvolt = <1650000>; 512a39ed23bSMarcel Ziswiler regulator-name = "On-module +V1.8_SNVS (LDO1)"; 513a39ed23bSMarcel Ziswiler }; 514a39ed23bSMarcel Ziswiler 515a39ed23bSMarcel Ziswiler LDO2 { 516a39ed23bSMarcel Ziswiler regulator-always-on; 517a39ed23bSMarcel Ziswiler regulator-boot-on; 518a39ed23bSMarcel Ziswiler regulator-max-microvolt = <1150000>; 519a39ed23bSMarcel Ziswiler regulator-min-microvolt = <800000>; 520a39ed23bSMarcel Ziswiler regulator-name = "On-module +V0.8_SNVS (LDO2)"; 521a39ed23bSMarcel Ziswiler }; 522a39ed23bSMarcel Ziswiler 523a39ed23bSMarcel Ziswiler LDO3 { 524a39ed23bSMarcel Ziswiler regulator-always-on; 525a39ed23bSMarcel Ziswiler regulator-boot-on; 526a39ed23bSMarcel Ziswiler regulator-max-microvolt = <1800000>; 527a39ed23bSMarcel Ziswiler regulator-min-microvolt = <1800000>; 528a39ed23bSMarcel Ziswiler regulator-name = "On-module +V1.8A (LDO3)"; 529a39ed23bSMarcel Ziswiler }; 530a39ed23bSMarcel Ziswiler 531a39ed23bSMarcel Ziswiler LDO4 { 532a39ed23bSMarcel Ziswiler regulator-always-on; 533a39ed23bSMarcel Ziswiler regulator-boot-on; 534a39ed23bSMarcel Ziswiler regulator-max-microvolt = <3300000>; 535a39ed23bSMarcel Ziswiler regulator-min-microvolt = <3300000>; 536a39ed23bSMarcel Ziswiler regulator-name = "On-module +V3.3_ADC (LDO4)"; 537a39ed23bSMarcel Ziswiler }; 538a39ed23bSMarcel Ziswiler 539a39ed23bSMarcel Ziswiler LDO5 { 540a39ed23bSMarcel Ziswiler regulator-max-microvolt = <3300000>; 541a39ed23bSMarcel Ziswiler regulator-min-microvolt = <1800000>; 542a39ed23bSMarcel Ziswiler regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 543a39ed23bSMarcel Ziswiler }; 544a39ed23bSMarcel Ziswiler }; 545a39ed23bSMarcel Ziswiler }; 546a39ed23bSMarcel Ziswiler 547a39ed23bSMarcel Ziswiler rtc_i2c: rtc@32 { 548a39ed23bSMarcel Ziswiler compatible = "epson,rx8130"; 549a39ed23bSMarcel Ziswiler reg = <0x32>; 550a39ed23bSMarcel Ziswiler }; 551a39ed23bSMarcel Ziswiler 552a39ed23bSMarcel Ziswiler /* On-module temperature sensor */ 553a39ed23bSMarcel Ziswiler hwmon_temp_module: sensor@48 { 554a39ed23bSMarcel Ziswiler compatible = "ti,tmp1075"; 555a39ed23bSMarcel Ziswiler reg = <0x48>; 556a39ed23bSMarcel Ziswiler vs-supply = <®_vdd_1v8>; 557a39ed23bSMarcel Ziswiler }; 558a39ed23bSMarcel Ziswiler 559a39ed23bSMarcel Ziswiler adc@49 { 560a39ed23bSMarcel Ziswiler compatible = "ti,ads1015"; 561a39ed23bSMarcel Ziswiler reg = <0x49>; 562a39ed23bSMarcel Ziswiler #address-cells = <1>; 563a39ed23bSMarcel Ziswiler #size-cells = <0>; 564a39ed23bSMarcel Ziswiler 565a39ed23bSMarcel Ziswiler /* Verdin I2C_1 (ADC_4 - ADC_3) */ 566a39ed23bSMarcel Ziswiler channel@0 { 567a39ed23bSMarcel Ziswiler reg = <0>; 568a39ed23bSMarcel Ziswiler ti,datarate = <4>; 569a39ed23bSMarcel Ziswiler ti,gain = <2>; 570a39ed23bSMarcel Ziswiler }; 571a39ed23bSMarcel Ziswiler 572a39ed23bSMarcel Ziswiler /* Verdin I2C_1 (ADC_4 - ADC_1) */ 573a39ed23bSMarcel Ziswiler channel@1 { 574a39ed23bSMarcel Ziswiler reg = <1>; 575a39ed23bSMarcel Ziswiler ti,datarate = <4>; 576a39ed23bSMarcel Ziswiler ti,gain = <2>; 577a39ed23bSMarcel Ziswiler }; 578a39ed23bSMarcel Ziswiler 579a39ed23bSMarcel Ziswiler /* Verdin I2C_1 (ADC_3 - ADC_1) */ 580a39ed23bSMarcel Ziswiler channel@2 { 581a39ed23bSMarcel Ziswiler reg = <2>; 582a39ed23bSMarcel Ziswiler ti,datarate = <4>; 583a39ed23bSMarcel Ziswiler ti,gain = <2>; 584a39ed23bSMarcel Ziswiler }; 585a39ed23bSMarcel Ziswiler 586a39ed23bSMarcel Ziswiler /* Verdin I2C_1 (ADC_2 - ADC_1) */ 587a39ed23bSMarcel Ziswiler channel@3 { 588a39ed23bSMarcel Ziswiler reg = <3>; 589a39ed23bSMarcel Ziswiler ti,datarate = <4>; 590a39ed23bSMarcel Ziswiler ti,gain = <2>; 591a39ed23bSMarcel Ziswiler }; 592a39ed23bSMarcel Ziswiler 593a39ed23bSMarcel Ziswiler /* Verdin I2C_1 ADC_4 */ 594a39ed23bSMarcel Ziswiler channel@4 { 595a39ed23bSMarcel Ziswiler reg = <4>; 596a39ed23bSMarcel Ziswiler ti,datarate = <4>; 597a39ed23bSMarcel Ziswiler ti,gain = <2>; 598a39ed23bSMarcel Ziswiler }; 599a39ed23bSMarcel Ziswiler 600a39ed23bSMarcel Ziswiler /* Verdin I2C_1 ADC_3 */ 601a39ed23bSMarcel Ziswiler channel@5 { 602a39ed23bSMarcel Ziswiler reg = <5>; 603a39ed23bSMarcel Ziswiler ti,datarate = <4>; 604a39ed23bSMarcel Ziswiler ti,gain = <2>; 605a39ed23bSMarcel Ziswiler }; 606a39ed23bSMarcel Ziswiler 607a39ed23bSMarcel Ziswiler /* Verdin I2C_1 ADC_2 */ 608a39ed23bSMarcel Ziswiler channel@6 { 609a39ed23bSMarcel Ziswiler reg = <6>; 610a39ed23bSMarcel Ziswiler ti,datarate = <4>; 611a39ed23bSMarcel Ziswiler ti,gain = <2>; 612a39ed23bSMarcel Ziswiler }; 613a39ed23bSMarcel Ziswiler 614a39ed23bSMarcel Ziswiler /* Verdin I2C_1 ADC_1 */ 615a39ed23bSMarcel Ziswiler channel@7 { 616a39ed23bSMarcel Ziswiler reg = <7>; 617a39ed23bSMarcel Ziswiler ti,datarate = <4>; 618a39ed23bSMarcel Ziswiler ti,gain = <2>; 619a39ed23bSMarcel Ziswiler }; 620a39ed23bSMarcel Ziswiler }; 621a39ed23bSMarcel Ziswiler 622a39ed23bSMarcel Ziswiler eeprom@50 { 623a39ed23bSMarcel Ziswiler compatible = "st,24c02"; 624a39ed23bSMarcel Ziswiler pagesize = <16>; 625a39ed23bSMarcel Ziswiler reg = <0x50>; 626a39ed23bSMarcel Ziswiler }; 627a39ed23bSMarcel Ziswiler}; 628a39ed23bSMarcel Ziswiler 629a39ed23bSMarcel Ziswiler/* Verdin I2C_2_DSI */ 630a39ed23bSMarcel Ziswiler&i2c2 { 631a39ed23bSMarcel Ziswiler /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ 632a39ed23bSMarcel Ziswiler clock-frequency = <10000>; 633a39ed23bSMarcel Ziswiler pinctrl-names = "default", "gpio"; 634a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_i2c2>; 635a39ed23bSMarcel Ziswiler pinctrl-1 = <&pinctrl_i2c2_gpio>; 636a39ed23bSMarcel Ziswiler scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 637a39ed23bSMarcel Ziswiler sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 638a39ed23bSMarcel Ziswiler 639a39ed23bSMarcel Ziswiler atmel_mxt_ts_mezzanine: touch-mezzanine@4a { 640a39ed23bSMarcel Ziswiler compatible = "atmel,maxtouch"; 641a39ed23bSMarcel Ziswiler /* Verdin GPIO_3 (SODIMM 210) */ 642a39ed23bSMarcel Ziswiler interrupt-parent = <&gpio1>; 643a39ed23bSMarcel Ziswiler interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 644a39ed23bSMarcel Ziswiler reg = <0x4a>; 645a39ed23bSMarcel Ziswiler /* Verdin GPIO_2 (SODIMM 208) */ 6468f143b9fSMarcel Ziswiler reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 647a39ed23bSMarcel Ziswiler status = "disabled"; 648a39ed23bSMarcel Ziswiler }; 649a39ed23bSMarcel Ziswiler}; 650a39ed23bSMarcel Ziswiler 651a39ed23bSMarcel Ziswiler/* TODO: Verdin I2C_3_HDMI */ 652a39ed23bSMarcel Ziswiler 653a39ed23bSMarcel Ziswiler/* Verdin I2C_4_CSI */ 654a39ed23bSMarcel Ziswiler&i2c3 { 655a39ed23bSMarcel Ziswiler clock-frequency = <400000>; 656a39ed23bSMarcel Ziswiler pinctrl-names = "default", "gpio"; 657a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_i2c3>; 658a39ed23bSMarcel Ziswiler pinctrl-1 = <&pinctrl_i2c3_gpio>; 659a39ed23bSMarcel Ziswiler scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 660a39ed23bSMarcel Ziswiler sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 661a39ed23bSMarcel Ziswiler}; 662a39ed23bSMarcel Ziswiler 663a39ed23bSMarcel Ziswiler/* Verdin I2C_1 */ 664a39ed23bSMarcel Ziswiler&i2c4 { 665a39ed23bSMarcel Ziswiler clock-frequency = <400000>; 666a39ed23bSMarcel Ziswiler pinctrl-names = "default", "gpio"; 667a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_i2c4>; 668a39ed23bSMarcel Ziswiler pinctrl-1 = <&pinctrl_i2c4_gpio>; 669a39ed23bSMarcel Ziswiler scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 670a39ed23bSMarcel Ziswiler sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 671a39ed23bSMarcel Ziswiler 672a39ed23bSMarcel Ziswiler gpio_expander_21: gpio-expander@21 { 673a39ed23bSMarcel Ziswiler compatible = "nxp,pcal6416"; 674a39ed23bSMarcel Ziswiler #gpio-cells = <2>; 675a39ed23bSMarcel Ziswiler gpio-controller; 676a39ed23bSMarcel Ziswiler reg = <0x21>; 677a39ed23bSMarcel Ziswiler vcc-supply = <®_3p3v>; 678a39ed23bSMarcel Ziswiler status = "disabled"; 679a39ed23bSMarcel Ziswiler }; 680a39ed23bSMarcel Ziswiler 681a39ed23bSMarcel Ziswiler lvds_ti_sn65dsi83: bridge@2c { 682a39ed23bSMarcel Ziswiler compatible = "ti,sn65dsi83"; 683a39ed23bSMarcel Ziswiler /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 684a39ed23bSMarcel Ziswiler /* Verdin GPIO_10_DSI (SODIMM 21) */ 685a39ed23bSMarcel Ziswiler enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 686a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 687a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_gpio_10_dsi>; 688a39ed23bSMarcel Ziswiler reg = <0x2c>; 689a39ed23bSMarcel Ziswiler status = "disabled"; 690a39ed23bSMarcel Ziswiler }; 691a39ed23bSMarcel Ziswiler 692a39ed23bSMarcel Ziswiler /* Current measurement into module VCC */ 693a39ed23bSMarcel Ziswiler hwmon: hwmon@40 { 694a39ed23bSMarcel Ziswiler compatible = "ti,ina219"; 695a39ed23bSMarcel Ziswiler reg = <0x40>; 696a39ed23bSMarcel Ziswiler shunt-resistor = <10000>; 697a39ed23bSMarcel Ziswiler status = "disabled"; 698a39ed23bSMarcel Ziswiler }; 699a39ed23bSMarcel Ziswiler 700a39ed23bSMarcel Ziswiler hdmi_lontium_lt8912: hdmi@48 { 701a39ed23bSMarcel Ziswiler compatible = "lontium,lt8912b"; 702a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 703a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; 704a39ed23bSMarcel Ziswiler reg = <0x48>; 705a39ed23bSMarcel Ziswiler /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 706a39ed23bSMarcel Ziswiler /* Verdin GPIO_10_DSI (SODIMM 21) */ 707a39ed23bSMarcel Ziswiler reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 708a39ed23bSMarcel Ziswiler status = "disabled"; 709a39ed23bSMarcel Ziswiler }; 710a39ed23bSMarcel Ziswiler 711a39ed23bSMarcel Ziswiler atmel_mxt_ts: touch@4a { 712a39ed23bSMarcel Ziswiler compatible = "atmel,maxtouch"; 713a39ed23bSMarcel Ziswiler /* 714a39ed23bSMarcel Ziswiler * Verdin GPIO_9_DSI 715a39ed23bSMarcel Ziswiler * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) 716a39ed23bSMarcel Ziswiler */ 717a39ed23bSMarcel Ziswiler interrupt-parent = <&gpio4>; 718a39ed23bSMarcel Ziswiler interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 719a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 720a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 721a39ed23bSMarcel Ziswiler reg = <0x4a>; 722a39ed23bSMarcel Ziswiler /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 7238f143b9fSMarcel Ziswiler reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 724a39ed23bSMarcel Ziswiler status = "disabled"; 725a39ed23bSMarcel Ziswiler }; 726a39ed23bSMarcel Ziswiler 727a39ed23bSMarcel Ziswiler /* Temperature sensor on carrier board */ 728a39ed23bSMarcel Ziswiler hwmon_temp: sensor@4f { 729a39ed23bSMarcel Ziswiler compatible = "ti,tmp75c"; 730a39ed23bSMarcel Ziswiler reg = <0x4f>; 731a39ed23bSMarcel Ziswiler status = "disabled"; 732a39ed23bSMarcel Ziswiler }; 733a39ed23bSMarcel Ziswiler 734a39ed23bSMarcel Ziswiler /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 735a39ed23bSMarcel Ziswiler eeprom_display_adapter: eeprom@50 { 736a39ed23bSMarcel Ziswiler compatible = "st,24c02"; 737a39ed23bSMarcel Ziswiler pagesize = <16>; 738a39ed23bSMarcel Ziswiler reg = <0x50>; 739a39ed23bSMarcel Ziswiler status = "disabled"; 740a39ed23bSMarcel Ziswiler }; 741a39ed23bSMarcel Ziswiler 742a39ed23bSMarcel Ziswiler /* EEPROM on carrier board */ 743a39ed23bSMarcel Ziswiler eeprom_carrier_board: eeprom@57 { 744a39ed23bSMarcel Ziswiler compatible = "st,24c02"; 745a39ed23bSMarcel Ziswiler pagesize = <16>; 746a39ed23bSMarcel Ziswiler reg = <0x57>; 747a39ed23bSMarcel Ziswiler status = "disabled"; 748a39ed23bSMarcel Ziswiler }; 749a39ed23bSMarcel Ziswiler}; 750a39ed23bSMarcel Ziswiler 751a39ed23bSMarcel Ziswiler/* TODO: Verdin PCIE_1 */ 752a39ed23bSMarcel Ziswiler 753a39ed23bSMarcel Ziswiler/* Verdin PWM_1 */ 754a39ed23bSMarcel Ziswiler&pwm1 { 755a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 756a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_pwm_1>; 757a39ed23bSMarcel Ziswiler #pwm-cells = <3>; 758a39ed23bSMarcel Ziswiler}; 759a39ed23bSMarcel Ziswiler 760a39ed23bSMarcel Ziswiler/* Verdin PWM_2 */ 761a39ed23bSMarcel Ziswiler&pwm2 { 762a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 763a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_pwm_2>; 764a39ed23bSMarcel Ziswiler #pwm-cells = <3>; 765a39ed23bSMarcel Ziswiler}; 766a39ed23bSMarcel Ziswiler 767a39ed23bSMarcel Ziswiler/* Verdin PWM_3_DSI */ 768a39ed23bSMarcel Ziswiler&pwm3 { 769a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 770a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_pwm_3>; 771a39ed23bSMarcel Ziswiler #pwm-cells = <3>; 772a39ed23bSMarcel Ziswiler}; 773a39ed23bSMarcel Ziswiler 774a39ed23bSMarcel Ziswiler/* TODO: Verdin I2S_1 */ 775a39ed23bSMarcel Ziswiler 776a39ed23bSMarcel Ziswiler/* TODO: Verdin I2S_2 */ 777a39ed23bSMarcel Ziswiler 778a39ed23bSMarcel Ziswiler&snvs_pwrkey { 779a39ed23bSMarcel Ziswiler status = "okay"; 780a39ed23bSMarcel Ziswiler}; 781a39ed23bSMarcel Ziswiler 782a39ed23bSMarcel Ziswiler/* Verdin UART_1 */ 783a39ed23bSMarcel Ziswiler&uart1 { 784a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 785a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_uart1>; 78683b41ad1SFabio Estevam uart-has-rtscts; 787a39ed23bSMarcel Ziswiler}; 788a39ed23bSMarcel Ziswiler 789a39ed23bSMarcel Ziswiler/* Verdin UART_2 */ 790a39ed23bSMarcel Ziswiler&uart2 { 791a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 792a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_uart2>; 79383b41ad1SFabio Estevam uart-has-rtscts; 794a39ed23bSMarcel Ziswiler}; 795a39ed23bSMarcel Ziswiler 796a39ed23bSMarcel Ziswiler/* Verdin UART_3, used as the Linux Console */ 797a39ed23bSMarcel Ziswiler&uart3 { 798a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 799a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_uart3>; 800a39ed23bSMarcel Ziswiler}; 801a39ed23bSMarcel Ziswiler 802a39ed23bSMarcel Ziswiler/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */ 803a39ed23bSMarcel Ziswiler&uart4 { 804a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 805a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_uart4>; 806a39ed23bSMarcel Ziswiler}; 807a39ed23bSMarcel Ziswiler 808a39ed23bSMarcel Ziswiler/* Verdin USB_1 */ 809a39ed23bSMarcel Ziswiler&usb3_phy0 { 810a39ed23bSMarcel Ziswiler vbus-supply = <®_usb1_vbus>; 811a39ed23bSMarcel Ziswiler}; 812a39ed23bSMarcel Ziswiler 813a39ed23bSMarcel Ziswiler&usb_dwc3_0 { 814a39ed23bSMarcel Ziswiler adp-disable; 815a39ed23bSMarcel Ziswiler dr_mode = "otg"; 816a39ed23bSMarcel Ziswiler hnp-disable; 817a39ed23bSMarcel Ziswiler maximum-speed = "high-speed"; 818a39ed23bSMarcel Ziswiler over-current-active-low; 819a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 820a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_usb_1_id>; 821a39ed23bSMarcel Ziswiler srp-disable; 822a39ed23bSMarcel Ziswiler}; 823a39ed23bSMarcel Ziswiler 824a39ed23bSMarcel Ziswiler/* Verdin USB_2 */ 825a39ed23bSMarcel Ziswiler&usb3_phy1 { 826a39ed23bSMarcel Ziswiler vbus-supply = <®_usb2_vbus>; 827a39ed23bSMarcel Ziswiler}; 828a39ed23bSMarcel Ziswiler 829a39ed23bSMarcel Ziswiler&usb_dwc3_1 { 830a39ed23bSMarcel Ziswiler disable-over-current; 831a39ed23bSMarcel Ziswiler dr_mode = "host"; 832a39ed23bSMarcel Ziswiler}; 833a39ed23bSMarcel Ziswiler 834a39ed23bSMarcel Ziswiler/* Verdin SD_1 */ 835a39ed23bSMarcel Ziswiler&usdhc2 { 836a39ed23bSMarcel Ziswiler assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 837a39ed23bSMarcel Ziswiler assigned-clock-rates = <400000000>; 838a39ed23bSMarcel Ziswiler bus-width = <4>; 839a39ed23bSMarcel Ziswiler cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 840a39ed23bSMarcel Ziswiler disable-wp; 841a39ed23bSMarcel Ziswiler pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 842a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 843a39ed23bSMarcel Ziswiler pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 844a39ed23bSMarcel Ziswiler pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 845a39ed23bSMarcel Ziswiler pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 846a39ed23bSMarcel Ziswiler vmmc-supply = <®_usdhc2_vmmc>; 847a39ed23bSMarcel Ziswiler}; 848a39ed23bSMarcel Ziswiler 849a39ed23bSMarcel Ziswiler/* On-module eMMC */ 850a39ed23bSMarcel Ziswiler&usdhc3 { 851a39ed23bSMarcel Ziswiler assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; 852a39ed23bSMarcel Ziswiler assigned-clock-rates = <400000000>; 853a39ed23bSMarcel Ziswiler bus-width = <8>; 854a39ed23bSMarcel Ziswiler non-removable; 855a39ed23bSMarcel Ziswiler pinctrl-names = "default", "state_100mhz", "state_200mhz"; 856a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_usdhc3>; 857a39ed23bSMarcel Ziswiler pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 858a39ed23bSMarcel Ziswiler pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 859a39ed23bSMarcel Ziswiler status = "okay"; 860a39ed23bSMarcel Ziswiler}; 861a39ed23bSMarcel Ziswiler 862a39ed23bSMarcel Ziswiler&wdog1 { 863a39ed23bSMarcel Ziswiler fsl,ext-reset-output; 864a39ed23bSMarcel Ziswiler pinctrl-names = "default"; 865a39ed23bSMarcel Ziswiler pinctrl-0 = <&pinctrl_wdog>; 866a39ed23bSMarcel Ziswiler status = "okay"; 867a39ed23bSMarcel Ziswiler}; 868a39ed23bSMarcel Ziswiler 869a39ed23bSMarcel Ziswiler&iomuxc { 870a39ed23bSMarcel Ziswiler pinctrl_bt_uart: btuartgrp { 871a39ed23bSMarcel Ziswiler fsl,pins = 872a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>, 873a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>, 874a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>, 875a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>; 876a39ed23bSMarcel Ziswiler }; 877a39ed23bSMarcel Ziswiler 878a39ed23bSMarcel Ziswiler pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 879a39ed23bSMarcel Ziswiler fsl,pins = 880a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */ 881a39ed23bSMarcel Ziswiler }; 882a39ed23bSMarcel Ziswiler 883a39ed23bSMarcel Ziswiler pinctrl_ecspi1: ecspi1grp { 884a39ed23bSMarcel Ziswiler fsl,pins = 885a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */ 886a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */ 887a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */ 888a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */ 889a39ed23bSMarcel Ziswiler }; 890a39ed23bSMarcel Ziswiler 891a39ed23bSMarcel Ziswiler /* Connection On Board PHY */ 892a39ed23bSMarcel Ziswiler pinctrl_eqos: eqosgrp { 893a39ed23bSMarcel Ziswiler fsl,pins = 894a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>, 895a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>, 896a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>, 897a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>, 898a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>, 899a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>, 900a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>, 901a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>, 902a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>, 903a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>, 904a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>, 905a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>, 906a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>, 907a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>; 908a39ed23bSMarcel Ziswiler }; 909a39ed23bSMarcel Ziswiler 910a39ed23bSMarcel Ziswiler /* ETH_INT# shared with TPM_INT# (usually N/A) */ 911a39ed23bSMarcel Ziswiler pinctrl_eth_tpm_int: ethtpmintgrp { 912a39ed23bSMarcel Ziswiler fsl,pins = 913a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>; 914a39ed23bSMarcel Ziswiler }; 915a39ed23bSMarcel Ziswiler 916a39ed23bSMarcel Ziswiler /* Connection Carrier Board PHY ETH_2 */ 917a39ed23bSMarcel Ziswiler pinctrl_fec: fecgrp { 918a39ed23bSMarcel Ziswiler fsl,pins = 919a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ 920a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ 921a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ 922a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ 923a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ 924a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ 925a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ 926a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ 927a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */ 928a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */ 929a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */ 930a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */ 931a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */ 932a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */ 933a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */ 934a39ed23bSMarcel Ziswiler }; 935a39ed23bSMarcel Ziswiler 936a39ed23bSMarcel Ziswiler pinctrl_fec_sleep: fecsleepgrp { 937a39ed23bSMarcel Ziswiler fsl,pins = 938a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ 939a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ 940a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ 941a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ 942a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ 943a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ 944a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ 945a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ 946a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */ 947a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */ 948a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */ 949a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */ 950a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */ 951a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */ 952a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */ 953a39ed23bSMarcel Ziswiler }; 954a39ed23bSMarcel Ziswiler 955a39ed23bSMarcel Ziswiler pinctrl_flexcan1: flexcan1grp { 956a39ed23bSMarcel Ziswiler fsl,pins = 957a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */ 958a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */ 959a39ed23bSMarcel Ziswiler }; 960a39ed23bSMarcel Ziswiler 961a39ed23bSMarcel Ziswiler pinctrl_flexcan2: flexcan2grp { 962a39ed23bSMarcel Ziswiler fsl,pins = 963a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */ 964a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */ 965a39ed23bSMarcel Ziswiler }; 966a39ed23bSMarcel Ziswiler 967a39ed23bSMarcel Ziswiler pinctrl_flexspi0: flexspi0grp { 968a39ed23bSMarcel Ziswiler fsl,pins = 969a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */ 970a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */ 971a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */ 972a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */ 973a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */ 974a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */ 975a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */ 976a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */ 977a39ed23bSMarcel Ziswiler }; 978a39ed23bSMarcel Ziswiler 979a39ed23bSMarcel Ziswiler pinctrl_gpio1: gpio1grp { 980a39ed23bSMarcel Ziswiler fsl,pins = 981a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */ 982a39ed23bSMarcel Ziswiler }; 983a39ed23bSMarcel Ziswiler 984a39ed23bSMarcel Ziswiler pinctrl_gpio2: gpio2grp { 985a39ed23bSMarcel Ziswiler fsl,pins = 986a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */ 987a39ed23bSMarcel Ziswiler }; 988a39ed23bSMarcel Ziswiler 989a39ed23bSMarcel Ziswiler pinctrl_gpio3: gpio3grp { 990a39ed23bSMarcel Ziswiler fsl,pins = 991a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */ 992a39ed23bSMarcel Ziswiler }; 993a39ed23bSMarcel Ziswiler 994a39ed23bSMarcel Ziswiler pinctrl_gpio4: gpio4grp { 995a39ed23bSMarcel Ziswiler fsl,pins = 996a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */ 997a39ed23bSMarcel Ziswiler }; 998a39ed23bSMarcel Ziswiler 999a39ed23bSMarcel Ziswiler pinctrl_gpio5: gpio5grp { 1000a39ed23bSMarcel Ziswiler fsl,pins = 1001a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */ 1002a39ed23bSMarcel Ziswiler }; 1003a39ed23bSMarcel Ziswiler 1004a39ed23bSMarcel Ziswiler pinctrl_gpio6: gpio6grp { 1005a39ed23bSMarcel Ziswiler fsl,pins = 1006a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */ 1007a39ed23bSMarcel Ziswiler }; 1008a39ed23bSMarcel Ziswiler 1009a39ed23bSMarcel Ziswiler pinctrl_gpio7: gpio7grp { 1010a39ed23bSMarcel Ziswiler fsl,pins = 1011a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */ 1012a39ed23bSMarcel Ziswiler }; 1013a39ed23bSMarcel Ziswiler 1014a39ed23bSMarcel Ziswiler pinctrl_gpio8: gpio8grp { 1015a39ed23bSMarcel Ziswiler fsl,pins = 1016a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */ 1017a39ed23bSMarcel Ziswiler }; 1018a39ed23bSMarcel Ziswiler 1019a39ed23bSMarcel Ziswiler /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 1020a39ed23bSMarcel Ziswiler pinctrl_gpio_9_dsi: gpio9dsigrp { 1021a39ed23bSMarcel Ziswiler fsl,pins = 1022a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */ 1023a39ed23bSMarcel Ziswiler }; 1024a39ed23bSMarcel Ziswiler 1025a39ed23bSMarcel Ziswiler /* Verdin GPIO_10_DSI */ 1026a39ed23bSMarcel Ziswiler pinctrl_gpio_10_dsi: gpio10dsigrp { 1027a39ed23bSMarcel Ziswiler fsl,pins = 1028a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */ 1029a39ed23bSMarcel Ziswiler }; 1030a39ed23bSMarcel Ziswiler 1031a39ed23bSMarcel Ziswiler /* Non-wifi MSP usage only */ 1032a39ed23bSMarcel Ziswiler pinctrl_gpio_hog1: gpiohog1grp { 1033a39ed23bSMarcel Ziswiler fsl,pins = 1034a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */ 1035a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */ 1036a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */ 1037a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */ 1038a39ed23bSMarcel Ziswiler }; 1039a39ed23bSMarcel Ziswiler 1040a39ed23bSMarcel Ziswiler /* USB_2_OC# */ 1041a39ed23bSMarcel Ziswiler pinctrl_gpio_hog2: gpiohog2grp { 1042a39ed23bSMarcel Ziswiler fsl,pins = 1043a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */ 1044a39ed23bSMarcel Ziswiler }; 1045a39ed23bSMarcel Ziswiler 1046a39ed23bSMarcel Ziswiler pinctrl_gpio_hog3: gpiohog3grp { 1047a39ed23bSMarcel Ziswiler fsl,pins = 1048a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */ 1049a39ed23bSMarcel Ziswiler /* CSI_1_MCLK */ 1050a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */ 1051a39ed23bSMarcel Ziswiler }; 1052a39ed23bSMarcel Ziswiler 1053a39ed23bSMarcel Ziswiler /* Wifi usage only */ 1054a39ed23bSMarcel Ziswiler pinctrl_gpio_hog4: gpiohog4grp { 1055a39ed23bSMarcel Ziswiler fsl,pins = 1056a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */ 1057a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */ 1058a39ed23bSMarcel Ziswiler }; 1059a39ed23bSMarcel Ziswiler 1060a39ed23bSMarcel Ziswiler pinctrl_gpio_keys: gpiokeysgrp { 1061a39ed23bSMarcel Ziswiler fsl,pins = 1062a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */ 1063a39ed23bSMarcel Ziswiler }; 1064a39ed23bSMarcel Ziswiler 1065a39ed23bSMarcel Ziswiler pinctrl_hdmi_hog: hdmihoggrp { 1066a39ed23bSMarcel Ziswiler fsl,pins = 1067a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */ 1068a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */ 1069a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */ 1070a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */ 1071a39ed23bSMarcel Ziswiler }; 1072a39ed23bSMarcel Ziswiler 1073a39ed23bSMarcel Ziswiler /* On-module I2C */ 1074a39ed23bSMarcel Ziswiler pinctrl_i2c1: i2c1grp { 1075a39ed23bSMarcel Ziswiler fsl,pins = 1076a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */ 1077a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */ 1078a39ed23bSMarcel Ziswiler }; 1079a39ed23bSMarcel Ziswiler 1080a39ed23bSMarcel Ziswiler pinctrl_i2c1_gpio: i2c1gpiogrp { 1081a39ed23bSMarcel Ziswiler fsl,pins = 1082a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */ 1083a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */ 1084a39ed23bSMarcel Ziswiler }; 1085a39ed23bSMarcel Ziswiler 1086a39ed23bSMarcel Ziswiler /* Verdin I2C_2_DSI */ 1087a39ed23bSMarcel Ziswiler pinctrl_i2c2: i2c2grp { 1088a39ed23bSMarcel Ziswiler fsl,pins = 1089a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */ 1090a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */ 1091a39ed23bSMarcel Ziswiler }; 1092a39ed23bSMarcel Ziswiler 1093a39ed23bSMarcel Ziswiler pinctrl_i2c2_gpio: i2c2gpiogrp { 1094a39ed23bSMarcel Ziswiler fsl,pins = 1095a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */ 1096a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */ 1097a39ed23bSMarcel Ziswiler }; 1098a39ed23bSMarcel Ziswiler 1099a39ed23bSMarcel Ziswiler /* Verdin I2C_4_CSI */ 1100a39ed23bSMarcel Ziswiler pinctrl_i2c3: i2c3grp { 1101a39ed23bSMarcel Ziswiler fsl,pins = 1102a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */ 1103a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */ 1104a39ed23bSMarcel Ziswiler }; 1105a39ed23bSMarcel Ziswiler 1106a39ed23bSMarcel Ziswiler pinctrl_i2c3_gpio: i2c3gpiogrp { 1107a39ed23bSMarcel Ziswiler fsl,pins = 1108a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */ 1109a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */ 1110a39ed23bSMarcel Ziswiler }; 1111a39ed23bSMarcel Ziswiler 1112a39ed23bSMarcel Ziswiler /* Verdin I2C_1 */ 1113a39ed23bSMarcel Ziswiler pinctrl_i2c4: i2c4grp { 1114a39ed23bSMarcel Ziswiler fsl,pins = 1115a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */ 1116a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */ 1117a39ed23bSMarcel Ziswiler }; 1118a39ed23bSMarcel Ziswiler 1119a39ed23bSMarcel Ziswiler pinctrl_i2c4_gpio: i2c4gpiogrp { 1120a39ed23bSMarcel Ziswiler fsl,pins = 1121a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */ 1122a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */ 1123a39ed23bSMarcel Ziswiler }; 1124a39ed23bSMarcel Ziswiler 1125a39ed23bSMarcel Ziswiler /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1126a39ed23bSMarcel Ziswiler pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1127a39ed23bSMarcel Ziswiler fsl,pins = 1128a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */ 1129a39ed23bSMarcel Ziswiler }; 1130a39ed23bSMarcel Ziswiler 1131a39ed23bSMarcel Ziswiler /* Verdin I2S_2_D_OUT shared with SAI3 */ 1132a39ed23bSMarcel Ziswiler pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1133a39ed23bSMarcel Ziswiler fsl,pins = 1134a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */ 1135a39ed23bSMarcel Ziswiler }; 1136a39ed23bSMarcel Ziswiler 1137a39ed23bSMarcel Ziswiler pinctrl_pcie: pciegrp { 1138a39ed23bSMarcel Ziswiler fsl,pins = 1139a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */ 1140a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */ 1141a39ed23bSMarcel Ziswiler }; 1142a39ed23bSMarcel Ziswiler 1143a39ed23bSMarcel Ziswiler pinctrl_pmic: pmicirqgrp { 1144a39ed23bSMarcel Ziswiler fsl,pins = 1145a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */ 1146a39ed23bSMarcel Ziswiler }; 1147a39ed23bSMarcel Ziswiler 1148a39ed23bSMarcel Ziswiler pinctrl_pwm_1: pwm1grp { 1149a39ed23bSMarcel Ziswiler fsl,pins = 1150a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */ 1151a39ed23bSMarcel Ziswiler }; 1152a39ed23bSMarcel Ziswiler 1153a39ed23bSMarcel Ziswiler pinctrl_pwm_2: pwm2grp { 1154a39ed23bSMarcel Ziswiler fsl,pins = 1155a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */ 1156a39ed23bSMarcel Ziswiler }; 1157a39ed23bSMarcel Ziswiler 1158a39ed23bSMarcel Ziswiler /* Verdin PWM_3_DSI shared with GPIO3_IO20 */ 1159a39ed23bSMarcel Ziswiler pinctrl_pwm_3: pwm3grp { 1160a39ed23bSMarcel Ziswiler fsl,pins = 1161a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */ 1162a39ed23bSMarcel Ziswiler }; 1163a39ed23bSMarcel Ziswiler 1164a39ed23bSMarcel Ziswiler /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */ 1165a39ed23bSMarcel Ziswiler pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp { 1166a39ed23bSMarcel Ziswiler fsl,pins = 1167a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */ 1168a39ed23bSMarcel Ziswiler }; 1169a39ed23bSMarcel Ziswiler 1170a39ed23bSMarcel Ziswiler pinctrl_reg_eth: regethgrp { 1171a39ed23bSMarcel Ziswiler fsl,pins = 1172a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */ 1173a39ed23bSMarcel Ziswiler }; 1174a39ed23bSMarcel Ziswiler 1175a39ed23bSMarcel Ziswiler pinctrl_sai1: sai1grp { 1176a39ed23bSMarcel Ziswiler fsl,pins = 1177a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */ 1178a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */ 1179a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */ 1180a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */ 1181a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */ 1182a39ed23bSMarcel Ziswiler }; 1183a39ed23bSMarcel Ziswiler 1184a39ed23bSMarcel Ziswiler pinctrl_sai3: sai3grp { 1185a39ed23bSMarcel Ziswiler fsl,pins = 1186a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */ 1187a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */ 1188a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */ 1189a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */ 1190a39ed23bSMarcel Ziswiler }; 1191a39ed23bSMarcel Ziswiler 1192a39ed23bSMarcel Ziswiler pinctrl_uart1: uart1grp { 1193a39ed23bSMarcel Ziswiler fsl,pins = 1194a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */ 1195a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */ 1196a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */ 1197a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */ 1198a39ed23bSMarcel Ziswiler }; 1199a39ed23bSMarcel Ziswiler 1200a39ed23bSMarcel Ziswiler pinctrl_uart2: uart2grp { 1201a39ed23bSMarcel Ziswiler fsl,pins = 1202a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */ 1203a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */ 1204a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */ 1205a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */ 1206a39ed23bSMarcel Ziswiler }; 1207a39ed23bSMarcel Ziswiler 1208a39ed23bSMarcel Ziswiler pinctrl_uart3: uart3grp { 1209a39ed23bSMarcel Ziswiler fsl,pins = 1210a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */ 1211a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */ 1212a39ed23bSMarcel Ziswiler }; 1213a39ed23bSMarcel Ziswiler 1214a39ed23bSMarcel Ziswiler /* Non-wifi usage only */ 1215a39ed23bSMarcel Ziswiler pinctrl_uart4: uart4grp { 1216a39ed23bSMarcel Ziswiler fsl,pins = 1217a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */ 1218a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */ 1219a39ed23bSMarcel Ziswiler }; 1220a39ed23bSMarcel Ziswiler 1221a39ed23bSMarcel Ziswiler pinctrl_usb1_vbus: usb1vbusgrp { 1222a39ed23bSMarcel Ziswiler fsl,pins = 1223a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */ 1224a39ed23bSMarcel Ziswiler }; 1225a39ed23bSMarcel Ziswiler 1226a39ed23bSMarcel Ziswiler /* USB_1_ID */ 1227a39ed23bSMarcel Ziswiler pinctrl_usb_1_id: usb1idgrp { 1228a39ed23bSMarcel Ziswiler fsl,pins = 1229a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */ 1230a39ed23bSMarcel Ziswiler }; 1231a39ed23bSMarcel Ziswiler 1232a39ed23bSMarcel Ziswiler pinctrl_usb2_vbus: usb2vbusgrp { 1233a39ed23bSMarcel Ziswiler fsl,pins = 1234a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */ 1235a39ed23bSMarcel Ziswiler }; 1236a39ed23bSMarcel Ziswiler 1237a39ed23bSMarcel Ziswiler /* On-module Wi-Fi */ 1238a39ed23bSMarcel Ziswiler pinctrl_usdhc1: usdhc1grp { 1239a39ed23bSMarcel Ziswiler fsl,pins = 1240a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, 1241a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, 1242a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, 1243a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, 1244a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, 1245a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; 1246a39ed23bSMarcel Ziswiler }; 1247a39ed23bSMarcel Ziswiler 1248a39ed23bSMarcel Ziswiler pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1249a39ed23bSMarcel Ziswiler fsl,pins = 1250a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, 1251a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, 1252a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, 1253a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, 1254a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, 1255a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; 1256a39ed23bSMarcel Ziswiler }; 1257a39ed23bSMarcel Ziswiler 1258a39ed23bSMarcel Ziswiler pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1259a39ed23bSMarcel Ziswiler fsl,pins = 1260a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, 1261a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, 1262a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, 1263a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, 1264a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, 1265a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; 1266a39ed23bSMarcel Ziswiler }; 1267a39ed23bSMarcel Ziswiler 1268a39ed23bSMarcel Ziswiler pinctrl_usdhc2_cd: usdhc2cdgrp { 1269a39ed23bSMarcel Ziswiler fsl,pins = 1270a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */ 1271a39ed23bSMarcel Ziswiler }; 1272a39ed23bSMarcel Ziswiler 1273a39ed23bSMarcel Ziswiler pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1274a39ed23bSMarcel Ziswiler fsl,pins = 1275a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */ 1276a39ed23bSMarcel Ziswiler }; 1277a39ed23bSMarcel Ziswiler 1278a39ed23bSMarcel Ziswiler pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1279a39ed23bSMarcel Ziswiler fsl,pins = 1280a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */ 1281a39ed23bSMarcel Ziswiler }; 1282a39ed23bSMarcel Ziswiler 1283a39ed23bSMarcel Ziswiler pinctrl_usdhc2: usdhc2grp { 1284a39ed23bSMarcel Ziswiler fsl,pins = 1285a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */ 1286a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */ 1287a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */ 1288a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */ 1289a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */ 1290a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */ 1291a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */ 1292a39ed23bSMarcel Ziswiler }; 1293a39ed23bSMarcel Ziswiler 1294a39ed23bSMarcel Ziswiler pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1295a39ed23bSMarcel Ziswiler fsl,pins = 1296a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, 1297a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 1298a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 1299a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1300a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1301a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1302a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1303a39ed23bSMarcel Ziswiler }; 1304a39ed23bSMarcel Ziswiler 1305a39ed23bSMarcel Ziswiler pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1306a39ed23bSMarcel Ziswiler fsl,pins = 1307a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, 1308a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, 1309a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, 1310a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, 1311a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, 1312a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, 1313a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; 1314a39ed23bSMarcel Ziswiler }; 1315a39ed23bSMarcel Ziswiler 1316a39ed23bSMarcel Ziswiler /* Avoid backfeeding with removed card power */ 1317a39ed23bSMarcel Ziswiler pinctrl_usdhc2_sleep: usdhc2slpgrp { 1318a39ed23bSMarcel Ziswiler fsl,pins = 1319a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>, 1320a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, 1321a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, 1322a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, 1323a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, 1324a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, 1325a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; 1326a39ed23bSMarcel Ziswiler }; 1327a39ed23bSMarcel Ziswiler 1328a39ed23bSMarcel Ziswiler pinctrl_usdhc3: usdhc3grp { 1329a39ed23bSMarcel Ziswiler fsl,pins = 1330a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1331a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, 1332a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, 1333a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, 1334a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, 1335a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, 1336a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, 1337a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, 1338a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, 1339a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, 1340a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, 1341a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; 1342a39ed23bSMarcel Ziswiler }; 1343a39ed23bSMarcel Ziswiler 1344a39ed23bSMarcel Ziswiler pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1345a39ed23bSMarcel Ziswiler fsl,pins = 1346a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1347a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, 1348a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 1349a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 1350a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 1351a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 1352a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 1353a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 1354a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 1355a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 1356a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 1357a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; 1358a39ed23bSMarcel Ziswiler }; 1359a39ed23bSMarcel Ziswiler 1360a39ed23bSMarcel Ziswiler pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1361a39ed23bSMarcel Ziswiler fsl,pins = 1362a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1363a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, 1364a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, 1365a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, 1366a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, 1367a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, 1368a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, 1369a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, 1370a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, 1371a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, 1372a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, 1373a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; 1374a39ed23bSMarcel Ziswiler }; 1375a39ed23bSMarcel Ziswiler 1376a39ed23bSMarcel Ziswiler pinctrl_wdog: wdoggrp { 1377a39ed23bSMarcel Ziswiler fsl,pins = 1378a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */ 1379a39ed23bSMarcel Ziswiler }; 1380a39ed23bSMarcel Ziswiler 1381a39ed23bSMarcel Ziswiler pinctrl_bluetooth_ctrl: bluetoothctrlgrp { 1382a39ed23bSMarcel Ziswiler fsl,pins = 1383a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */ 1384a39ed23bSMarcel Ziswiler }; 1385a39ed23bSMarcel Ziswiler 1386a39ed23bSMarcel Ziswiler pinctrl_wifi_ctrl: wifictrlgrp { 1387a39ed23bSMarcel Ziswiler fsl,pins = 1388a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */ 1389a39ed23bSMarcel Ziswiler }; 1390a39ed23bSMarcel Ziswiler 1391a39ed23bSMarcel Ziswiler pinctrl_wifi_i2s: wifii2sgrp { 1392a39ed23bSMarcel Ziswiler fsl,pins = 1393a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */ 1394a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */ 1395a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */ 1396a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */ 1397a39ed23bSMarcel Ziswiler }; 1398a39ed23bSMarcel Ziswiler 1399a39ed23bSMarcel Ziswiler pinctrl_wifi_pwr_en: wifipwrengrp { 1400a39ed23bSMarcel Ziswiler fsl,pins = 1401a39ed23bSMarcel Ziswiler <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */ 1402a39ed23bSMarcel Ziswiler }; 1403a39ed23bSMarcel Ziswiler}; 1404