1*0d5b288cSTim Harvey// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*0d5b288cSTim Harvey/* 3*0d5b288cSTim Harvey * Copyright 2023 Gateworks Corporation 4*0d5b288cSTim Harvey */ 5*0d5b288cSTim Harvey 6*0d5b288cSTim Harvey#include <dt-bindings/gpio/gpio.h> 7*0d5b288cSTim Harvey#include <dt-bindings/input/linux-event-codes.h> 8*0d5b288cSTim Harvey#include <dt-bindings/net/ti-dp83867.h> 9*0d5b288cSTim Harvey 10*0d5b288cSTim Harvey/ { 11*0d5b288cSTim Harvey aliases { 12*0d5b288cSTim Harvey ethernet0 = &eqos; 13*0d5b288cSTim Harvey }; 14*0d5b288cSTim Harvey 15*0d5b288cSTim Harvey memory@40000000 { 16*0d5b288cSTim Harvey device_type = "memory"; 17*0d5b288cSTim Harvey reg = <0x0 0x40000000 0 0x80000000>; 18*0d5b288cSTim Harvey }; 19*0d5b288cSTim Harvey 20*0d5b288cSTim Harvey gpio-keys { 21*0d5b288cSTim Harvey compatible = "gpio-keys"; 22*0d5b288cSTim Harvey 23*0d5b288cSTim Harvey key-user-pb { 24*0d5b288cSTim Harvey label = "user_pb"; 25*0d5b288cSTim Harvey gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 26*0d5b288cSTim Harvey linux,code = <BTN_0>; 27*0d5b288cSTim Harvey }; 28*0d5b288cSTim Harvey 29*0d5b288cSTim Harvey key-user-pb1x { 30*0d5b288cSTim Harvey label = "user_pb1x"; 31*0d5b288cSTim Harvey linux,code = <BTN_1>; 32*0d5b288cSTim Harvey interrupt-parent = <&gsc>; 33*0d5b288cSTim Harvey interrupts = <0>; 34*0d5b288cSTim Harvey }; 35*0d5b288cSTim Harvey 36*0d5b288cSTim Harvey key-erased { 37*0d5b288cSTim Harvey label = "key_erased"; 38*0d5b288cSTim Harvey linux,code = <BTN_2>; 39*0d5b288cSTim Harvey interrupt-parent = <&gsc>; 40*0d5b288cSTim Harvey interrupts = <1>; 41*0d5b288cSTim Harvey }; 42*0d5b288cSTim Harvey 43*0d5b288cSTim Harvey key-eeprom-wp { 44*0d5b288cSTim Harvey label = "eeprom_wp"; 45*0d5b288cSTim Harvey linux,code = <BTN_3>; 46*0d5b288cSTim Harvey interrupt-parent = <&gsc>; 47*0d5b288cSTim Harvey interrupts = <2>; 48*0d5b288cSTim Harvey }; 49*0d5b288cSTim Harvey 50*0d5b288cSTim Harvey key-tamper { 51*0d5b288cSTim Harvey label = "tamper"; 52*0d5b288cSTim Harvey linux,code = <BTN_4>; 53*0d5b288cSTim Harvey interrupt-parent = <&gsc>; 54*0d5b288cSTim Harvey interrupts = <5>; 55*0d5b288cSTim Harvey }; 56*0d5b288cSTim Harvey 57*0d5b288cSTim Harvey switch-hold { 58*0d5b288cSTim Harvey label = "switch_hold"; 59*0d5b288cSTim Harvey linux,code = <BTN_5>; 60*0d5b288cSTim Harvey interrupt-parent = <&gsc>; 61*0d5b288cSTim Harvey interrupts = <7>; 62*0d5b288cSTim Harvey }; 63*0d5b288cSTim Harvey }; 64*0d5b288cSTim Harvey}; 65*0d5b288cSTim Harvey 66*0d5b288cSTim Harvey&A53_0 { 67*0d5b288cSTim Harvey cpu-supply = <&buck3_reg>; 68*0d5b288cSTim Harvey}; 69*0d5b288cSTim Harvey 70*0d5b288cSTim Harvey&A53_1 { 71*0d5b288cSTim Harvey cpu-supply = <&buck3_reg>; 72*0d5b288cSTim Harvey}; 73*0d5b288cSTim Harvey 74*0d5b288cSTim Harvey&A53_2 { 75*0d5b288cSTim Harvey cpu-supply = <&buck3_reg>; 76*0d5b288cSTim Harvey}; 77*0d5b288cSTim Harvey 78*0d5b288cSTim Harvey&A53_3 { 79*0d5b288cSTim Harvey cpu-supply = <&buck3_reg>; 80*0d5b288cSTim Harvey}; 81*0d5b288cSTim Harvey 82*0d5b288cSTim Harvey&eqos { 83*0d5b288cSTim Harvey pinctrl-names = "default"; 84*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_eqos>; 85*0d5b288cSTim Harvey phy-mode = "rgmii-id"; 86*0d5b288cSTim Harvey phy-handle = <ðphy0>; 87*0d5b288cSTim Harvey status = "okay"; 88*0d5b288cSTim Harvey 89*0d5b288cSTim Harvey mdio { 90*0d5b288cSTim Harvey compatible = "snps,dwmac-mdio"; 91*0d5b288cSTim Harvey #address-cells = <1>; 92*0d5b288cSTim Harvey #size-cells = <0>; 93*0d5b288cSTim Harvey 94*0d5b288cSTim Harvey ethphy0: ethernet-phy@0 { 95*0d5b288cSTim Harvey compatible = "ethernet-phy-ieee802.3-c22"; 96*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_ethphy0>; 97*0d5b288cSTim Harvey pinctrl-names = "default"; 98*0d5b288cSTim Harvey reg = <0x0>; 99*0d5b288cSTim Harvey interrupt-parent = <&gpio3>; 100*0d5b288cSTim Harvey interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 101*0d5b288cSTim Harvey ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 102*0d5b288cSTim Harvey ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 103*0d5b288cSTim Harvey tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 104*0d5b288cSTim Harvey rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 105*0d5b288cSTim Harvey }; 106*0d5b288cSTim Harvey }; 107*0d5b288cSTim Harvey}; 108*0d5b288cSTim Harvey 109*0d5b288cSTim Harvey&i2c1 { 110*0d5b288cSTim Harvey clock-frequency = <100000>; 111*0d5b288cSTim Harvey pinctrl-names = "default", "gpio"; 112*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_i2c1>; 113*0d5b288cSTim Harvey pinctrl-1 = <&pinctrl_i2c1_gpio>; 114*0d5b288cSTim Harvey scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 115*0d5b288cSTim Harvey sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 116*0d5b288cSTim Harvey status = "okay"; 117*0d5b288cSTim Harvey 118*0d5b288cSTim Harvey gsc: gsc@20 { 119*0d5b288cSTim Harvey compatible = "gw,gsc"; 120*0d5b288cSTim Harvey reg = <0x20>; 121*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_gsc>; 122*0d5b288cSTim Harvey interrupt-parent = <&gpio2>; 123*0d5b288cSTim Harvey interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 124*0d5b288cSTim Harvey interrupt-controller; 125*0d5b288cSTim Harvey #interrupt-cells = <1>; 126*0d5b288cSTim Harvey #address-cells = <1>; 127*0d5b288cSTim Harvey #size-cells = <0>; 128*0d5b288cSTim Harvey 129*0d5b288cSTim Harvey adc { 130*0d5b288cSTim Harvey compatible = "gw,gsc-adc"; 131*0d5b288cSTim Harvey #address-cells = <1>; 132*0d5b288cSTim Harvey #size-cells = <0>; 133*0d5b288cSTim Harvey 134*0d5b288cSTim Harvey channel@6 { 135*0d5b288cSTim Harvey gw,mode = <0>; 136*0d5b288cSTim Harvey reg = <0x06>; 137*0d5b288cSTim Harvey label = "temp"; 138*0d5b288cSTim Harvey }; 139*0d5b288cSTim Harvey 140*0d5b288cSTim Harvey channel@8 { 141*0d5b288cSTim Harvey gw,mode = <1>; 142*0d5b288cSTim Harvey reg = <0x08>; 143*0d5b288cSTim Harvey label = "vdd_bat"; 144*0d5b288cSTim Harvey }; 145*0d5b288cSTim Harvey 146*0d5b288cSTim Harvey channel@16 { 147*0d5b288cSTim Harvey gw,mode = <4>; 148*0d5b288cSTim Harvey reg = <0x16>; 149*0d5b288cSTim Harvey label = "fan_tach"; 150*0d5b288cSTim Harvey }; 151*0d5b288cSTim Harvey 152*0d5b288cSTim Harvey channel@82 { 153*0d5b288cSTim Harvey gw,mode = <2>; 154*0d5b288cSTim Harvey reg = <0x82>; 155*0d5b288cSTim Harvey label = "vdd_vin"; 156*0d5b288cSTim Harvey gw,voltage-divider-ohms = <22100 1000>; 157*0d5b288cSTim Harvey }; 158*0d5b288cSTim Harvey 159*0d5b288cSTim Harvey channel@84 { 160*0d5b288cSTim Harvey gw,mode = <2>; 161*0d5b288cSTim Harvey reg = <0x84>; 162*0d5b288cSTim Harvey label = "vdd_adc1"; 163*0d5b288cSTim Harvey gw,voltage-divider-ohms = <10000 10000>; 164*0d5b288cSTim Harvey }; 165*0d5b288cSTim Harvey 166*0d5b288cSTim Harvey channel@86 { 167*0d5b288cSTim Harvey gw,mode = <2>; 168*0d5b288cSTim Harvey reg = <0x86>; 169*0d5b288cSTim Harvey label = "vdd_adc2"; 170*0d5b288cSTim Harvey gw,voltage-divider-ohms = <10000 10000>; 171*0d5b288cSTim Harvey }; 172*0d5b288cSTim Harvey 173*0d5b288cSTim Harvey channel@88 { 174*0d5b288cSTim Harvey gw,mode = <2>; 175*0d5b288cSTim Harvey reg = <0x88>; 176*0d5b288cSTim Harvey label = "vdd_1p0"; 177*0d5b288cSTim Harvey }; 178*0d5b288cSTim Harvey 179*0d5b288cSTim Harvey channel@8c { 180*0d5b288cSTim Harvey gw,mode = <2>; 181*0d5b288cSTim Harvey reg = <0x8c>; 182*0d5b288cSTim Harvey label = "vdd_1p8"; 183*0d5b288cSTim Harvey }; 184*0d5b288cSTim Harvey 185*0d5b288cSTim Harvey channel@8e { 186*0d5b288cSTim Harvey gw,mode = <2>; 187*0d5b288cSTim Harvey reg = <0x8e>; 188*0d5b288cSTim Harvey label = "vdd_2p5"; 189*0d5b288cSTim Harvey }; 190*0d5b288cSTim Harvey 191*0d5b288cSTim Harvey channel@90 { 192*0d5b288cSTim Harvey gw,mode = <2>; 193*0d5b288cSTim Harvey reg = <0x90>; 194*0d5b288cSTim Harvey label = "vdd_3p3"; 195*0d5b288cSTim Harvey gw,voltage-divider-ohms = <10000 10000>; 196*0d5b288cSTim Harvey }; 197*0d5b288cSTim Harvey 198*0d5b288cSTim Harvey channel@92 { 199*0d5b288cSTim Harvey gw,mode = <2>; 200*0d5b288cSTim Harvey reg = <0x92>; 201*0d5b288cSTim Harvey label = "vdd_dram"; 202*0d5b288cSTim Harvey }; 203*0d5b288cSTim Harvey 204*0d5b288cSTim Harvey channel@98 { 205*0d5b288cSTim Harvey gw,mode = <2>; 206*0d5b288cSTim Harvey reg = <0x98>; 207*0d5b288cSTim Harvey label = "vdd_soc"; 208*0d5b288cSTim Harvey }; 209*0d5b288cSTim Harvey 210*0d5b288cSTim Harvey channel@9a { 211*0d5b288cSTim Harvey gw,mode = <2>; 212*0d5b288cSTim Harvey reg = <0x9a>; 213*0d5b288cSTim Harvey label = "vdd_arm"; 214*0d5b288cSTim Harvey }; 215*0d5b288cSTim Harvey 216*0d5b288cSTim Harvey channel@a2 { 217*0d5b288cSTim Harvey gw,mode = <2>; 218*0d5b288cSTim Harvey reg = <0xa2>; 219*0d5b288cSTim Harvey label = "vdd_gsc"; 220*0d5b288cSTim Harvey gw,voltage-divider-ohms = <10000 10000>; 221*0d5b288cSTim Harvey }; 222*0d5b288cSTim Harvey }; 223*0d5b288cSTim Harvey 224*0d5b288cSTim Harvey fan-controller@0 { 225*0d5b288cSTim Harvey compatible = "gw,gsc-fan"; 226*0d5b288cSTim Harvey reg = <0x0a>; 227*0d5b288cSTim Harvey }; 228*0d5b288cSTim Harvey }; 229*0d5b288cSTim Harvey 230*0d5b288cSTim Harvey gpio: gpio@23 { 231*0d5b288cSTim Harvey compatible = "nxp,pca9555"; 232*0d5b288cSTim Harvey reg = <0x23>; 233*0d5b288cSTim Harvey gpio-controller; 234*0d5b288cSTim Harvey #gpio-cells = <2>; 235*0d5b288cSTim Harvey interrupt-parent = <&gsc>; 236*0d5b288cSTim Harvey interrupts = <4>; 237*0d5b288cSTim Harvey }; 238*0d5b288cSTim Harvey 239*0d5b288cSTim Harvey eeprom@50 { 240*0d5b288cSTim Harvey compatible = "atmel,24c02"; 241*0d5b288cSTim Harvey reg = <0x50>; 242*0d5b288cSTim Harvey pagesize = <16>; 243*0d5b288cSTim Harvey }; 244*0d5b288cSTim Harvey 245*0d5b288cSTim Harvey eeprom@51 { 246*0d5b288cSTim Harvey compatible = "atmel,24c02"; 247*0d5b288cSTim Harvey reg = <0x51>; 248*0d5b288cSTim Harvey pagesize = <16>; 249*0d5b288cSTim Harvey }; 250*0d5b288cSTim Harvey 251*0d5b288cSTim Harvey eeprom@52 { 252*0d5b288cSTim Harvey compatible = "atmel,24c02"; 253*0d5b288cSTim Harvey reg = <0x52>; 254*0d5b288cSTim Harvey pagesize = <16>; 255*0d5b288cSTim Harvey }; 256*0d5b288cSTim Harvey 257*0d5b288cSTim Harvey eeprom@53 { 258*0d5b288cSTim Harvey compatible = "atmel,24c02"; 259*0d5b288cSTim Harvey reg = <0x53>; 260*0d5b288cSTim Harvey pagesize = <16>; 261*0d5b288cSTim Harvey }; 262*0d5b288cSTim Harvey 263*0d5b288cSTim Harvey rtc@68 { 264*0d5b288cSTim Harvey compatible = "dallas,ds1672"; 265*0d5b288cSTim Harvey reg = <0x68>; 266*0d5b288cSTim Harvey }; 267*0d5b288cSTim Harvey 268*0d5b288cSTim Harvey pmic@69 { 269*0d5b288cSTim Harvey compatible = "mps,mp5416"; 270*0d5b288cSTim Harvey reg = <0x69>; 271*0d5b288cSTim Harvey 272*0d5b288cSTim Harvey regulators { 273*0d5b288cSTim Harvey /* vdd_soc */ 274*0d5b288cSTim Harvey buck1 { 275*0d5b288cSTim Harvey regulator-name = "buck1"; 276*0d5b288cSTim Harvey regulator-min-microvolt = <850000>; 277*0d5b288cSTim Harvey regulator-max-microvolt = <1000000>; 278*0d5b288cSTim Harvey regulator-always-on; 279*0d5b288cSTim Harvey regulator-boot-on; 280*0d5b288cSTim Harvey }; 281*0d5b288cSTim Harvey 282*0d5b288cSTim Harvey /* vdd_dram */ 283*0d5b288cSTim Harvey buck2 { 284*0d5b288cSTim Harvey regulator-name = "buck2"; 285*0d5b288cSTim Harvey regulator-min-microvolt = <1100000>; 286*0d5b288cSTim Harvey regulator-max-microvolt = <1100000>; 287*0d5b288cSTim Harvey regulator-always-on; 288*0d5b288cSTim Harvey regulator-boot-on; 289*0d5b288cSTim Harvey }; 290*0d5b288cSTim Harvey 291*0d5b288cSTim Harvey /* vdd_arm */ 292*0d5b288cSTim Harvey buck3_reg: buck3 { 293*0d5b288cSTim Harvey regulator-name = "buck3"; 294*0d5b288cSTim Harvey regulator-min-microvolt = <850000>; 295*0d5b288cSTim Harvey regulator-max-microvolt = <1000000>; 296*0d5b288cSTim Harvey regulator-always-on; 297*0d5b288cSTim Harvey regulator-boot-on; 298*0d5b288cSTim Harvey }; 299*0d5b288cSTim Harvey 300*0d5b288cSTim Harvey /* vdd_1p8 */ 301*0d5b288cSTim Harvey buck4 { 302*0d5b288cSTim Harvey regulator-name = "buck4"; 303*0d5b288cSTim Harvey regulator-min-microvolt = <1800000>; 304*0d5b288cSTim Harvey regulator-max-microvolt = <1800000>; 305*0d5b288cSTim Harvey regulator-always-on; 306*0d5b288cSTim Harvey regulator-boot-on; 307*0d5b288cSTim Harvey }; 308*0d5b288cSTim Harvey 309*0d5b288cSTim Harvey /* OUT2: nvcc_snvs_1p8 */ 310*0d5b288cSTim Harvey ldo1 { 311*0d5b288cSTim Harvey regulator-name = "ldo1"; 312*0d5b288cSTim Harvey regulator-min-microvolt = <1800000>; 313*0d5b288cSTim Harvey regulator-max-microvolt = <1800000>; 314*0d5b288cSTim Harvey regulator-always-on; 315*0d5b288cSTim Harvey regulator-boot-on; 316*0d5b288cSTim Harvey }; 317*0d5b288cSTim Harvey 318*0d5b288cSTim Harvey /* OUT3: vdd_1p0 */ 319*0d5b288cSTim Harvey ldo2 { 320*0d5b288cSTim Harvey regulator-name = "ldo2"; 321*0d5b288cSTim Harvey regulator-min-microvolt = <1000000>; 322*0d5b288cSTim Harvey regulator-max-microvolt = <1000000>; 323*0d5b288cSTim Harvey regulator-always-on; 324*0d5b288cSTim Harvey regulator-boot-on; 325*0d5b288cSTim Harvey }; 326*0d5b288cSTim Harvey 327*0d5b288cSTim Harvey /* OUT4: vdd_2p5 */ 328*0d5b288cSTim Harvey ldo3 { 329*0d5b288cSTim Harvey regulator-name = "ldo3"; 330*0d5b288cSTim Harvey regulator-min-microvolt = <2500000>; 331*0d5b288cSTim Harvey regulator-max-microvolt = <2500000>; 332*0d5b288cSTim Harvey regulator-always-on; 333*0d5b288cSTim Harvey regulator-boot-on; 334*0d5b288cSTim Harvey }; 335*0d5b288cSTim Harvey 336*0d5b288cSTim Harvey /* OUT5: vdd_3p3 */ 337*0d5b288cSTim Harvey ldo4 { 338*0d5b288cSTim Harvey regulator-name = "ldo4"; 339*0d5b288cSTim Harvey regulator-min-microvolt = <3300000>; 340*0d5b288cSTim Harvey regulator-max-microvolt = <3300000>; 341*0d5b288cSTim Harvey regulator-always-on; 342*0d5b288cSTim Harvey regulator-boot-on; 343*0d5b288cSTim Harvey }; 344*0d5b288cSTim Harvey }; 345*0d5b288cSTim Harvey }; 346*0d5b288cSTim Harvey}; 347*0d5b288cSTim Harvey 348*0d5b288cSTim Harvey/* off-board header */ 349*0d5b288cSTim Harvey&i2c2 { 350*0d5b288cSTim Harvey clock-frequency = <400000>; 351*0d5b288cSTim Harvey pinctrl-names = "default", "gpio"; 352*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_i2c2>; 353*0d5b288cSTim Harvey pinctrl-1 = <&pinctrl_i2c2_gpio>; 354*0d5b288cSTim Harvey scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 355*0d5b288cSTim Harvey sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 356*0d5b288cSTim Harvey status = "okay"; 357*0d5b288cSTim Harvey 358*0d5b288cSTim Harvey eeprom@52 { 359*0d5b288cSTim Harvey compatible = "atmel,24c32"; 360*0d5b288cSTim Harvey reg = <0x52>; 361*0d5b288cSTim Harvey pagesize = <32>; 362*0d5b288cSTim Harvey }; 363*0d5b288cSTim Harvey}; 364*0d5b288cSTim Harvey 365*0d5b288cSTim Harvey/* off-board header */ 366*0d5b288cSTim Harvey&i2c3 { 367*0d5b288cSTim Harvey clock-frequency = <400000>; 368*0d5b288cSTim Harvey pinctrl-names = "default", "gpio"; 369*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_i2c3>; 370*0d5b288cSTim Harvey pinctrl-1 = <&pinctrl_i2c3_gpio>; 371*0d5b288cSTim Harvey scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 372*0d5b288cSTim Harvey sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 373*0d5b288cSTim Harvey status = "okay"; 374*0d5b288cSTim Harvey}; 375*0d5b288cSTim Harvey 376*0d5b288cSTim Harvey/* off-board header */ 377*0d5b288cSTim Harvey&uart1 { 378*0d5b288cSTim Harvey pinctrl-names = "default"; 379*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_uart1>; 380*0d5b288cSTim Harvey status = "okay"; 381*0d5b288cSTim Harvey}; 382*0d5b288cSTim Harvey 383*0d5b288cSTim Harvey/* console */ 384*0d5b288cSTim Harvey&uart2 { 385*0d5b288cSTim Harvey pinctrl-names = "default"; 386*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_uart2>; 387*0d5b288cSTim Harvey status = "okay"; 388*0d5b288cSTim Harvey}; 389*0d5b288cSTim Harvey 390*0d5b288cSTim Harvey/* off-board header */ 391*0d5b288cSTim Harvey&uart3 { 392*0d5b288cSTim Harvey pinctrl-names = "default"; 393*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_uart3>; 394*0d5b288cSTim Harvey status = "okay"; 395*0d5b288cSTim Harvey}; 396*0d5b288cSTim Harvey 397*0d5b288cSTim Harvey/* off-board */ 398*0d5b288cSTim Harvey&usdhc1 { 399*0d5b288cSTim Harvey pinctrl-names = "default"; 400*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_usdhc1>; 401*0d5b288cSTim Harvey bus-width = <4>; 402*0d5b288cSTim Harvey non-removable; 403*0d5b288cSTim Harvey status = "okay"; 404*0d5b288cSTim Harvey bus-width = <4>; 405*0d5b288cSTim Harvey non-removable; 406*0d5b288cSTim Harvey status = "okay"; 407*0d5b288cSTim Harvey}; 408*0d5b288cSTim Harvey 409*0d5b288cSTim Harvey/* eMMC */ 410*0d5b288cSTim Harvey&usdhc3 { 411*0d5b288cSTim Harvey pinctrl-names = "default", "state_100mhz", "state_200mhz"; 412*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_usdhc3>; 413*0d5b288cSTim Harvey pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 414*0d5b288cSTim Harvey pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 415*0d5b288cSTim Harvey bus-width = <8>; 416*0d5b288cSTim Harvey non-removable; 417*0d5b288cSTim Harvey status = "okay"; 418*0d5b288cSTim Harvey}; 419*0d5b288cSTim Harvey 420*0d5b288cSTim Harvey&wdog1 { 421*0d5b288cSTim Harvey pinctrl-names = "default"; 422*0d5b288cSTim Harvey pinctrl-0 = <&pinctrl_wdog>; 423*0d5b288cSTim Harvey fsl,ext-reset-output; 424*0d5b288cSTim Harvey status = "okay"; 425*0d5b288cSTim Harvey}; 426*0d5b288cSTim Harvey 427*0d5b288cSTim Harvey&iomuxc { 428*0d5b288cSTim Harvey pinctrl_eqos: eqosgrp { 429*0d5b288cSTim Harvey fsl,pins = < 430*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 431*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 432*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 433*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 434*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 435*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 436*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 437*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 438*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 439*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 440*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 441*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 442*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 443*0d5b288cSTim Harvey MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 444*0d5b288cSTim Harvey >; 445*0d5b288cSTim Harvey }; 446*0d5b288cSTim Harvey 447*0d5b288cSTim Harvey pinctrl_ethphy0: ethphy0grp { 448*0d5b288cSTim Harvey fsl,pins = < 449*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */ 450*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */ 451*0d5b288cSTim Harvey >; 452*0d5b288cSTim Harvey }; 453*0d5b288cSTim Harvey 454*0d5b288cSTim Harvey pinctrl_gsc: gscgrp { 455*0d5b288cSTim Harvey fsl,pins = < 456*0d5b288cSTim Harvey MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */ 457*0d5b288cSTim Harvey >; 458*0d5b288cSTim Harvey }; 459*0d5b288cSTim Harvey 460*0d5b288cSTim Harvey pinctrl_i2c1: i2c1grp { 461*0d5b288cSTim Harvey fsl,pins = < 462*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 463*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 464*0d5b288cSTim Harvey >; 465*0d5b288cSTim Harvey }; 466*0d5b288cSTim Harvey 467*0d5b288cSTim Harvey pinctrl_i2c1_gpio: i2c1gpiogrp { 468*0d5b288cSTim Harvey fsl,pins = < 469*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 470*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 471*0d5b288cSTim Harvey >; 472*0d5b288cSTim Harvey }; 473*0d5b288cSTim Harvey 474*0d5b288cSTim Harvey pinctrl_i2c2: i2c2grp { 475*0d5b288cSTim Harvey fsl,pins = < 476*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 477*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 478*0d5b288cSTim Harvey >; 479*0d5b288cSTim Harvey }; 480*0d5b288cSTim Harvey 481*0d5b288cSTim Harvey pinctrl_i2c2_gpio: i2c2gpiogrp { 482*0d5b288cSTim Harvey fsl,pins = < 483*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 484*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 485*0d5b288cSTim Harvey >; 486*0d5b288cSTim Harvey }; 487*0d5b288cSTim Harvey 488*0d5b288cSTim Harvey pinctrl_i2c3: i2c3grp { 489*0d5b288cSTim Harvey fsl,pins = < 490*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 491*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 492*0d5b288cSTim Harvey >; 493*0d5b288cSTim Harvey }; 494*0d5b288cSTim Harvey 495*0d5b288cSTim Harvey pinctrl_i2c3_gpio: i2c3gpiogrp { 496*0d5b288cSTim Harvey fsl,pins = < 497*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 498*0d5b288cSTim Harvey MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 499*0d5b288cSTim Harvey >; 500*0d5b288cSTim Harvey }; 501*0d5b288cSTim Harvey 502*0d5b288cSTim Harvey pinctrl_uart1: uart1grp { 503*0d5b288cSTim Harvey fsl,pins = < 504*0d5b288cSTim Harvey MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 505*0d5b288cSTim Harvey MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 506*0d5b288cSTim Harvey >; 507*0d5b288cSTim Harvey }; 508*0d5b288cSTim Harvey 509*0d5b288cSTim Harvey pinctrl_uart2: uart2grp { 510*0d5b288cSTim Harvey fsl,pins = < 511*0d5b288cSTim Harvey MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 512*0d5b288cSTim Harvey MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 513*0d5b288cSTim Harvey >; 514*0d5b288cSTim Harvey }; 515*0d5b288cSTim Harvey 516*0d5b288cSTim Harvey pinctrl_uart3: uart3grp { 517*0d5b288cSTim Harvey fsl,pins = < 518*0d5b288cSTim Harvey MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 519*0d5b288cSTim Harvey MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 520*0d5b288cSTim Harvey >; 521*0d5b288cSTim Harvey }; 522*0d5b288cSTim Harvey 523*0d5b288cSTim Harvey pinctrl_usdhc1: usdhc1grp { 524*0d5b288cSTim Harvey fsl,pins = < 525*0d5b288cSTim Harvey MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 526*0d5b288cSTim Harvey MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 527*0d5b288cSTim Harvey MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 528*0d5b288cSTim Harvey MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 529*0d5b288cSTim Harvey MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 530*0d5b288cSTim Harvey MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 531*0d5b288cSTim Harvey >; 532*0d5b288cSTim Harvey }; 533*0d5b288cSTim Harvey 534*0d5b288cSTim Harvey pinctrl_usdhc3: usdhc3grp { 535*0d5b288cSTim Harvey fsl,pins = < 536*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 537*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 538*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 539*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 540*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 541*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 542*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 543*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 544*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 545*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 546*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 547*0d5b288cSTim Harvey >; 548*0d5b288cSTim Harvey }; 549*0d5b288cSTim Harvey 550*0d5b288cSTim Harvey pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 551*0d5b288cSTim Harvey fsl,pins = < 552*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 553*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 554*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 555*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 556*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 557*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 558*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 559*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 560*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 561*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 562*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 563*0d5b288cSTim Harvey >; 564*0d5b288cSTim Harvey }; 565*0d5b288cSTim Harvey 566*0d5b288cSTim Harvey pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 567*0d5b288cSTim Harvey fsl,pins = < 568*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 569*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 570*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 571*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 572*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 573*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 574*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 575*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 576*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 577*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 578*0d5b288cSTim Harvey MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 579*0d5b288cSTim Harvey >; 580*0d5b288cSTim Harvey }; 581*0d5b288cSTim Harvey 582*0d5b288cSTim Harvey pinctrl_wdog: wdoggrp { 583*0d5b288cSTim Harvey fsl,pins = < 584*0d5b288cSTim Harvey MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 585*0d5b288cSTim Harvey >; 586*0d5b288cSTim Harvey }; 587*0d5b288cSTim Harvey}; 588